1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 */ 24 #include <linux/firmware.h> 25 #include <drm/drmP.h> 26 #include "amdgpu.h" 27 #include "amdgpu_ucode.h" 28 #include "amdgpu_trace.h" 29 #include "vi.h" 30 #include "vid.h" 31 32 #include "oss/oss_2_4_d.h" 33 #include "oss/oss_2_4_sh_mask.h" 34 35 #include "gmc/gmc_8_1_d.h" 36 #include "gmc/gmc_8_1_sh_mask.h" 37 38 #include "gca/gfx_8_0_d.h" 39 #include "gca/gfx_8_0_enum.h" 40 #include "gca/gfx_8_0_sh_mask.h" 41 42 #include "bif/bif_5_0_d.h" 43 #include "bif/bif_5_0_sh_mask.h" 44 45 #include "iceland_sdma_pkt_open.h" 46 47 static void sdma_v2_4_set_ring_funcs(struct amdgpu_device *adev); 48 static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device *adev); 49 static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev); 50 static void sdma_v2_4_set_irq_funcs(struct amdgpu_device *adev); 51 52 MODULE_FIRMWARE("amdgpu/topaz_sdma.bin"); 53 MODULE_FIRMWARE("amdgpu/topaz_sdma1.bin"); 54 55 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] = 56 { 57 SDMA0_REGISTER_OFFSET, 58 SDMA1_REGISTER_OFFSET 59 }; 60 61 static const u32 golden_settings_iceland_a11[] = 62 { 63 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, 64 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, 65 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, 66 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, 67 }; 68 69 static const u32 iceland_mgcg_cgcg_init[] = 70 { 71 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, 72 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 73 }; 74 75 /* 76 * sDMA - System DMA 77 * Starting with CIK, the GPU has new asynchronous 78 * DMA engines. These engines are used for compute 79 * and gfx. There are two DMA engines (SDMA0, SDMA1) 80 * and each one supports 1 ring buffer used for gfx 81 * and 2 queues used for compute. 82 * 83 * The programming model is very similar to the CP 84 * (ring buffer, IBs, etc.), but sDMA has it's own 85 * packet format that is different from the PM4 format 86 * used by the CP. sDMA supports copying data, writing 87 * embedded data, solid fills, and a number of other 88 * things. It also has support for tiling/detiling of 89 * buffers. 90 */ 91 92 static void sdma_v2_4_init_golden_registers(struct amdgpu_device *adev) 93 { 94 switch (adev->asic_type) { 95 case CHIP_TOPAZ: 96 amdgpu_program_register_sequence(adev, 97 iceland_mgcg_cgcg_init, 98 (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init)); 99 amdgpu_program_register_sequence(adev, 100 golden_settings_iceland_a11, 101 (const u32)ARRAY_SIZE(golden_settings_iceland_a11)); 102 break; 103 default: 104 break; 105 } 106 } 107 108 /** 109 * sdma_v2_4_init_microcode - load ucode images from disk 110 * 111 * @adev: amdgpu_device pointer 112 * 113 * Use the firmware interface to load the ucode images into 114 * the driver (not loaded into hw). 115 * Returns 0 on success, error on failure. 116 */ 117 static int sdma_v2_4_init_microcode(struct amdgpu_device *adev) 118 { 119 const char *chip_name; 120 char fw_name[30]; 121 int err = 0, i; 122 struct amdgpu_firmware_info *info = NULL; 123 const struct common_firmware_header *header = NULL; 124 const struct sdma_firmware_header_v1_0 *hdr; 125 126 DRM_DEBUG("\n"); 127 128 switch (adev->asic_type) { 129 case CHIP_TOPAZ: 130 chip_name = "topaz"; 131 break; 132 default: BUG(); 133 } 134 135 for (i = 0; i < adev->sdma.num_instances; i++) { 136 if (i == 0) 137 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name); 138 else 139 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name); 140 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev); 141 if (err) 142 goto out; 143 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw); 144 if (err) 145 goto out; 146 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 147 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version); 148 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version); 149 if (adev->sdma.instance[i].feature_version >= 20) 150 adev->sdma.instance[i].burst_nop = true; 151 152 if (adev->firmware.smu_load) { 153 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i]; 154 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i; 155 info->fw = adev->sdma.instance[i].fw; 156 header = (const struct common_firmware_header *)info->fw->data; 157 adev->firmware.fw_size += 158 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 159 } 160 } 161 162 out: 163 if (err) { 164 printk(KERN_ERR 165 "sdma_v2_4: Failed to load firmware \"%s\"\n", 166 fw_name); 167 for (i = 0; i < adev->sdma.num_instances; i++) { 168 release_firmware(adev->sdma.instance[i].fw); 169 adev->sdma.instance[i].fw = NULL; 170 } 171 } 172 return err; 173 } 174 175 /** 176 * sdma_v2_4_ring_get_rptr - get the current read pointer 177 * 178 * @ring: amdgpu ring pointer 179 * 180 * Get the current rptr from the hardware (VI+). 181 */ 182 static uint32_t sdma_v2_4_ring_get_rptr(struct amdgpu_ring *ring) 183 { 184 u32 rptr; 185 186 /* XXX check if swapping is necessary on BE */ 187 rptr = ring->adev->wb.wb[ring->rptr_offs] >> 2; 188 189 return rptr; 190 } 191 192 /** 193 * sdma_v2_4_ring_get_wptr - get the current write pointer 194 * 195 * @ring: amdgpu ring pointer 196 * 197 * Get the current wptr from the hardware (VI+). 198 */ 199 static uint32_t sdma_v2_4_ring_get_wptr(struct amdgpu_ring *ring) 200 { 201 struct amdgpu_device *adev = ring->adev; 202 int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1; 203 u32 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) >> 2; 204 205 return wptr; 206 } 207 208 /** 209 * sdma_v2_4_ring_set_wptr - commit the write pointer 210 * 211 * @ring: amdgpu ring pointer 212 * 213 * Write the wptr back to the hardware (VI+). 214 */ 215 static void sdma_v2_4_ring_set_wptr(struct amdgpu_ring *ring) 216 { 217 struct amdgpu_device *adev = ring->adev; 218 int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1; 219 220 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], ring->wptr << 2); 221 } 222 223 static void sdma_v2_4_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 224 { 225 struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring); 226 int i; 227 228 for (i = 0; i < count; i++) 229 if (sdma && sdma->burst_nop && (i == 0)) 230 amdgpu_ring_write(ring, ring->nop | 231 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 232 else 233 amdgpu_ring_write(ring, ring->nop); 234 } 235 236 /** 237 * sdma_v2_4_ring_emit_ib - Schedule an IB on the DMA engine 238 * 239 * @ring: amdgpu ring pointer 240 * @ib: IB object to schedule 241 * 242 * Schedule an IB in the DMA ring (VI). 243 */ 244 static void sdma_v2_4_ring_emit_ib(struct amdgpu_ring *ring, 245 struct amdgpu_ib *ib) 246 { 247 u32 vmid = (ib->vm ? ib->vm->ids[ring->idx].id : 0) & 0xf; 248 u32 next_rptr = ring->wptr + 5; 249 250 while ((next_rptr & 7) != 2) 251 next_rptr++; 252 253 next_rptr += 6; 254 255 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 256 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 257 amdgpu_ring_write(ring, lower_32_bits(ring->next_rptr_gpu_addr) & 0xfffffffc); 258 amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr)); 259 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1)); 260 amdgpu_ring_write(ring, next_rptr); 261 262 /* IB packet must end on a 8 DW boundary */ 263 sdma_v2_4_ring_insert_nop(ring, (10 - (ring->wptr & 7)) % 8); 264 265 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 266 SDMA_PKT_INDIRECT_HEADER_VMID(vmid)); 267 /* base must be 32 byte aligned */ 268 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 269 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 270 amdgpu_ring_write(ring, ib->length_dw); 271 amdgpu_ring_write(ring, 0); 272 amdgpu_ring_write(ring, 0); 273 274 } 275 276 /** 277 * sdma_v2_4_hdp_flush_ring_emit - emit an hdp flush on the DMA ring 278 * 279 * @ring: amdgpu ring pointer 280 * 281 * Emit an hdp flush packet on the requested DMA ring. 282 */ 283 static void sdma_v2_4_ring_emit_hdp_flush(struct amdgpu_ring *ring) 284 { 285 u32 ref_and_mask = 0; 286 287 if (ring == &ring->adev->sdma.instance[0].ring) 288 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1); 289 else 290 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1); 291 292 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 293 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) | 294 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 295 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2); 296 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2); 297 amdgpu_ring_write(ring, ref_and_mask); /* reference */ 298 amdgpu_ring_write(ring, ref_and_mask); /* mask */ 299 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 300 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 301 } 302 303 /** 304 * sdma_v2_4_ring_emit_fence - emit a fence on the DMA ring 305 * 306 * @ring: amdgpu ring pointer 307 * @fence: amdgpu fence object 308 * 309 * Add a DMA fence packet to the ring to write 310 * the fence seq number and DMA trap packet to generate 311 * an interrupt if needed (VI). 312 */ 313 static void sdma_v2_4_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 314 unsigned flags) 315 { 316 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 317 /* write the fence */ 318 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 319 amdgpu_ring_write(ring, lower_32_bits(addr)); 320 amdgpu_ring_write(ring, upper_32_bits(addr)); 321 amdgpu_ring_write(ring, lower_32_bits(seq)); 322 323 /* optionally write high bits as well */ 324 if (write64bit) { 325 addr += 4; 326 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 327 amdgpu_ring_write(ring, lower_32_bits(addr)); 328 amdgpu_ring_write(ring, upper_32_bits(addr)); 329 amdgpu_ring_write(ring, upper_32_bits(seq)); 330 } 331 332 /* generate an interrupt */ 333 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); 334 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); 335 } 336 337 /** 338 * sdma_v2_4_gfx_stop - stop the gfx async dma engines 339 * 340 * @adev: amdgpu_device pointer 341 * 342 * Stop the gfx async dma ring buffers (VI). 343 */ 344 static void sdma_v2_4_gfx_stop(struct amdgpu_device *adev) 345 { 346 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring; 347 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring; 348 u32 rb_cntl, ib_cntl; 349 int i; 350 351 if ((adev->mman.buffer_funcs_ring == sdma0) || 352 (adev->mman.buffer_funcs_ring == sdma1)) 353 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size); 354 355 for (i = 0; i < adev->sdma.num_instances; i++) { 356 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); 357 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); 358 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); 359 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); 360 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); 361 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); 362 } 363 sdma0->ready = false; 364 sdma1->ready = false; 365 } 366 367 /** 368 * sdma_v2_4_rlc_stop - stop the compute async dma engines 369 * 370 * @adev: amdgpu_device pointer 371 * 372 * Stop the compute async dma queues (VI). 373 */ 374 static void sdma_v2_4_rlc_stop(struct amdgpu_device *adev) 375 { 376 /* XXX todo */ 377 } 378 379 /** 380 * sdma_v2_4_enable - stop the async dma engines 381 * 382 * @adev: amdgpu_device pointer 383 * @enable: enable/disable the DMA MEs. 384 * 385 * Halt or unhalt the async dma engines (VI). 386 */ 387 static void sdma_v2_4_enable(struct amdgpu_device *adev, bool enable) 388 { 389 u32 f32_cntl; 390 int i; 391 392 if (enable == false) { 393 sdma_v2_4_gfx_stop(adev); 394 sdma_v2_4_rlc_stop(adev); 395 } 396 397 for (i = 0; i < adev->sdma.num_instances; i++) { 398 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]); 399 if (enable) 400 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0); 401 else 402 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1); 403 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl); 404 } 405 } 406 407 /** 408 * sdma_v2_4_gfx_resume - setup and start the async dma engines 409 * 410 * @adev: amdgpu_device pointer 411 * 412 * Set up the gfx DMA ring buffers and enable them (VI). 413 * Returns 0 for success, error for failure. 414 */ 415 static int sdma_v2_4_gfx_resume(struct amdgpu_device *adev) 416 { 417 struct amdgpu_ring *ring; 418 u32 rb_cntl, ib_cntl; 419 u32 rb_bufsz; 420 u32 wb_offset; 421 int i, j, r; 422 423 for (i = 0; i < adev->sdma.num_instances; i++) { 424 ring = &adev->sdma.instance[i].ring; 425 wb_offset = (ring->rptr_offs * 4); 426 427 mutex_lock(&adev->srbm_mutex); 428 for (j = 0; j < 16; j++) { 429 vi_srbm_select(adev, 0, 0, 0, j); 430 /* SDMA GFX */ 431 WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0); 432 WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0); 433 } 434 vi_srbm_select(adev, 0, 0, 0, 0); 435 mutex_unlock(&adev->srbm_mutex); 436 437 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0); 438 439 /* Set ring buffer size in dwords */ 440 rb_bufsz = order_base_2(ring->ring_size / 4); 441 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); 442 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); 443 #ifdef __BIG_ENDIAN 444 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); 445 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 446 RPTR_WRITEBACK_SWAP_ENABLE, 1); 447 #endif 448 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); 449 450 /* Initialize the ring buffer's read and write pointers */ 451 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0); 452 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0); 453 454 /* set the wb address whether it's enabled or not */ 455 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i], 456 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 457 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i], 458 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 459 460 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); 461 462 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8); 463 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40); 464 465 ring->wptr = 0; 466 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2); 467 468 /* enable DMA RB */ 469 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); 470 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); 471 472 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); 473 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); 474 #ifdef __BIG_ENDIAN 475 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); 476 #endif 477 /* enable DMA IBs */ 478 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); 479 480 ring->ready = true; 481 482 r = amdgpu_ring_test_ring(ring); 483 if (r) { 484 ring->ready = false; 485 return r; 486 } 487 488 if (adev->mman.buffer_funcs_ring == ring) 489 amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size); 490 } 491 492 return 0; 493 } 494 495 /** 496 * sdma_v2_4_rlc_resume - setup and start the async dma engines 497 * 498 * @adev: amdgpu_device pointer 499 * 500 * Set up the compute DMA queues and enable them (VI). 501 * Returns 0 for success, error for failure. 502 */ 503 static int sdma_v2_4_rlc_resume(struct amdgpu_device *adev) 504 { 505 /* XXX todo */ 506 return 0; 507 } 508 509 /** 510 * sdma_v2_4_load_microcode - load the sDMA ME ucode 511 * 512 * @adev: amdgpu_device pointer 513 * 514 * Loads the sDMA0/1 ucode. 515 * Returns 0 for success, -EINVAL if the ucode is not available. 516 */ 517 static int sdma_v2_4_load_microcode(struct amdgpu_device *adev) 518 { 519 const struct sdma_firmware_header_v1_0 *hdr; 520 const __le32 *fw_data; 521 u32 fw_size; 522 int i, j; 523 524 /* halt the MEs */ 525 sdma_v2_4_enable(adev, false); 526 527 for (i = 0; i < adev->sdma.num_instances; i++) { 528 if (!adev->sdma.instance[i].fw) 529 return -EINVAL; 530 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 531 amdgpu_ucode_print_sdma_hdr(&hdr->header); 532 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 533 fw_data = (const __le32 *) 534 (adev->sdma.instance[i].fw->data + 535 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 536 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0); 537 for (j = 0; j < fw_size; j++) 538 WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++)); 539 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version); 540 } 541 542 return 0; 543 } 544 545 /** 546 * sdma_v2_4_start - setup and start the async dma engines 547 * 548 * @adev: amdgpu_device pointer 549 * 550 * Set up the DMA engines and enable them (VI). 551 * Returns 0 for success, error for failure. 552 */ 553 static int sdma_v2_4_start(struct amdgpu_device *adev) 554 { 555 int r; 556 557 if (!adev->firmware.smu_load) { 558 r = sdma_v2_4_load_microcode(adev); 559 if (r) 560 return r; 561 } else { 562 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev, 563 AMDGPU_UCODE_ID_SDMA0); 564 if (r) 565 return -EINVAL; 566 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev, 567 AMDGPU_UCODE_ID_SDMA1); 568 if (r) 569 return -EINVAL; 570 } 571 572 /* unhalt the MEs */ 573 sdma_v2_4_enable(adev, true); 574 575 /* start the gfx rings and rlc compute queues */ 576 r = sdma_v2_4_gfx_resume(adev); 577 if (r) 578 return r; 579 r = sdma_v2_4_rlc_resume(adev); 580 if (r) 581 return r; 582 583 return 0; 584 } 585 586 /** 587 * sdma_v2_4_ring_test_ring - simple async dma engine test 588 * 589 * @ring: amdgpu_ring structure holding ring information 590 * 591 * Test the DMA engine by writing using it to write an 592 * value to memory. (VI). 593 * Returns 0 for success, error for failure. 594 */ 595 static int sdma_v2_4_ring_test_ring(struct amdgpu_ring *ring) 596 { 597 struct amdgpu_device *adev = ring->adev; 598 unsigned i; 599 unsigned index; 600 int r; 601 u32 tmp; 602 u64 gpu_addr; 603 604 r = amdgpu_wb_get(adev, &index); 605 if (r) { 606 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); 607 return r; 608 } 609 610 gpu_addr = adev->wb.gpu_addr + (index * 4); 611 tmp = 0xCAFEDEAD; 612 adev->wb.wb[index] = cpu_to_le32(tmp); 613 614 r = amdgpu_ring_alloc(ring, 5); 615 if (r) { 616 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r); 617 amdgpu_wb_free(adev, index); 618 return r; 619 } 620 621 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 622 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 623 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 624 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 625 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1)); 626 amdgpu_ring_write(ring, 0xDEADBEEF); 627 amdgpu_ring_commit(ring); 628 629 for (i = 0; i < adev->usec_timeout; i++) { 630 tmp = le32_to_cpu(adev->wb.wb[index]); 631 if (tmp == 0xDEADBEEF) 632 break; 633 DRM_UDELAY(1); 634 } 635 636 if (i < adev->usec_timeout) { 637 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); 638 } else { 639 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", 640 ring->idx, tmp); 641 r = -EINVAL; 642 } 643 amdgpu_wb_free(adev, index); 644 645 return r; 646 } 647 648 /** 649 * sdma_v2_4_ring_test_ib - test an IB on the DMA engine 650 * 651 * @ring: amdgpu_ring structure holding ring information 652 * 653 * Test a simple IB in the DMA ring (VI). 654 * Returns 0 on success, error on failure. 655 */ 656 static int sdma_v2_4_ring_test_ib(struct amdgpu_ring *ring) 657 { 658 struct amdgpu_device *adev = ring->adev; 659 struct amdgpu_ib ib; 660 struct fence *f = NULL; 661 unsigned i; 662 unsigned index; 663 int r; 664 u32 tmp = 0; 665 u64 gpu_addr; 666 667 r = amdgpu_wb_get(adev, &index); 668 if (r) { 669 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); 670 return r; 671 } 672 673 gpu_addr = adev->wb.gpu_addr + (index * 4); 674 tmp = 0xCAFEDEAD; 675 adev->wb.wb[index] = cpu_to_le32(tmp); 676 memset(&ib, 0, sizeof(ib)); 677 r = amdgpu_ib_get(ring, NULL, 256, &ib); 678 if (r) { 679 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r); 680 goto err0; 681 } 682 683 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 684 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 685 ib.ptr[1] = lower_32_bits(gpu_addr); 686 ib.ptr[2] = upper_32_bits(gpu_addr); 687 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1); 688 ib.ptr[4] = 0xDEADBEEF; 689 ib.ptr[5] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 690 ib.ptr[6] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 691 ib.ptr[7] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 692 ib.length_dw = 8; 693 694 r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, &ib, 1, NULL, 695 AMDGPU_FENCE_OWNER_UNDEFINED, 696 &f); 697 if (r) 698 goto err1; 699 700 r = fence_wait(f, false); 701 if (r) { 702 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r); 703 goto err1; 704 } 705 for (i = 0; i < adev->usec_timeout; i++) { 706 tmp = le32_to_cpu(adev->wb.wb[index]); 707 if (tmp == 0xDEADBEEF) 708 break; 709 DRM_UDELAY(1); 710 } 711 if (i < adev->usec_timeout) { 712 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", 713 ring->idx, i); 714 goto err1; 715 } else { 716 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp); 717 r = -EINVAL; 718 } 719 720 err1: 721 fence_put(f); 722 amdgpu_ib_free(adev, &ib); 723 err0: 724 amdgpu_wb_free(adev, index); 725 return r; 726 } 727 728 /** 729 * sdma_v2_4_vm_copy_pte - update PTEs by copying them from the GART 730 * 731 * @ib: indirect buffer to fill with commands 732 * @pe: addr of the page entry 733 * @src: src addr to copy from 734 * @count: number of page entries to update 735 * 736 * Update PTEs by copying them from the GART using sDMA (CIK). 737 */ 738 static void sdma_v2_4_vm_copy_pte(struct amdgpu_ib *ib, 739 uint64_t pe, uint64_t src, 740 unsigned count) 741 { 742 while (count) { 743 unsigned bytes = count * 8; 744 if (bytes > 0x1FFFF8) 745 bytes = 0x1FFFF8; 746 747 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 748 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 749 ib->ptr[ib->length_dw++] = bytes; 750 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 751 ib->ptr[ib->length_dw++] = lower_32_bits(src); 752 ib->ptr[ib->length_dw++] = upper_32_bits(src); 753 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 754 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 755 756 pe += bytes; 757 src += bytes; 758 count -= bytes / 8; 759 } 760 } 761 762 /** 763 * sdma_v2_4_vm_write_pte - update PTEs by writing them manually 764 * 765 * @ib: indirect buffer to fill with commands 766 * @pe: addr of the page entry 767 * @addr: dst addr to write into pe 768 * @count: number of page entries to update 769 * @incr: increase next addr by incr bytes 770 * @flags: access flags 771 * 772 * Update PTEs by writing them manually using sDMA (CIK). 773 */ 774 static void sdma_v2_4_vm_write_pte(struct amdgpu_ib *ib, 775 const dma_addr_t *pages_addr, uint64_t pe, 776 uint64_t addr, unsigned count, 777 uint32_t incr, uint32_t flags) 778 { 779 uint64_t value; 780 unsigned ndw; 781 782 while (count) { 783 ndw = count * 2; 784 if (ndw > 0xFFFFE) 785 ndw = 0xFFFFE; 786 787 /* for non-physically contiguous pages (system) */ 788 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 789 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 790 ib->ptr[ib->length_dw++] = pe; 791 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 792 ib->ptr[ib->length_dw++] = ndw; 793 for (; ndw > 0; ndw -= 2, --count, pe += 8) { 794 value = amdgpu_vm_map_gart(pages_addr, addr); 795 addr += incr; 796 value |= flags; 797 ib->ptr[ib->length_dw++] = value; 798 ib->ptr[ib->length_dw++] = upper_32_bits(value); 799 } 800 } 801 } 802 803 /** 804 * sdma_v2_4_vm_set_pte_pde - update the page tables using sDMA 805 * 806 * @ib: indirect buffer to fill with commands 807 * @pe: addr of the page entry 808 * @addr: dst addr to write into pe 809 * @count: number of page entries to update 810 * @incr: increase next addr by incr bytes 811 * @flags: access flags 812 * 813 * Update the page tables using sDMA (CIK). 814 */ 815 static void sdma_v2_4_vm_set_pte_pde(struct amdgpu_ib *ib, 816 uint64_t pe, 817 uint64_t addr, unsigned count, 818 uint32_t incr, uint32_t flags) 819 { 820 uint64_t value; 821 unsigned ndw; 822 823 while (count) { 824 ndw = count; 825 if (ndw > 0x7FFFF) 826 ndw = 0x7FFFF; 827 828 if (flags & AMDGPU_PTE_VALID) 829 value = addr; 830 else 831 value = 0; 832 833 /* for physically contiguous pages (vram) */ 834 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE); 835 ib->ptr[ib->length_dw++] = pe; /* dst addr */ 836 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 837 ib->ptr[ib->length_dw++] = flags; /* mask */ 838 ib->ptr[ib->length_dw++] = 0; 839 ib->ptr[ib->length_dw++] = value; /* value */ 840 ib->ptr[ib->length_dw++] = upper_32_bits(value); 841 ib->ptr[ib->length_dw++] = incr; /* increment size */ 842 ib->ptr[ib->length_dw++] = 0; 843 ib->ptr[ib->length_dw++] = ndw; /* number of entries */ 844 845 pe += ndw * 8; 846 addr += ndw * incr; 847 count -= ndw; 848 } 849 } 850 851 /** 852 * sdma_v2_4_vm_pad_ib - pad the IB to the required number of dw 853 * 854 * @ib: indirect buffer to fill with padding 855 * 856 */ 857 static void sdma_v2_4_vm_pad_ib(struct amdgpu_ib *ib) 858 { 859 struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ib->ring); 860 u32 pad_count; 861 int i; 862 863 pad_count = (8 - (ib->length_dw & 0x7)) % 8; 864 for (i = 0; i < pad_count; i++) 865 if (sdma && sdma->burst_nop && (i == 0)) 866 ib->ptr[ib->length_dw++] = 867 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | 868 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 869 else 870 ib->ptr[ib->length_dw++] = 871 SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 872 } 873 874 /** 875 * sdma_v2_4_ring_emit_vm_flush - cik vm flush using sDMA 876 * 877 * @ring: amdgpu_ring pointer 878 * @vm: amdgpu_vm pointer 879 * 880 * Update the page table base and flush the VM TLB 881 * using sDMA (VI). 882 */ 883 static void sdma_v2_4_ring_emit_vm_flush(struct amdgpu_ring *ring, 884 unsigned vm_id, uint64_t pd_addr) 885 { 886 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 887 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 888 if (vm_id < 8) { 889 amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id)); 890 } else { 891 amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8)); 892 } 893 amdgpu_ring_write(ring, pd_addr >> 12); 894 895 /* flush TLB */ 896 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 897 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 898 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST); 899 amdgpu_ring_write(ring, 1 << vm_id); 900 901 /* wait for flush */ 902 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 903 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 904 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */ 905 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2); 906 amdgpu_ring_write(ring, 0); 907 amdgpu_ring_write(ring, 0); /* reference */ 908 amdgpu_ring_write(ring, 0); /* mask */ 909 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 910 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 911 } 912 913 static int sdma_v2_4_early_init(void *handle) 914 { 915 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 916 917 adev->sdma.num_instances = SDMA_MAX_INSTANCE; 918 919 sdma_v2_4_set_ring_funcs(adev); 920 sdma_v2_4_set_buffer_funcs(adev); 921 sdma_v2_4_set_vm_pte_funcs(adev); 922 sdma_v2_4_set_irq_funcs(adev); 923 924 return 0; 925 } 926 927 static int sdma_v2_4_sw_init(void *handle) 928 { 929 struct amdgpu_ring *ring; 930 int r, i; 931 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 932 933 /* SDMA trap event */ 934 r = amdgpu_irq_add_id(adev, 224, &adev->sdma.trap_irq); 935 if (r) 936 return r; 937 938 /* SDMA Privileged inst */ 939 r = amdgpu_irq_add_id(adev, 241, &adev->sdma.illegal_inst_irq); 940 if (r) 941 return r; 942 943 /* SDMA Privileged inst */ 944 r = amdgpu_irq_add_id(adev, 247, &adev->sdma.illegal_inst_irq); 945 if (r) 946 return r; 947 948 r = sdma_v2_4_init_microcode(adev); 949 if (r) { 950 DRM_ERROR("Failed to load sdma firmware!\n"); 951 return r; 952 } 953 954 for (i = 0; i < adev->sdma.num_instances; i++) { 955 ring = &adev->sdma.instance[i].ring; 956 ring->ring_obj = NULL; 957 ring->use_doorbell = false; 958 sprintf(ring->name, "sdma%d", i); 959 r = amdgpu_ring_init(adev, ring, 256 * 1024, 960 SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf, 961 &adev->sdma.trap_irq, 962 (i == 0) ? 963 AMDGPU_SDMA_IRQ_TRAP0 : AMDGPU_SDMA_IRQ_TRAP1, 964 AMDGPU_RING_TYPE_SDMA); 965 if (r) 966 return r; 967 } 968 969 return r; 970 } 971 972 static int sdma_v2_4_sw_fini(void *handle) 973 { 974 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 975 int i; 976 977 for (i = 0; i < adev->sdma.num_instances; i++) 978 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 979 980 return 0; 981 } 982 983 static int sdma_v2_4_hw_init(void *handle) 984 { 985 int r; 986 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 987 988 sdma_v2_4_init_golden_registers(adev); 989 990 r = sdma_v2_4_start(adev); 991 if (r) 992 return r; 993 994 return r; 995 } 996 997 static int sdma_v2_4_hw_fini(void *handle) 998 { 999 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1000 1001 sdma_v2_4_enable(adev, false); 1002 1003 return 0; 1004 } 1005 1006 static int sdma_v2_4_suspend(void *handle) 1007 { 1008 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1009 1010 return sdma_v2_4_hw_fini(adev); 1011 } 1012 1013 static int sdma_v2_4_resume(void *handle) 1014 { 1015 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1016 1017 return sdma_v2_4_hw_init(adev); 1018 } 1019 1020 static bool sdma_v2_4_is_idle(void *handle) 1021 { 1022 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1023 u32 tmp = RREG32(mmSRBM_STATUS2); 1024 1025 if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK | 1026 SRBM_STATUS2__SDMA1_BUSY_MASK)) 1027 return false; 1028 1029 return true; 1030 } 1031 1032 static int sdma_v2_4_wait_for_idle(void *handle) 1033 { 1034 unsigned i; 1035 u32 tmp; 1036 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1037 1038 for (i = 0; i < adev->usec_timeout; i++) { 1039 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK | 1040 SRBM_STATUS2__SDMA1_BUSY_MASK); 1041 1042 if (!tmp) 1043 return 0; 1044 udelay(1); 1045 } 1046 return -ETIMEDOUT; 1047 } 1048 1049 static void sdma_v2_4_print_status(void *handle) 1050 { 1051 int i, j; 1052 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1053 1054 dev_info(adev->dev, "VI SDMA registers\n"); 1055 dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n", 1056 RREG32(mmSRBM_STATUS2)); 1057 for (i = 0; i < adev->sdma.num_instances; i++) { 1058 dev_info(adev->dev, " SDMA%d_STATUS_REG=0x%08X\n", 1059 i, RREG32(mmSDMA0_STATUS_REG + sdma_offsets[i])); 1060 dev_info(adev->dev, " SDMA%d_F32_CNTL=0x%08X\n", 1061 i, RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i])); 1062 dev_info(adev->dev, " SDMA%d_CNTL=0x%08X\n", 1063 i, RREG32(mmSDMA0_CNTL + sdma_offsets[i])); 1064 dev_info(adev->dev, " SDMA%d_SEM_WAIT_FAIL_TIMER_CNTL=0x%08X\n", 1065 i, RREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i])); 1066 dev_info(adev->dev, " SDMA%d_GFX_IB_CNTL=0x%08X\n", 1067 i, RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i])); 1068 dev_info(adev->dev, " SDMA%d_GFX_RB_CNTL=0x%08X\n", 1069 i, RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i])); 1070 dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR=0x%08X\n", 1071 i, RREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i])); 1072 dev_info(adev->dev, " SDMA%d_GFX_RB_WPTR=0x%08X\n", 1073 i, RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i])); 1074 dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR_ADDR_HI=0x%08X\n", 1075 i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i])); 1076 dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR_ADDR_LO=0x%08X\n", 1077 i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i])); 1078 dev_info(adev->dev, " SDMA%d_GFX_RB_BASE=0x%08X\n", 1079 i, RREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i])); 1080 dev_info(adev->dev, " SDMA%d_GFX_RB_BASE_HI=0x%08X\n", 1081 i, RREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i])); 1082 mutex_lock(&adev->srbm_mutex); 1083 for (j = 0; j < 16; j++) { 1084 vi_srbm_select(adev, 0, 0, 0, j); 1085 dev_info(adev->dev, " VM %d:\n", j); 1086 dev_info(adev->dev, " SDMA%d_GFX_VIRTUAL_ADDR=0x%08X\n", 1087 i, RREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i])); 1088 dev_info(adev->dev, " SDMA%d_GFX_APE1_CNTL=0x%08X\n", 1089 i, RREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i])); 1090 } 1091 vi_srbm_select(adev, 0, 0, 0, 0); 1092 mutex_unlock(&adev->srbm_mutex); 1093 } 1094 } 1095 1096 static int sdma_v2_4_soft_reset(void *handle) 1097 { 1098 u32 srbm_soft_reset = 0; 1099 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1100 u32 tmp = RREG32(mmSRBM_STATUS2); 1101 1102 if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) { 1103 /* sdma0 */ 1104 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET); 1105 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0); 1106 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp); 1107 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK; 1108 } 1109 if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) { 1110 /* sdma1 */ 1111 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET); 1112 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0); 1113 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp); 1114 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK; 1115 } 1116 1117 if (srbm_soft_reset) { 1118 sdma_v2_4_print_status((void *)adev); 1119 1120 tmp = RREG32(mmSRBM_SOFT_RESET); 1121 tmp |= srbm_soft_reset; 1122 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1123 WREG32(mmSRBM_SOFT_RESET, tmp); 1124 tmp = RREG32(mmSRBM_SOFT_RESET); 1125 1126 udelay(50); 1127 1128 tmp &= ~srbm_soft_reset; 1129 WREG32(mmSRBM_SOFT_RESET, tmp); 1130 tmp = RREG32(mmSRBM_SOFT_RESET); 1131 1132 /* Wait a little for things to settle down */ 1133 udelay(50); 1134 1135 sdma_v2_4_print_status((void *)adev); 1136 } 1137 1138 return 0; 1139 } 1140 1141 static int sdma_v2_4_set_trap_irq_state(struct amdgpu_device *adev, 1142 struct amdgpu_irq_src *src, 1143 unsigned type, 1144 enum amdgpu_interrupt_state state) 1145 { 1146 u32 sdma_cntl; 1147 1148 switch (type) { 1149 case AMDGPU_SDMA_IRQ_TRAP0: 1150 switch (state) { 1151 case AMDGPU_IRQ_STATE_DISABLE: 1152 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); 1153 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); 1154 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); 1155 break; 1156 case AMDGPU_IRQ_STATE_ENABLE: 1157 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); 1158 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); 1159 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); 1160 break; 1161 default: 1162 break; 1163 } 1164 break; 1165 case AMDGPU_SDMA_IRQ_TRAP1: 1166 switch (state) { 1167 case AMDGPU_IRQ_STATE_DISABLE: 1168 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); 1169 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); 1170 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); 1171 break; 1172 case AMDGPU_IRQ_STATE_ENABLE: 1173 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); 1174 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); 1175 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); 1176 break; 1177 default: 1178 break; 1179 } 1180 break; 1181 default: 1182 break; 1183 } 1184 return 0; 1185 } 1186 1187 static int sdma_v2_4_process_trap_irq(struct amdgpu_device *adev, 1188 struct amdgpu_irq_src *source, 1189 struct amdgpu_iv_entry *entry) 1190 { 1191 u8 instance_id, queue_id; 1192 1193 instance_id = (entry->ring_id & 0x3) >> 0; 1194 queue_id = (entry->ring_id & 0xc) >> 2; 1195 DRM_DEBUG("IH: SDMA trap\n"); 1196 switch (instance_id) { 1197 case 0: 1198 switch (queue_id) { 1199 case 0: 1200 amdgpu_fence_process(&adev->sdma.instance[0].ring); 1201 break; 1202 case 1: 1203 /* XXX compute */ 1204 break; 1205 case 2: 1206 /* XXX compute */ 1207 break; 1208 } 1209 break; 1210 case 1: 1211 switch (queue_id) { 1212 case 0: 1213 amdgpu_fence_process(&adev->sdma.instance[1].ring); 1214 break; 1215 case 1: 1216 /* XXX compute */ 1217 break; 1218 case 2: 1219 /* XXX compute */ 1220 break; 1221 } 1222 break; 1223 } 1224 return 0; 1225 } 1226 1227 static int sdma_v2_4_process_illegal_inst_irq(struct amdgpu_device *adev, 1228 struct amdgpu_irq_src *source, 1229 struct amdgpu_iv_entry *entry) 1230 { 1231 DRM_ERROR("Illegal instruction in SDMA command stream\n"); 1232 schedule_work(&adev->reset_work); 1233 return 0; 1234 } 1235 1236 static int sdma_v2_4_set_clockgating_state(void *handle, 1237 enum amd_clockgating_state state) 1238 { 1239 /* XXX handled via the smc on VI */ 1240 return 0; 1241 } 1242 1243 static int sdma_v2_4_set_powergating_state(void *handle, 1244 enum amd_powergating_state state) 1245 { 1246 return 0; 1247 } 1248 1249 const struct amd_ip_funcs sdma_v2_4_ip_funcs = { 1250 .early_init = sdma_v2_4_early_init, 1251 .late_init = NULL, 1252 .sw_init = sdma_v2_4_sw_init, 1253 .sw_fini = sdma_v2_4_sw_fini, 1254 .hw_init = sdma_v2_4_hw_init, 1255 .hw_fini = sdma_v2_4_hw_fini, 1256 .suspend = sdma_v2_4_suspend, 1257 .resume = sdma_v2_4_resume, 1258 .is_idle = sdma_v2_4_is_idle, 1259 .wait_for_idle = sdma_v2_4_wait_for_idle, 1260 .soft_reset = sdma_v2_4_soft_reset, 1261 .print_status = sdma_v2_4_print_status, 1262 .set_clockgating_state = sdma_v2_4_set_clockgating_state, 1263 .set_powergating_state = sdma_v2_4_set_powergating_state, 1264 }; 1265 1266 static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = { 1267 .get_rptr = sdma_v2_4_ring_get_rptr, 1268 .get_wptr = sdma_v2_4_ring_get_wptr, 1269 .set_wptr = sdma_v2_4_ring_set_wptr, 1270 .parse_cs = NULL, 1271 .emit_ib = sdma_v2_4_ring_emit_ib, 1272 .emit_fence = sdma_v2_4_ring_emit_fence, 1273 .emit_vm_flush = sdma_v2_4_ring_emit_vm_flush, 1274 .emit_hdp_flush = sdma_v2_4_ring_emit_hdp_flush, 1275 .test_ring = sdma_v2_4_ring_test_ring, 1276 .test_ib = sdma_v2_4_ring_test_ib, 1277 .insert_nop = sdma_v2_4_ring_insert_nop, 1278 }; 1279 1280 static void sdma_v2_4_set_ring_funcs(struct amdgpu_device *adev) 1281 { 1282 int i; 1283 1284 for (i = 0; i < adev->sdma.num_instances; i++) 1285 adev->sdma.instance[i].ring.funcs = &sdma_v2_4_ring_funcs; 1286 } 1287 1288 static const struct amdgpu_irq_src_funcs sdma_v2_4_trap_irq_funcs = { 1289 .set = sdma_v2_4_set_trap_irq_state, 1290 .process = sdma_v2_4_process_trap_irq, 1291 }; 1292 1293 static const struct amdgpu_irq_src_funcs sdma_v2_4_illegal_inst_irq_funcs = { 1294 .process = sdma_v2_4_process_illegal_inst_irq, 1295 }; 1296 1297 static void sdma_v2_4_set_irq_funcs(struct amdgpu_device *adev) 1298 { 1299 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST; 1300 adev->sdma.trap_irq.funcs = &sdma_v2_4_trap_irq_funcs; 1301 adev->sdma.illegal_inst_irq.funcs = &sdma_v2_4_illegal_inst_irq_funcs; 1302 } 1303 1304 /** 1305 * sdma_v2_4_emit_copy_buffer - copy buffer using the sDMA engine 1306 * 1307 * @ring: amdgpu_ring structure holding ring information 1308 * @src_offset: src GPU address 1309 * @dst_offset: dst GPU address 1310 * @byte_count: number of bytes to xfer 1311 * 1312 * Copy GPU buffers using the DMA engine (VI). 1313 * Used by the amdgpu ttm implementation to move pages if 1314 * registered as the asic copy callback. 1315 */ 1316 static void sdma_v2_4_emit_copy_buffer(struct amdgpu_ib *ib, 1317 uint64_t src_offset, 1318 uint64_t dst_offset, 1319 uint32_t byte_count) 1320 { 1321 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1322 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1323 ib->ptr[ib->length_dw++] = byte_count; 1324 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1325 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 1326 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 1327 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1328 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1329 } 1330 1331 /** 1332 * sdma_v2_4_emit_fill_buffer - fill buffer using the sDMA engine 1333 * 1334 * @ring: amdgpu_ring structure holding ring information 1335 * @src_data: value to write to buffer 1336 * @dst_offset: dst GPU address 1337 * @byte_count: number of bytes to xfer 1338 * 1339 * Fill GPU buffers using the DMA engine (VI). 1340 */ 1341 static void sdma_v2_4_emit_fill_buffer(struct amdgpu_ib *ib, 1342 uint32_t src_data, 1343 uint64_t dst_offset, 1344 uint32_t byte_count) 1345 { 1346 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); 1347 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1348 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1349 ib->ptr[ib->length_dw++] = src_data; 1350 ib->ptr[ib->length_dw++] = byte_count; 1351 } 1352 1353 static const struct amdgpu_buffer_funcs sdma_v2_4_buffer_funcs = { 1354 .copy_max_bytes = 0x1fffff, 1355 .copy_num_dw = 7, 1356 .emit_copy_buffer = sdma_v2_4_emit_copy_buffer, 1357 1358 .fill_max_bytes = 0x1fffff, 1359 .fill_num_dw = 7, 1360 .emit_fill_buffer = sdma_v2_4_emit_fill_buffer, 1361 }; 1362 1363 static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device *adev) 1364 { 1365 if (adev->mman.buffer_funcs == NULL) { 1366 adev->mman.buffer_funcs = &sdma_v2_4_buffer_funcs; 1367 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 1368 } 1369 } 1370 1371 static const struct amdgpu_vm_pte_funcs sdma_v2_4_vm_pte_funcs = { 1372 .copy_pte = sdma_v2_4_vm_copy_pte, 1373 .write_pte = sdma_v2_4_vm_write_pte, 1374 .set_pte_pde = sdma_v2_4_vm_set_pte_pde, 1375 .pad_ib = sdma_v2_4_vm_pad_ib, 1376 }; 1377 1378 static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev) 1379 { 1380 if (adev->vm_manager.vm_pte_funcs == NULL) { 1381 adev->vm_manager.vm_pte_funcs = &sdma_v2_4_vm_pte_funcs; 1382 adev->vm_manager.vm_pte_funcs_ring = &adev->sdma.instance[0].ring; 1383 adev->vm_manager.vm_pte_funcs_ring->is_pte_ring = true; 1384 } 1385 } 1386