1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 */ 24 25 #include <linux/delay.h> 26 #include <linux/firmware.h> 27 #include <linux/module.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_ucode.h" 31 #include "amdgpu_trace.h" 32 #include "vi.h" 33 #include "vid.h" 34 35 #include "oss/oss_2_4_d.h" 36 #include "oss/oss_2_4_sh_mask.h" 37 38 #include "gmc/gmc_7_1_d.h" 39 #include "gmc/gmc_7_1_sh_mask.h" 40 41 #include "gca/gfx_8_0_d.h" 42 #include "gca/gfx_8_0_enum.h" 43 #include "gca/gfx_8_0_sh_mask.h" 44 45 #include "bif/bif_5_0_d.h" 46 #include "bif/bif_5_0_sh_mask.h" 47 48 #include "iceland_sdma_pkt_open.h" 49 50 #include "ivsrcid/ivsrcid_vislands30.h" 51 52 static void sdma_v2_4_set_ring_funcs(struct amdgpu_device *adev); 53 static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device *adev); 54 static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev); 55 static void sdma_v2_4_set_irq_funcs(struct amdgpu_device *adev); 56 57 MODULE_FIRMWARE("amdgpu/topaz_sdma.bin"); 58 MODULE_FIRMWARE("amdgpu/topaz_sdma1.bin"); 59 60 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] = { 61 SDMA0_REGISTER_OFFSET, 62 SDMA1_REGISTER_OFFSET 63 }; 64 65 static const u32 golden_settings_iceland_a11[] = { 66 mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, 67 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, 68 mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007, 69 mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000, 70 }; 71 72 static const u32 iceland_mgcg_cgcg_init[] = { 73 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100, 74 mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 75 }; 76 77 /* 78 * sDMA - System DMA 79 * Starting with CIK, the GPU has new asynchronous 80 * DMA engines. These engines are used for compute 81 * and gfx. There are two DMA engines (SDMA0, SDMA1) 82 * and each one supports 1 ring buffer used for gfx 83 * and 2 queues used for compute. 84 * 85 * The programming model is very similar to the CP 86 * (ring buffer, IBs, etc.), but sDMA has it's own 87 * packet format that is different from the PM4 format 88 * used by the CP. sDMA supports copying data, writing 89 * embedded data, solid fills, and a number of other 90 * things. It also has support for tiling/detiling of 91 * buffers. 92 */ 93 94 static void sdma_v2_4_init_golden_registers(struct amdgpu_device *adev) 95 { 96 switch (adev->asic_type) { 97 case CHIP_TOPAZ: 98 amdgpu_device_program_register_sequence(adev, 99 iceland_mgcg_cgcg_init, 100 ARRAY_SIZE(iceland_mgcg_cgcg_init)); 101 amdgpu_device_program_register_sequence(adev, 102 golden_settings_iceland_a11, 103 ARRAY_SIZE(golden_settings_iceland_a11)); 104 break; 105 default: 106 break; 107 } 108 } 109 110 static void sdma_v2_4_free_microcode(struct amdgpu_device *adev) 111 { 112 int i; 113 114 for (i = 0; i < adev->sdma.num_instances; i++) 115 amdgpu_ucode_release(&adev->sdma.instance[i].fw); 116 } 117 118 /** 119 * sdma_v2_4_init_microcode - load ucode images from disk 120 * 121 * @adev: amdgpu_device pointer 122 * 123 * Use the firmware interface to load the ucode images into 124 * the driver (not loaded into hw). 125 * Returns 0 on success, error on failure. 126 */ 127 static int sdma_v2_4_init_microcode(struct amdgpu_device *adev) 128 { 129 const char *chip_name; 130 char fw_name[30]; 131 int err = 0, i; 132 struct amdgpu_firmware_info *info = NULL; 133 const struct common_firmware_header *header = NULL; 134 const struct sdma_firmware_header_v1_0 *hdr; 135 136 DRM_DEBUG("\n"); 137 138 switch (adev->asic_type) { 139 case CHIP_TOPAZ: 140 chip_name = "topaz"; 141 break; 142 default: 143 BUG(); 144 } 145 146 for (i = 0; i < adev->sdma.num_instances; i++) { 147 if (i == 0) 148 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name); 149 else 150 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name); 151 err = amdgpu_ucode_request(adev, &adev->sdma.instance[i].fw, fw_name); 152 if (err) 153 goto out; 154 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 155 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version); 156 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version); 157 if (adev->sdma.instance[i].feature_version >= 20) 158 adev->sdma.instance[i].burst_nop = true; 159 160 if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU) { 161 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i]; 162 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i; 163 info->fw = adev->sdma.instance[i].fw; 164 header = (const struct common_firmware_header *)info->fw->data; 165 adev->firmware.fw_size += 166 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 167 } 168 } 169 170 out: 171 if (err) { 172 pr_err("sdma_v2_4: Failed to load firmware \"%s\"\n", fw_name); 173 for (i = 0; i < adev->sdma.num_instances; i++) 174 amdgpu_ucode_release(&adev->sdma.instance[i].fw); 175 } 176 return err; 177 } 178 179 /** 180 * sdma_v2_4_ring_get_rptr - get the current read pointer 181 * 182 * @ring: amdgpu ring pointer 183 * 184 * Get the current rptr from the hardware (VI+). 185 */ 186 static uint64_t sdma_v2_4_ring_get_rptr(struct amdgpu_ring *ring) 187 { 188 /* XXX check if swapping is necessary on BE */ 189 return *ring->rptr_cpu_addr >> 2; 190 } 191 192 /** 193 * sdma_v2_4_ring_get_wptr - get the current write pointer 194 * 195 * @ring: amdgpu ring pointer 196 * 197 * Get the current wptr from the hardware (VI+). 198 */ 199 static uint64_t sdma_v2_4_ring_get_wptr(struct amdgpu_ring *ring) 200 { 201 struct amdgpu_device *adev = ring->adev; 202 u32 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) >> 2; 203 204 return wptr; 205 } 206 207 /** 208 * sdma_v2_4_ring_set_wptr - commit the write pointer 209 * 210 * @ring: amdgpu ring pointer 211 * 212 * Write the wptr back to the hardware (VI+). 213 */ 214 static void sdma_v2_4_ring_set_wptr(struct amdgpu_ring *ring) 215 { 216 struct amdgpu_device *adev = ring->adev; 217 218 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], ring->wptr << 2); 219 } 220 221 static void sdma_v2_4_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 222 { 223 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 224 int i; 225 226 for (i = 0; i < count; i++) 227 if (sdma && sdma->burst_nop && (i == 0)) 228 amdgpu_ring_write(ring, ring->funcs->nop | 229 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 230 else 231 amdgpu_ring_write(ring, ring->funcs->nop); 232 } 233 234 /** 235 * sdma_v2_4_ring_emit_ib - Schedule an IB on the DMA engine 236 * 237 * @ring: amdgpu ring pointer 238 * @job: job to retrieve vmid from 239 * @ib: IB object to schedule 240 * @flags: unused 241 * 242 * Schedule an IB in the DMA ring (VI). 243 */ 244 static void sdma_v2_4_ring_emit_ib(struct amdgpu_ring *ring, 245 struct amdgpu_job *job, 246 struct amdgpu_ib *ib, 247 uint32_t flags) 248 { 249 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 250 251 /* IB packet must end on a 8 DW boundary */ 252 sdma_v2_4_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); 253 254 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 255 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 256 /* base must be 32 byte aligned */ 257 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 258 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 259 amdgpu_ring_write(ring, ib->length_dw); 260 amdgpu_ring_write(ring, 0); 261 amdgpu_ring_write(ring, 0); 262 263 } 264 265 /** 266 * sdma_v2_4_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 267 * 268 * @ring: amdgpu ring pointer 269 * 270 * Emit an hdp flush packet on the requested DMA ring. 271 */ 272 static void sdma_v2_4_ring_emit_hdp_flush(struct amdgpu_ring *ring) 273 { 274 u32 ref_and_mask = 0; 275 276 if (ring->me == 0) 277 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1); 278 else 279 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1); 280 281 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 282 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) | 283 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 284 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2); 285 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2); 286 amdgpu_ring_write(ring, ref_and_mask); /* reference */ 287 amdgpu_ring_write(ring, ref_and_mask); /* mask */ 288 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 289 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 290 } 291 292 /** 293 * sdma_v2_4_ring_emit_fence - emit a fence on the DMA ring 294 * 295 * @ring: amdgpu ring pointer 296 * @addr: address 297 * @seq: sequence number 298 * @flags: fence related flags 299 * 300 * Add a DMA fence packet to the ring to write 301 * the fence seq number and DMA trap packet to generate 302 * an interrupt if needed (VI). 303 */ 304 static void sdma_v2_4_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 305 unsigned flags) 306 { 307 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 308 /* write the fence */ 309 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 310 amdgpu_ring_write(ring, lower_32_bits(addr)); 311 amdgpu_ring_write(ring, upper_32_bits(addr)); 312 amdgpu_ring_write(ring, lower_32_bits(seq)); 313 314 /* optionally write high bits as well */ 315 if (write64bit) { 316 addr += 4; 317 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 318 amdgpu_ring_write(ring, lower_32_bits(addr)); 319 amdgpu_ring_write(ring, upper_32_bits(addr)); 320 amdgpu_ring_write(ring, upper_32_bits(seq)); 321 } 322 323 /* generate an interrupt */ 324 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); 325 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); 326 } 327 328 /** 329 * sdma_v2_4_gfx_stop - stop the gfx async dma engines 330 * 331 * @adev: amdgpu_device pointer 332 * 333 * Stop the gfx async dma ring buffers (VI). 334 */ 335 static void sdma_v2_4_gfx_stop(struct amdgpu_device *adev) 336 { 337 u32 rb_cntl, ib_cntl; 338 int i; 339 340 for (i = 0; i < adev->sdma.num_instances; i++) { 341 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); 342 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); 343 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); 344 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); 345 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); 346 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); 347 } 348 } 349 350 /** 351 * sdma_v2_4_rlc_stop - stop the compute async dma engines 352 * 353 * @adev: amdgpu_device pointer 354 * 355 * Stop the compute async dma queues (VI). 356 */ 357 static void sdma_v2_4_rlc_stop(struct amdgpu_device *adev) 358 { 359 /* XXX todo */ 360 } 361 362 /** 363 * sdma_v2_4_enable - stop the async dma engines 364 * 365 * @adev: amdgpu_device pointer 366 * @enable: enable/disable the DMA MEs. 367 * 368 * Halt or unhalt the async dma engines (VI). 369 */ 370 static void sdma_v2_4_enable(struct amdgpu_device *adev, bool enable) 371 { 372 u32 f32_cntl; 373 int i; 374 375 if (!enable) { 376 sdma_v2_4_gfx_stop(adev); 377 sdma_v2_4_rlc_stop(adev); 378 } 379 380 for (i = 0; i < adev->sdma.num_instances; i++) { 381 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]); 382 if (enable) 383 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0); 384 else 385 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1); 386 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl); 387 } 388 } 389 390 /** 391 * sdma_v2_4_gfx_resume - setup and start the async dma engines 392 * 393 * @adev: amdgpu_device pointer 394 * 395 * Set up the gfx DMA ring buffers and enable them (VI). 396 * Returns 0 for success, error for failure. 397 */ 398 static int sdma_v2_4_gfx_resume(struct amdgpu_device *adev) 399 { 400 struct amdgpu_ring *ring; 401 u32 rb_cntl, ib_cntl; 402 u32 rb_bufsz; 403 int i, j, r; 404 405 for (i = 0; i < adev->sdma.num_instances; i++) { 406 ring = &adev->sdma.instance[i].ring; 407 408 mutex_lock(&adev->srbm_mutex); 409 for (j = 0; j < 16; j++) { 410 vi_srbm_select(adev, 0, 0, 0, j); 411 /* SDMA GFX */ 412 WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0); 413 WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0); 414 } 415 vi_srbm_select(adev, 0, 0, 0, 0); 416 mutex_unlock(&adev->srbm_mutex); 417 418 WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i], 419 adev->gfx.config.gb_addr_config & 0x70); 420 421 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0); 422 423 /* Set ring buffer size in dwords */ 424 rb_bufsz = order_base_2(ring->ring_size / 4); 425 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); 426 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); 427 #ifdef __BIG_ENDIAN 428 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); 429 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 430 RPTR_WRITEBACK_SWAP_ENABLE, 1); 431 #endif 432 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); 433 434 /* Initialize the ring buffer's read and write pointers */ 435 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0); 436 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0); 437 WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0); 438 WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0); 439 440 /* set the wb address whether it's enabled or not */ 441 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i], 442 upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF); 443 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i], 444 lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC); 445 446 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); 447 448 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8); 449 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40); 450 451 ring->wptr = 0; 452 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2); 453 454 /* enable DMA RB */ 455 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); 456 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); 457 458 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); 459 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); 460 #ifdef __BIG_ENDIAN 461 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); 462 #endif 463 /* enable DMA IBs */ 464 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); 465 } 466 467 sdma_v2_4_enable(adev, true); 468 for (i = 0; i < adev->sdma.num_instances; i++) { 469 ring = &adev->sdma.instance[i].ring; 470 r = amdgpu_ring_test_helper(ring); 471 if (r) 472 return r; 473 } 474 475 return 0; 476 } 477 478 /** 479 * sdma_v2_4_rlc_resume - setup and start the async dma engines 480 * 481 * @adev: amdgpu_device pointer 482 * 483 * Set up the compute DMA queues and enable them (VI). 484 * Returns 0 for success, error for failure. 485 */ 486 static int sdma_v2_4_rlc_resume(struct amdgpu_device *adev) 487 { 488 /* XXX todo */ 489 return 0; 490 } 491 492 493 /** 494 * sdma_v2_4_start - setup and start the async dma engines 495 * 496 * @adev: amdgpu_device pointer 497 * 498 * Set up the DMA engines and enable them (VI). 499 * Returns 0 for success, error for failure. 500 */ 501 static int sdma_v2_4_start(struct amdgpu_device *adev) 502 { 503 int r; 504 505 /* halt the engine before programing */ 506 sdma_v2_4_enable(adev, false); 507 508 /* start the gfx rings and rlc compute queues */ 509 r = sdma_v2_4_gfx_resume(adev); 510 if (r) 511 return r; 512 r = sdma_v2_4_rlc_resume(adev); 513 if (r) 514 return r; 515 516 return 0; 517 } 518 519 /** 520 * sdma_v2_4_ring_test_ring - simple async dma engine test 521 * 522 * @ring: amdgpu_ring structure holding ring information 523 * 524 * Test the DMA engine by writing using it to write an 525 * value to memory. (VI). 526 * Returns 0 for success, error for failure. 527 */ 528 static int sdma_v2_4_ring_test_ring(struct amdgpu_ring *ring) 529 { 530 struct amdgpu_device *adev = ring->adev; 531 unsigned i; 532 unsigned index; 533 int r; 534 u32 tmp; 535 u64 gpu_addr; 536 537 r = amdgpu_device_wb_get(adev, &index); 538 if (r) 539 return r; 540 541 gpu_addr = adev->wb.gpu_addr + (index * 4); 542 tmp = 0xCAFEDEAD; 543 adev->wb.wb[index] = cpu_to_le32(tmp); 544 545 r = amdgpu_ring_alloc(ring, 5); 546 if (r) 547 goto error_free_wb; 548 549 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 550 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 551 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 552 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 553 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1)); 554 amdgpu_ring_write(ring, 0xDEADBEEF); 555 amdgpu_ring_commit(ring); 556 557 for (i = 0; i < adev->usec_timeout; i++) { 558 tmp = le32_to_cpu(adev->wb.wb[index]); 559 if (tmp == 0xDEADBEEF) 560 break; 561 udelay(1); 562 } 563 564 if (i >= adev->usec_timeout) 565 r = -ETIMEDOUT; 566 567 error_free_wb: 568 amdgpu_device_wb_free(adev, index); 569 return r; 570 } 571 572 /** 573 * sdma_v2_4_ring_test_ib - test an IB on the DMA engine 574 * 575 * @ring: amdgpu_ring structure holding ring information 576 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT 577 * 578 * Test a simple IB in the DMA ring (VI). 579 * Returns 0 on success, error on failure. 580 */ 581 static int sdma_v2_4_ring_test_ib(struct amdgpu_ring *ring, long timeout) 582 { 583 struct amdgpu_device *adev = ring->adev; 584 struct amdgpu_ib ib; 585 struct dma_fence *f = NULL; 586 unsigned index; 587 u32 tmp = 0; 588 u64 gpu_addr; 589 long r; 590 591 r = amdgpu_device_wb_get(adev, &index); 592 if (r) 593 return r; 594 595 gpu_addr = adev->wb.gpu_addr + (index * 4); 596 tmp = 0xCAFEDEAD; 597 adev->wb.wb[index] = cpu_to_le32(tmp); 598 memset(&ib, 0, sizeof(ib)); 599 r = amdgpu_ib_get(adev, NULL, 256, 600 AMDGPU_IB_POOL_DIRECT, &ib); 601 if (r) 602 goto err0; 603 604 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 605 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 606 ib.ptr[1] = lower_32_bits(gpu_addr); 607 ib.ptr[2] = upper_32_bits(gpu_addr); 608 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1); 609 ib.ptr[4] = 0xDEADBEEF; 610 ib.ptr[5] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 611 ib.ptr[6] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 612 ib.ptr[7] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 613 ib.length_dw = 8; 614 615 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 616 if (r) 617 goto err1; 618 619 r = dma_fence_wait_timeout(f, false, timeout); 620 if (r == 0) { 621 r = -ETIMEDOUT; 622 goto err1; 623 } else if (r < 0) { 624 goto err1; 625 } 626 tmp = le32_to_cpu(adev->wb.wb[index]); 627 if (tmp == 0xDEADBEEF) 628 r = 0; 629 else 630 r = -EINVAL; 631 632 err1: 633 amdgpu_ib_free(adev, &ib, NULL); 634 dma_fence_put(f); 635 err0: 636 amdgpu_device_wb_free(adev, index); 637 return r; 638 } 639 640 /** 641 * sdma_v2_4_vm_copy_pte - update PTEs by copying them from the GART 642 * 643 * @ib: indirect buffer to fill with commands 644 * @pe: addr of the page entry 645 * @src: src addr to copy from 646 * @count: number of page entries to update 647 * 648 * Update PTEs by copying them from the GART using sDMA (CIK). 649 */ 650 static void sdma_v2_4_vm_copy_pte(struct amdgpu_ib *ib, 651 uint64_t pe, uint64_t src, 652 unsigned count) 653 { 654 unsigned bytes = count * 8; 655 656 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 657 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 658 ib->ptr[ib->length_dw++] = bytes; 659 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 660 ib->ptr[ib->length_dw++] = lower_32_bits(src); 661 ib->ptr[ib->length_dw++] = upper_32_bits(src); 662 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 663 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 664 } 665 666 /** 667 * sdma_v2_4_vm_write_pte - update PTEs by writing them manually 668 * 669 * @ib: indirect buffer to fill with commands 670 * @pe: addr of the page entry 671 * @value: dst addr to write into pe 672 * @count: number of page entries to update 673 * @incr: increase next addr by incr bytes 674 * 675 * Update PTEs by writing them manually using sDMA (CIK). 676 */ 677 static void sdma_v2_4_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 678 uint64_t value, unsigned count, 679 uint32_t incr) 680 { 681 unsigned ndw = count * 2; 682 683 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 684 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 685 ib->ptr[ib->length_dw++] = pe; 686 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 687 ib->ptr[ib->length_dw++] = ndw; 688 for (; ndw > 0; ndw -= 2) { 689 ib->ptr[ib->length_dw++] = lower_32_bits(value); 690 ib->ptr[ib->length_dw++] = upper_32_bits(value); 691 value += incr; 692 } 693 } 694 695 /** 696 * sdma_v2_4_vm_set_pte_pde - update the page tables using sDMA 697 * 698 * @ib: indirect buffer to fill with commands 699 * @pe: addr of the page entry 700 * @addr: dst addr to write into pe 701 * @count: number of page entries to update 702 * @incr: increase next addr by incr bytes 703 * @flags: access flags 704 * 705 * Update the page tables using sDMA (CIK). 706 */ 707 static void sdma_v2_4_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe, 708 uint64_t addr, unsigned count, 709 uint32_t incr, uint64_t flags) 710 { 711 /* for physically contiguous pages (vram) */ 712 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE); 713 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 714 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 715 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 716 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 717 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 718 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 719 ib->ptr[ib->length_dw++] = incr; /* increment size */ 720 ib->ptr[ib->length_dw++] = 0; 721 ib->ptr[ib->length_dw++] = count; /* number of entries */ 722 } 723 724 /** 725 * sdma_v2_4_ring_pad_ib - pad the IB to the required number of dw 726 * 727 * @ring: amdgpu_ring structure holding ring information 728 * @ib: indirect buffer to fill with padding 729 * 730 */ 731 static void sdma_v2_4_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 732 { 733 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 734 u32 pad_count; 735 int i; 736 737 pad_count = (-ib->length_dw) & 7; 738 for (i = 0; i < pad_count; i++) 739 if (sdma && sdma->burst_nop && (i == 0)) 740 ib->ptr[ib->length_dw++] = 741 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | 742 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 743 else 744 ib->ptr[ib->length_dw++] = 745 SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 746 } 747 748 /** 749 * sdma_v2_4_ring_emit_pipeline_sync - sync the pipeline 750 * 751 * @ring: amdgpu_ring pointer 752 * 753 * Make sure all previous operations are completed (CIK). 754 */ 755 static void sdma_v2_4_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 756 { 757 uint32_t seq = ring->fence_drv.sync_seq; 758 uint64_t addr = ring->fence_drv.gpu_addr; 759 760 /* wait for idle */ 761 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 762 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 763 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */ 764 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1)); 765 amdgpu_ring_write(ring, addr & 0xfffffffc); 766 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 767 amdgpu_ring_write(ring, seq); /* reference */ 768 amdgpu_ring_write(ring, 0xffffffff); /* mask */ 769 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 770 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ 771 } 772 773 /** 774 * sdma_v2_4_ring_emit_vm_flush - cik vm flush using sDMA 775 * 776 * @ring: amdgpu_ring pointer 777 * @vmid: vmid number to use 778 * @pd_addr: address 779 * 780 * Update the page table base and flush the VM TLB 781 * using sDMA (VI). 782 */ 783 static void sdma_v2_4_ring_emit_vm_flush(struct amdgpu_ring *ring, 784 unsigned vmid, uint64_t pd_addr) 785 { 786 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 787 788 /* wait for flush */ 789 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 790 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 791 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */ 792 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2); 793 amdgpu_ring_write(ring, 0); 794 amdgpu_ring_write(ring, 0); /* reference */ 795 amdgpu_ring_write(ring, 0); /* mask */ 796 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 797 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 798 } 799 800 static void sdma_v2_4_ring_emit_wreg(struct amdgpu_ring *ring, 801 uint32_t reg, uint32_t val) 802 { 803 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 804 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 805 amdgpu_ring_write(ring, reg); 806 amdgpu_ring_write(ring, val); 807 } 808 809 static int sdma_v2_4_early_init(void *handle) 810 { 811 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 812 int r; 813 814 adev->sdma.num_instances = SDMA_MAX_INSTANCE; 815 816 r = sdma_v2_4_init_microcode(adev); 817 if (r) 818 return r; 819 820 sdma_v2_4_set_ring_funcs(adev); 821 sdma_v2_4_set_buffer_funcs(adev); 822 sdma_v2_4_set_vm_pte_funcs(adev); 823 sdma_v2_4_set_irq_funcs(adev); 824 825 return 0; 826 } 827 828 static int sdma_v2_4_sw_init(void *handle) 829 { 830 struct amdgpu_ring *ring; 831 int r, i; 832 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 833 834 /* SDMA trap event */ 835 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_TRAP, 836 &adev->sdma.trap_irq); 837 if (r) 838 return r; 839 840 /* SDMA Privileged inst */ 841 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 241, 842 &adev->sdma.illegal_inst_irq); 843 if (r) 844 return r; 845 846 /* SDMA Privileged inst */ 847 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_SRBM_WRITE, 848 &adev->sdma.illegal_inst_irq); 849 if (r) 850 return r; 851 852 for (i = 0; i < adev->sdma.num_instances; i++) { 853 ring = &adev->sdma.instance[i].ring; 854 ring->ring_obj = NULL; 855 ring->use_doorbell = false; 856 sprintf(ring->name, "sdma%d", i); 857 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq, 858 (i == 0) ? AMDGPU_SDMA_IRQ_INSTANCE0 : 859 AMDGPU_SDMA_IRQ_INSTANCE1, 860 AMDGPU_RING_PRIO_DEFAULT, NULL); 861 if (r) 862 return r; 863 } 864 865 return r; 866 } 867 868 static int sdma_v2_4_sw_fini(void *handle) 869 { 870 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 871 int i; 872 873 for (i = 0; i < adev->sdma.num_instances; i++) 874 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 875 876 sdma_v2_4_free_microcode(adev); 877 return 0; 878 } 879 880 static int sdma_v2_4_hw_init(void *handle) 881 { 882 int r; 883 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 884 885 sdma_v2_4_init_golden_registers(adev); 886 887 r = sdma_v2_4_start(adev); 888 if (r) 889 return r; 890 891 return r; 892 } 893 894 static int sdma_v2_4_hw_fini(void *handle) 895 { 896 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 897 898 sdma_v2_4_enable(adev, false); 899 900 return 0; 901 } 902 903 static int sdma_v2_4_suspend(void *handle) 904 { 905 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 906 907 return sdma_v2_4_hw_fini(adev); 908 } 909 910 static int sdma_v2_4_resume(void *handle) 911 { 912 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 913 914 return sdma_v2_4_hw_init(adev); 915 } 916 917 static bool sdma_v2_4_is_idle(void *handle) 918 { 919 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 920 u32 tmp = RREG32(mmSRBM_STATUS2); 921 922 if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK | 923 SRBM_STATUS2__SDMA1_BUSY_MASK)) 924 return false; 925 926 return true; 927 } 928 929 static int sdma_v2_4_wait_for_idle(void *handle) 930 { 931 unsigned i; 932 u32 tmp; 933 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 934 935 for (i = 0; i < adev->usec_timeout; i++) { 936 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK | 937 SRBM_STATUS2__SDMA1_BUSY_MASK); 938 939 if (!tmp) 940 return 0; 941 udelay(1); 942 } 943 return -ETIMEDOUT; 944 } 945 946 static int sdma_v2_4_soft_reset(void *handle) 947 { 948 u32 srbm_soft_reset = 0; 949 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 950 u32 tmp = RREG32(mmSRBM_STATUS2); 951 952 if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) { 953 /* sdma0 */ 954 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET); 955 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0); 956 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp); 957 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK; 958 } 959 if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) { 960 /* sdma1 */ 961 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET); 962 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0); 963 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp); 964 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK; 965 } 966 967 if (srbm_soft_reset) { 968 tmp = RREG32(mmSRBM_SOFT_RESET); 969 tmp |= srbm_soft_reset; 970 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 971 WREG32(mmSRBM_SOFT_RESET, tmp); 972 tmp = RREG32(mmSRBM_SOFT_RESET); 973 974 udelay(50); 975 976 tmp &= ~srbm_soft_reset; 977 WREG32(mmSRBM_SOFT_RESET, tmp); 978 tmp = RREG32(mmSRBM_SOFT_RESET); 979 980 /* Wait a little for things to settle down */ 981 udelay(50); 982 } 983 984 return 0; 985 } 986 987 static int sdma_v2_4_set_trap_irq_state(struct amdgpu_device *adev, 988 struct amdgpu_irq_src *src, 989 unsigned type, 990 enum amdgpu_interrupt_state state) 991 { 992 u32 sdma_cntl; 993 994 switch (type) { 995 case AMDGPU_SDMA_IRQ_INSTANCE0: 996 switch (state) { 997 case AMDGPU_IRQ_STATE_DISABLE: 998 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); 999 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); 1000 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); 1001 break; 1002 case AMDGPU_IRQ_STATE_ENABLE: 1003 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); 1004 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); 1005 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); 1006 break; 1007 default: 1008 break; 1009 } 1010 break; 1011 case AMDGPU_SDMA_IRQ_INSTANCE1: 1012 switch (state) { 1013 case AMDGPU_IRQ_STATE_DISABLE: 1014 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); 1015 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); 1016 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); 1017 break; 1018 case AMDGPU_IRQ_STATE_ENABLE: 1019 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); 1020 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); 1021 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); 1022 break; 1023 default: 1024 break; 1025 } 1026 break; 1027 default: 1028 break; 1029 } 1030 return 0; 1031 } 1032 1033 static int sdma_v2_4_process_trap_irq(struct amdgpu_device *adev, 1034 struct amdgpu_irq_src *source, 1035 struct amdgpu_iv_entry *entry) 1036 { 1037 u8 instance_id, queue_id; 1038 1039 instance_id = (entry->ring_id & 0x3) >> 0; 1040 queue_id = (entry->ring_id & 0xc) >> 2; 1041 DRM_DEBUG("IH: SDMA trap\n"); 1042 switch (instance_id) { 1043 case 0: 1044 switch (queue_id) { 1045 case 0: 1046 amdgpu_fence_process(&adev->sdma.instance[0].ring); 1047 break; 1048 case 1: 1049 /* XXX compute */ 1050 break; 1051 case 2: 1052 /* XXX compute */ 1053 break; 1054 } 1055 break; 1056 case 1: 1057 switch (queue_id) { 1058 case 0: 1059 amdgpu_fence_process(&adev->sdma.instance[1].ring); 1060 break; 1061 case 1: 1062 /* XXX compute */ 1063 break; 1064 case 2: 1065 /* XXX compute */ 1066 break; 1067 } 1068 break; 1069 } 1070 return 0; 1071 } 1072 1073 static int sdma_v2_4_process_illegal_inst_irq(struct amdgpu_device *adev, 1074 struct amdgpu_irq_src *source, 1075 struct amdgpu_iv_entry *entry) 1076 { 1077 u8 instance_id, queue_id; 1078 1079 DRM_ERROR("Illegal instruction in SDMA command stream\n"); 1080 instance_id = (entry->ring_id & 0x3) >> 0; 1081 queue_id = (entry->ring_id & 0xc) >> 2; 1082 1083 if (instance_id <= 1 && queue_id == 0) 1084 drm_sched_fault(&adev->sdma.instance[instance_id].ring.sched); 1085 return 0; 1086 } 1087 1088 static int sdma_v2_4_set_clockgating_state(void *handle, 1089 enum amd_clockgating_state state) 1090 { 1091 /* XXX handled via the smc on VI */ 1092 return 0; 1093 } 1094 1095 static int sdma_v2_4_set_powergating_state(void *handle, 1096 enum amd_powergating_state state) 1097 { 1098 return 0; 1099 } 1100 1101 static const struct amd_ip_funcs sdma_v2_4_ip_funcs = { 1102 .name = "sdma_v2_4", 1103 .early_init = sdma_v2_4_early_init, 1104 .late_init = NULL, 1105 .sw_init = sdma_v2_4_sw_init, 1106 .sw_fini = sdma_v2_4_sw_fini, 1107 .hw_init = sdma_v2_4_hw_init, 1108 .hw_fini = sdma_v2_4_hw_fini, 1109 .suspend = sdma_v2_4_suspend, 1110 .resume = sdma_v2_4_resume, 1111 .is_idle = sdma_v2_4_is_idle, 1112 .wait_for_idle = sdma_v2_4_wait_for_idle, 1113 .soft_reset = sdma_v2_4_soft_reset, 1114 .set_clockgating_state = sdma_v2_4_set_clockgating_state, 1115 .set_powergating_state = sdma_v2_4_set_powergating_state, 1116 }; 1117 1118 static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = { 1119 .type = AMDGPU_RING_TYPE_SDMA, 1120 .align_mask = 0xf, 1121 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 1122 .support_64bit_ptrs = false, 1123 .secure_submission_supported = true, 1124 .get_rptr = sdma_v2_4_ring_get_rptr, 1125 .get_wptr = sdma_v2_4_ring_get_wptr, 1126 .set_wptr = sdma_v2_4_ring_set_wptr, 1127 .emit_frame_size = 1128 6 + /* sdma_v2_4_ring_emit_hdp_flush */ 1129 3 + /* hdp invalidate */ 1130 6 + /* sdma_v2_4_ring_emit_pipeline_sync */ 1131 VI_FLUSH_GPU_TLB_NUM_WREG * 3 + 6 + /* sdma_v2_4_ring_emit_vm_flush */ 1132 10 + 10 + 10, /* sdma_v2_4_ring_emit_fence x3 for user fence, vm fence */ 1133 .emit_ib_size = 7 + 6, /* sdma_v2_4_ring_emit_ib */ 1134 .emit_ib = sdma_v2_4_ring_emit_ib, 1135 .emit_fence = sdma_v2_4_ring_emit_fence, 1136 .emit_pipeline_sync = sdma_v2_4_ring_emit_pipeline_sync, 1137 .emit_vm_flush = sdma_v2_4_ring_emit_vm_flush, 1138 .emit_hdp_flush = sdma_v2_4_ring_emit_hdp_flush, 1139 .test_ring = sdma_v2_4_ring_test_ring, 1140 .test_ib = sdma_v2_4_ring_test_ib, 1141 .insert_nop = sdma_v2_4_ring_insert_nop, 1142 .pad_ib = sdma_v2_4_ring_pad_ib, 1143 .emit_wreg = sdma_v2_4_ring_emit_wreg, 1144 }; 1145 1146 static void sdma_v2_4_set_ring_funcs(struct amdgpu_device *adev) 1147 { 1148 int i; 1149 1150 for (i = 0; i < adev->sdma.num_instances; i++) { 1151 adev->sdma.instance[i].ring.funcs = &sdma_v2_4_ring_funcs; 1152 adev->sdma.instance[i].ring.me = i; 1153 } 1154 } 1155 1156 static const struct amdgpu_irq_src_funcs sdma_v2_4_trap_irq_funcs = { 1157 .set = sdma_v2_4_set_trap_irq_state, 1158 .process = sdma_v2_4_process_trap_irq, 1159 }; 1160 1161 static const struct amdgpu_irq_src_funcs sdma_v2_4_illegal_inst_irq_funcs = { 1162 .process = sdma_v2_4_process_illegal_inst_irq, 1163 }; 1164 1165 static void sdma_v2_4_set_irq_funcs(struct amdgpu_device *adev) 1166 { 1167 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST; 1168 adev->sdma.trap_irq.funcs = &sdma_v2_4_trap_irq_funcs; 1169 adev->sdma.illegal_inst_irq.funcs = &sdma_v2_4_illegal_inst_irq_funcs; 1170 } 1171 1172 /** 1173 * sdma_v2_4_emit_copy_buffer - copy buffer using the sDMA engine 1174 * 1175 * @ib: indirect buffer to copy to 1176 * @src_offset: src GPU address 1177 * @dst_offset: dst GPU address 1178 * @byte_count: number of bytes to xfer 1179 * @tmz: unused 1180 * 1181 * Copy GPU buffers using the DMA engine (VI). 1182 * Used by the amdgpu ttm implementation to move pages if 1183 * registered as the asic copy callback. 1184 */ 1185 static void sdma_v2_4_emit_copy_buffer(struct amdgpu_ib *ib, 1186 uint64_t src_offset, 1187 uint64_t dst_offset, 1188 uint32_t byte_count, 1189 bool tmz) 1190 { 1191 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1192 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1193 ib->ptr[ib->length_dw++] = byte_count; 1194 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1195 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 1196 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 1197 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1198 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1199 } 1200 1201 /** 1202 * sdma_v2_4_emit_fill_buffer - fill buffer using the sDMA engine 1203 * 1204 * @ib: indirect buffer to copy to 1205 * @src_data: value to write to buffer 1206 * @dst_offset: dst GPU address 1207 * @byte_count: number of bytes to xfer 1208 * 1209 * Fill GPU buffers using the DMA engine (VI). 1210 */ 1211 static void sdma_v2_4_emit_fill_buffer(struct amdgpu_ib *ib, 1212 uint32_t src_data, 1213 uint64_t dst_offset, 1214 uint32_t byte_count) 1215 { 1216 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); 1217 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1218 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1219 ib->ptr[ib->length_dw++] = src_data; 1220 ib->ptr[ib->length_dw++] = byte_count; 1221 } 1222 1223 static const struct amdgpu_buffer_funcs sdma_v2_4_buffer_funcs = { 1224 .copy_max_bytes = 0x1fffff, 1225 .copy_num_dw = 7, 1226 .emit_copy_buffer = sdma_v2_4_emit_copy_buffer, 1227 1228 .fill_max_bytes = 0x1fffff, 1229 .fill_num_dw = 7, 1230 .emit_fill_buffer = sdma_v2_4_emit_fill_buffer, 1231 }; 1232 1233 static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device *adev) 1234 { 1235 adev->mman.buffer_funcs = &sdma_v2_4_buffer_funcs; 1236 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 1237 } 1238 1239 static const struct amdgpu_vm_pte_funcs sdma_v2_4_vm_pte_funcs = { 1240 .copy_pte_num_dw = 7, 1241 .copy_pte = sdma_v2_4_vm_copy_pte, 1242 1243 .write_pte = sdma_v2_4_vm_write_pte, 1244 .set_pte_pde = sdma_v2_4_vm_set_pte_pde, 1245 }; 1246 1247 static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev) 1248 { 1249 unsigned i; 1250 1251 adev->vm_manager.vm_pte_funcs = &sdma_v2_4_vm_pte_funcs; 1252 for (i = 0; i < adev->sdma.num_instances; i++) { 1253 adev->vm_manager.vm_pte_scheds[i] = 1254 &adev->sdma.instance[i].ring.sched; 1255 } 1256 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; 1257 } 1258 1259 const struct amdgpu_ip_block_version sdma_v2_4_ip_block = { 1260 .type = AMD_IP_BLOCK_TYPE_SDMA, 1261 .major = 2, 1262 .minor = 4, 1263 .rev = 0, 1264 .funcs = &sdma_v2_4_ip_funcs, 1265 }; 1266