1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 #include <drm/drmP.h> 28 #include "amdgpu.h" 29 #include "amdgpu_psp.h" 30 #include "amdgpu_ucode.h" 31 #include "soc15_common.h" 32 #include "psp_v3_1.h" 33 34 #include "mp/mp_9_0_offset.h" 35 #include "mp/mp_9_0_sh_mask.h" 36 #include "gc/gc_9_0_offset.h" 37 #include "sdma0/sdma0_4_0_offset.h" 38 #include "nbio/nbio_6_1_offset.h" 39 40 MODULE_FIRMWARE("amdgpu/vega10_sos.bin"); 41 MODULE_FIRMWARE("amdgpu/vega10_asd.bin"); 42 MODULE_FIRMWARE("amdgpu/vega12_sos.bin"); 43 MODULE_FIRMWARE("amdgpu/vega12_asd.bin"); 44 45 46 #define smnMP1_FIRMWARE_FLAGS 0x3010028 47 48 static uint32_t sos_old_versions[] = {1517616, 1510592, 1448594, 1446554}; 49 50 static int 51 psp_v3_1_get_fw_type(struct amdgpu_firmware_info *ucode, enum psp_gfx_fw_type *type) 52 { 53 switch(ucode->ucode_id) { 54 case AMDGPU_UCODE_ID_SDMA0: 55 *type = GFX_FW_TYPE_SDMA0; 56 break; 57 case AMDGPU_UCODE_ID_SDMA1: 58 *type = GFX_FW_TYPE_SDMA1; 59 break; 60 case AMDGPU_UCODE_ID_CP_CE: 61 *type = GFX_FW_TYPE_CP_CE; 62 break; 63 case AMDGPU_UCODE_ID_CP_PFP: 64 *type = GFX_FW_TYPE_CP_PFP; 65 break; 66 case AMDGPU_UCODE_ID_CP_ME: 67 *type = GFX_FW_TYPE_CP_ME; 68 break; 69 case AMDGPU_UCODE_ID_CP_MEC1: 70 *type = GFX_FW_TYPE_CP_MEC; 71 break; 72 case AMDGPU_UCODE_ID_CP_MEC1_JT: 73 *type = GFX_FW_TYPE_CP_MEC_ME1; 74 break; 75 case AMDGPU_UCODE_ID_CP_MEC2: 76 *type = GFX_FW_TYPE_CP_MEC; 77 break; 78 case AMDGPU_UCODE_ID_CP_MEC2_JT: 79 *type = GFX_FW_TYPE_CP_MEC_ME2; 80 break; 81 case AMDGPU_UCODE_ID_RLC_G: 82 *type = GFX_FW_TYPE_RLC_G; 83 break; 84 case AMDGPU_UCODE_ID_SMC: 85 *type = GFX_FW_TYPE_SMU; 86 break; 87 case AMDGPU_UCODE_ID_UVD: 88 *type = GFX_FW_TYPE_UVD; 89 break; 90 case AMDGPU_UCODE_ID_VCE: 91 *type = GFX_FW_TYPE_VCE; 92 break; 93 case AMDGPU_UCODE_ID_MAXIMUM: 94 default: 95 return -EINVAL; 96 } 97 98 return 0; 99 } 100 101 static int psp_v3_1_init_microcode(struct psp_context *psp) 102 { 103 struct amdgpu_device *adev = psp->adev; 104 const char *chip_name; 105 char fw_name[30]; 106 int err = 0; 107 const struct psp_firmware_header_v1_0 *hdr; 108 109 DRM_DEBUG("\n"); 110 111 switch (adev->asic_type) { 112 case CHIP_VEGA10: 113 chip_name = "vega10"; 114 break; 115 case CHIP_VEGA12: 116 chip_name = "vega12"; 117 break; 118 default: BUG(); 119 } 120 121 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name); 122 err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev); 123 if (err) 124 goto out; 125 126 err = amdgpu_ucode_validate(adev->psp.sos_fw); 127 if (err) 128 goto out; 129 130 hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 131 adev->psp.sos_fw_version = le32_to_cpu(hdr->header.ucode_version); 132 adev->psp.sos_feature_version = le32_to_cpu(hdr->ucode_feature_version); 133 adev->psp.sos_bin_size = le32_to_cpu(hdr->sos_size_bytes); 134 adev->psp.sys_bin_size = le32_to_cpu(hdr->header.ucode_size_bytes) - 135 le32_to_cpu(hdr->sos_size_bytes); 136 adev->psp.sys_start_addr = (uint8_t *)hdr + 137 le32_to_cpu(hdr->header.ucode_array_offset_bytes); 138 adev->psp.sos_start_addr = (uint8_t *)adev->psp.sys_start_addr + 139 le32_to_cpu(hdr->sos_offset_bytes); 140 141 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name); 142 err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev); 143 if (err) 144 goto out; 145 146 err = amdgpu_ucode_validate(adev->psp.asd_fw); 147 if (err) 148 goto out; 149 150 hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; 151 adev->psp.asd_fw_version = le32_to_cpu(hdr->header.ucode_version); 152 adev->psp.asd_feature_version = le32_to_cpu(hdr->ucode_feature_version); 153 adev->psp.asd_ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes); 154 adev->psp.asd_start_addr = (uint8_t *)hdr + 155 le32_to_cpu(hdr->header.ucode_array_offset_bytes); 156 157 return 0; 158 out: 159 if (err) { 160 dev_err(adev->dev, 161 "psp v3.1: Failed to load firmware \"%s\"\n", 162 fw_name); 163 release_firmware(adev->psp.sos_fw); 164 adev->psp.sos_fw = NULL; 165 release_firmware(adev->psp.asd_fw); 166 adev->psp.asd_fw = NULL; 167 } 168 169 return err; 170 } 171 172 static int psp_v3_1_bootloader_load_sysdrv(struct psp_context *psp) 173 { 174 int ret; 175 uint32_t psp_gfxdrv_command_reg = 0; 176 struct amdgpu_device *adev = psp->adev; 177 uint32_t sol_reg; 178 179 /* Check sOS sign of life register to confirm sys driver and sOS 180 * are already been loaded. 181 */ 182 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 183 if (sol_reg) 184 return 0; 185 186 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */ 187 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 188 0x80000000, 0x80000000, false); 189 if (ret) 190 return ret; 191 192 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 193 194 /* Copy PSP System Driver binary to memory */ 195 memcpy(psp->fw_pri_buf, psp->sys_start_addr, psp->sys_bin_size); 196 197 /* Provide the sys driver to bootloader */ 198 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, 199 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 200 psp_gfxdrv_command_reg = 1 << 16; 201 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 202 psp_gfxdrv_command_reg); 203 204 /* there might be handshake issue with hardware which needs delay */ 205 mdelay(20); 206 207 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 208 0x80000000, 0x80000000, false); 209 210 return ret; 211 } 212 213 static bool psp_v3_1_match_version(struct amdgpu_device *adev, uint32_t ver) 214 { 215 int i; 216 217 if (ver == adev->psp.sos_fw_version) 218 return true; 219 220 /* 221 * Double check if the latest four legacy versions. 222 * If yes, it is still the right version. 223 */ 224 for (i = 0; i < sizeof(sos_old_versions) / sizeof(uint32_t); i++) { 225 if (sos_old_versions[i] == adev->psp.sos_fw_version) 226 return true; 227 } 228 229 return false; 230 } 231 232 static int psp_v3_1_bootloader_load_sos(struct psp_context *psp) 233 { 234 int ret; 235 unsigned int psp_gfxdrv_command_reg = 0; 236 struct amdgpu_device *adev = psp->adev; 237 uint32_t sol_reg, ver; 238 239 /* Check sOS sign of life register to confirm sys driver and sOS 240 * are already been loaded. 241 */ 242 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 243 if (sol_reg) 244 return 0; 245 246 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */ 247 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 248 0x80000000, 0x80000000, false); 249 if (ret) 250 return ret; 251 252 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 253 254 /* Copy Secure OS binary to PSP memory */ 255 memcpy(psp->fw_pri_buf, psp->sos_start_addr, psp->sos_bin_size); 256 257 /* Provide the PSP secure OS to bootloader */ 258 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, 259 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 260 psp_gfxdrv_command_reg = 2 << 16; 261 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 262 psp_gfxdrv_command_reg); 263 264 /* there might be handshake issue with hardware which needs delay */ 265 mdelay(20); 266 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81), 267 RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81), 268 0, true); 269 270 ver = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58); 271 if (!psp_v3_1_match_version(adev, ver)) 272 DRM_WARN("SOS version doesn't match\n"); 273 274 return ret; 275 } 276 277 static int psp_v3_1_prep_cmd_buf(struct amdgpu_firmware_info *ucode, 278 struct psp_gfx_cmd_resp *cmd) 279 { 280 int ret; 281 uint64_t fw_mem_mc_addr = ucode->mc_addr; 282 283 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 284 285 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 286 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr); 287 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr); 288 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; 289 290 ret = psp_v3_1_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); 291 if (ret) 292 DRM_ERROR("Unknown firmware type\n"); 293 294 return ret; 295 } 296 297 static int psp_v3_1_ring_init(struct psp_context *psp, 298 enum psp_ring_type ring_type) 299 { 300 int ret = 0; 301 struct psp_ring *ring; 302 struct amdgpu_device *adev = psp->adev; 303 304 ring = &psp->km_ring; 305 306 ring->ring_type = ring_type; 307 308 /* allocate 4k Page of Local Frame Buffer memory for ring */ 309 ring->ring_size = 0x1000; 310 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE, 311 AMDGPU_GEM_DOMAIN_VRAM, 312 &adev->firmware.rbuf, 313 &ring->ring_mem_mc_addr, 314 (void **)&ring->ring_mem); 315 if (ret) { 316 ring->ring_size = 0; 317 return ret; 318 } 319 320 return 0; 321 } 322 323 static int psp_v3_1_ring_create(struct psp_context *psp, 324 enum psp_ring_type ring_type) 325 { 326 int ret = 0; 327 unsigned int psp_ring_reg = 0; 328 struct psp_ring *ring = &psp->km_ring; 329 struct amdgpu_device *adev = psp->adev; 330 331 /* Write low address of the ring to C2PMSG_69 */ 332 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 333 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg); 334 /* Write high address of the ring to C2PMSG_70 */ 335 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 336 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg); 337 /* Write size of ring to C2PMSG_71 */ 338 psp_ring_reg = ring->ring_size; 339 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg); 340 /* Write the ring initialization command to C2PMSG_64 */ 341 psp_ring_reg = ring_type; 342 psp_ring_reg = psp_ring_reg << 16; 343 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg); 344 345 /* there might be handshake issue with hardware which needs delay */ 346 mdelay(20); 347 348 /* Wait for response flag (bit 31) in C2PMSG_64 */ 349 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 350 0x80000000, 0x8000FFFF, false); 351 352 return ret; 353 } 354 355 static int psp_v3_1_ring_stop(struct psp_context *psp, 356 enum psp_ring_type ring_type) 357 { 358 int ret = 0; 359 unsigned int psp_ring_reg = 0; 360 struct amdgpu_device *adev = psp->adev; 361 362 /* Write the ring destroy command to C2PMSG_64 */ 363 psp_ring_reg = 3 << 16; 364 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg); 365 366 /* there might be handshake issue with hardware which needs delay */ 367 mdelay(20); 368 369 /* Wait for response flag (bit 31) in C2PMSG_64 */ 370 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 371 0x80000000, 0x80000000, false); 372 373 return ret; 374 } 375 376 static int psp_v3_1_ring_destroy(struct psp_context *psp, 377 enum psp_ring_type ring_type) 378 { 379 int ret = 0; 380 struct psp_ring *ring = &psp->km_ring; 381 struct amdgpu_device *adev = psp->adev; 382 383 ret = psp_v3_1_ring_stop(psp, ring_type); 384 if (ret) 385 DRM_ERROR("Fail to stop psp ring\n"); 386 387 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 388 &ring->ring_mem_mc_addr, 389 (void **)&ring->ring_mem); 390 391 return ret; 392 } 393 394 static int psp_v3_1_cmd_submit(struct psp_context *psp, 395 struct amdgpu_firmware_info *ucode, 396 uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr, 397 int index) 398 { 399 unsigned int psp_write_ptr_reg = 0; 400 struct psp_gfx_rb_frame * write_frame = psp->km_ring.ring_mem; 401 struct psp_ring *ring = &psp->km_ring; 402 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem; 403 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start + 404 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1; 405 struct amdgpu_device *adev = psp->adev; 406 uint32_t ring_size_dw = ring->ring_size / 4; 407 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; 408 409 /* KM (GPCOM) prepare write pointer */ 410 psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67); 411 412 /* Update KM RB frame pointer to new frame */ 413 /* write_frame ptr increments by size of rb_frame in bytes */ 414 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */ 415 if ((psp_write_ptr_reg % ring_size_dw) == 0) 416 write_frame = ring_buffer_start; 417 else 418 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw); 419 /* Check invalid write_frame ptr address */ 420 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) { 421 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", 422 ring_buffer_start, ring_buffer_end, write_frame); 423 DRM_ERROR("write_frame is pointing to address out of bounds\n"); 424 return -EINVAL; 425 } 426 427 /* Initialize KM RB frame */ 428 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); 429 430 /* Update KM RB frame */ 431 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); 432 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); 433 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); 434 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); 435 write_frame->fence_value = index; 436 437 /* Update the write Pointer in DWORDs */ 438 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; 439 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg); 440 441 return 0; 442 } 443 444 static int 445 psp_v3_1_sram_map(struct amdgpu_device *adev, 446 unsigned int *sram_offset, unsigned int *sram_addr_reg_offset, 447 unsigned int *sram_data_reg_offset, 448 enum AMDGPU_UCODE_ID ucode_id) 449 { 450 int ret = 0; 451 452 switch(ucode_id) { 453 /* TODO: needs to confirm */ 454 #if 0 455 case AMDGPU_UCODE_ID_SMC: 456 *sram_offset = 0; 457 *sram_addr_reg_offset = 0; 458 *sram_data_reg_offset = 0; 459 break; 460 #endif 461 462 case AMDGPU_UCODE_ID_CP_CE: 463 *sram_offset = 0x0; 464 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR); 465 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA); 466 break; 467 468 case AMDGPU_UCODE_ID_CP_PFP: 469 *sram_offset = 0x0; 470 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR); 471 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA); 472 break; 473 474 case AMDGPU_UCODE_ID_CP_ME: 475 *sram_offset = 0x0; 476 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR); 477 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA); 478 break; 479 480 case AMDGPU_UCODE_ID_CP_MEC1: 481 *sram_offset = 0x10000; 482 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR); 483 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA); 484 break; 485 486 case AMDGPU_UCODE_ID_CP_MEC2: 487 *sram_offset = 0x10000; 488 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR); 489 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA); 490 break; 491 492 case AMDGPU_UCODE_ID_RLC_G: 493 *sram_offset = 0x2000; 494 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR); 495 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA); 496 break; 497 498 case AMDGPU_UCODE_ID_SDMA0: 499 *sram_offset = 0x0; 500 *sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR); 501 *sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA); 502 break; 503 504 /* TODO: needs to confirm */ 505 #if 0 506 case AMDGPU_UCODE_ID_SDMA1: 507 *sram_offset = ; 508 *sram_addr_reg_offset = ; 509 break; 510 511 case AMDGPU_UCODE_ID_UVD: 512 *sram_offset = ; 513 *sram_addr_reg_offset = ; 514 break; 515 516 case AMDGPU_UCODE_ID_VCE: 517 *sram_offset = ; 518 *sram_addr_reg_offset = ; 519 break; 520 #endif 521 522 case AMDGPU_UCODE_ID_MAXIMUM: 523 default: 524 ret = -EINVAL; 525 break; 526 } 527 528 return ret; 529 } 530 531 static bool psp_v3_1_compare_sram_data(struct psp_context *psp, 532 struct amdgpu_firmware_info *ucode, 533 enum AMDGPU_UCODE_ID ucode_type) 534 { 535 int err = 0; 536 unsigned int fw_sram_reg_val = 0; 537 unsigned int fw_sram_addr_reg_offset = 0; 538 unsigned int fw_sram_data_reg_offset = 0; 539 unsigned int ucode_size; 540 uint32_t *ucode_mem = NULL; 541 struct amdgpu_device *adev = psp->adev; 542 543 err = psp_v3_1_sram_map(adev, &fw_sram_reg_val, &fw_sram_addr_reg_offset, 544 &fw_sram_data_reg_offset, ucode_type); 545 if (err) 546 return false; 547 548 WREG32(fw_sram_addr_reg_offset, fw_sram_reg_val); 549 550 ucode_size = ucode->ucode_size; 551 ucode_mem = (uint32_t *)ucode->kaddr; 552 while (ucode_size) { 553 fw_sram_reg_val = RREG32(fw_sram_data_reg_offset); 554 555 if (*ucode_mem != fw_sram_reg_val) 556 return false; 557 558 ucode_mem++; 559 /* 4 bytes */ 560 ucode_size -= 4; 561 } 562 563 return true; 564 } 565 566 static bool psp_v3_1_smu_reload_quirk(struct psp_context *psp) 567 { 568 struct amdgpu_device *adev = psp->adev; 569 uint32_t reg; 570 571 reg = smnMP1_FIRMWARE_FLAGS | 0x03b00000; 572 WREG32_SOC15(NBIO, 0, mmPCIE_INDEX2, reg); 573 reg = RREG32_SOC15(NBIO, 0, mmPCIE_DATA2); 574 return (reg & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) ? true : false; 575 } 576 577 static int psp_v3_1_mode1_reset(struct psp_context *psp) 578 { 579 int ret; 580 uint32_t offset; 581 struct amdgpu_device *adev = psp->adev; 582 583 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64); 584 585 ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false); 586 587 if (ret) { 588 DRM_INFO("psp is not working correctly before mode1 reset!\n"); 589 return -EINVAL; 590 } 591 592 /*send the mode 1 reset command*/ 593 WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST); 594 595 msleep(500); 596 597 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33); 598 599 ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false); 600 601 if (ret) { 602 DRM_INFO("psp mode 1 reset failed!\n"); 603 return -EINVAL; 604 } 605 606 DRM_INFO("psp mode1 reset succeed \n"); 607 608 return 0; 609 } 610 611 static const struct psp_funcs psp_v3_1_funcs = { 612 .init_microcode = psp_v3_1_init_microcode, 613 .bootloader_load_sysdrv = psp_v3_1_bootloader_load_sysdrv, 614 .bootloader_load_sos = psp_v3_1_bootloader_load_sos, 615 .prep_cmd_buf = psp_v3_1_prep_cmd_buf, 616 .ring_init = psp_v3_1_ring_init, 617 .ring_create = psp_v3_1_ring_create, 618 .ring_stop = psp_v3_1_ring_stop, 619 .ring_destroy = psp_v3_1_ring_destroy, 620 .cmd_submit = psp_v3_1_cmd_submit, 621 .compare_sram_data = psp_v3_1_compare_sram_data, 622 .smu_reload_quirk = psp_v3_1_smu_reload_quirk, 623 .mode1_reset = psp_v3_1_mode1_reset, 624 }; 625 626 void psp_v3_1_set_psp_funcs(struct psp_context *psp) 627 { 628 psp->funcs = &psp_v3_1_funcs; 629 } 630