1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 #include "drmP.h" 28 #include "amdgpu.h" 29 #include "amdgpu_psp.h" 30 #include "amdgpu_ucode.h" 31 #include "soc15_common.h" 32 #include "psp_v3_1.h" 33 34 #include "vega10/soc15ip.h" 35 #include "vega10/MP/mp_9_0_offset.h" 36 #include "vega10/MP/mp_9_0_sh_mask.h" 37 #include "vega10/GC/gc_9_0_offset.h" 38 #include "vega10/SDMA0/sdma0_4_0_offset.h" 39 #include "vega10/NBIO/nbio_6_1_offset.h" 40 41 MODULE_FIRMWARE("amdgpu/vega10_sos.bin"); 42 MODULE_FIRMWARE("amdgpu/vega10_asd.bin"); 43 44 #define smnMP1_FIRMWARE_FLAGS 0x3010028 45 46 static int 47 psp_v3_1_get_fw_type(struct amdgpu_firmware_info *ucode, enum psp_gfx_fw_type *type) 48 { 49 switch(ucode->ucode_id) { 50 case AMDGPU_UCODE_ID_SDMA0: 51 *type = GFX_FW_TYPE_SDMA0; 52 break; 53 case AMDGPU_UCODE_ID_SDMA1: 54 *type = GFX_FW_TYPE_SDMA1; 55 break; 56 case AMDGPU_UCODE_ID_CP_CE: 57 *type = GFX_FW_TYPE_CP_CE; 58 break; 59 case AMDGPU_UCODE_ID_CP_PFP: 60 *type = GFX_FW_TYPE_CP_PFP; 61 break; 62 case AMDGPU_UCODE_ID_CP_ME: 63 *type = GFX_FW_TYPE_CP_ME; 64 break; 65 case AMDGPU_UCODE_ID_CP_MEC1: 66 *type = GFX_FW_TYPE_CP_MEC; 67 break; 68 case AMDGPU_UCODE_ID_CP_MEC1_JT: 69 *type = GFX_FW_TYPE_CP_MEC_ME1; 70 break; 71 case AMDGPU_UCODE_ID_CP_MEC2: 72 *type = GFX_FW_TYPE_CP_MEC; 73 break; 74 case AMDGPU_UCODE_ID_CP_MEC2_JT: 75 *type = GFX_FW_TYPE_CP_MEC_ME2; 76 break; 77 case AMDGPU_UCODE_ID_RLC_G: 78 *type = GFX_FW_TYPE_RLC_G; 79 break; 80 case AMDGPU_UCODE_ID_SMC: 81 *type = GFX_FW_TYPE_SMU; 82 break; 83 case AMDGPU_UCODE_ID_UVD: 84 *type = GFX_FW_TYPE_UVD; 85 break; 86 case AMDGPU_UCODE_ID_VCE: 87 *type = GFX_FW_TYPE_VCE; 88 break; 89 case AMDGPU_UCODE_ID_MAXIMUM: 90 default: 91 return -EINVAL; 92 } 93 94 return 0; 95 } 96 97 int psp_v3_1_init_microcode(struct psp_context *psp) 98 { 99 struct amdgpu_device *adev = psp->adev; 100 const char *chip_name; 101 char fw_name[30]; 102 int err = 0; 103 const struct psp_firmware_header_v1_0 *hdr; 104 105 DRM_DEBUG("\n"); 106 107 switch (adev->asic_type) { 108 case CHIP_VEGA10: 109 chip_name = "vega10"; 110 break; 111 default: BUG(); 112 } 113 114 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name); 115 err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev); 116 if (err) 117 goto out; 118 119 err = amdgpu_ucode_validate(adev->psp.sos_fw); 120 if (err) 121 goto out; 122 123 hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 124 adev->psp.sos_fw_version = le32_to_cpu(hdr->header.ucode_version); 125 adev->psp.sos_feature_version = le32_to_cpu(hdr->ucode_feature_version); 126 adev->psp.sos_bin_size = le32_to_cpu(hdr->sos_size_bytes); 127 adev->psp.sys_bin_size = le32_to_cpu(hdr->header.ucode_size_bytes) - 128 le32_to_cpu(hdr->sos_size_bytes); 129 adev->psp.sys_start_addr = (uint8_t *)hdr + 130 le32_to_cpu(hdr->header.ucode_array_offset_bytes); 131 adev->psp.sos_start_addr = (uint8_t *)adev->psp.sys_start_addr + 132 le32_to_cpu(hdr->sos_offset_bytes); 133 134 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name); 135 err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev); 136 if (err) 137 goto out; 138 139 err = amdgpu_ucode_validate(adev->psp.asd_fw); 140 if (err) 141 goto out; 142 143 hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; 144 adev->psp.asd_fw_version = le32_to_cpu(hdr->header.ucode_version); 145 adev->psp.asd_feature_version = le32_to_cpu(hdr->ucode_feature_version); 146 adev->psp.asd_ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes); 147 adev->psp.asd_start_addr = (uint8_t *)hdr + 148 le32_to_cpu(hdr->header.ucode_array_offset_bytes); 149 150 return 0; 151 out: 152 if (err) { 153 dev_err(adev->dev, 154 "psp v3.1: Failed to load firmware \"%s\"\n", 155 fw_name); 156 release_firmware(adev->psp.sos_fw); 157 adev->psp.sos_fw = NULL; 158 release_firmware(adev->psp.asd_fw); 159 adev->psp.asd_fw = NULL; 160 } 161 162 return err; 163 } 164 165 int psp_v3_1_bootloader_load_sysdrv(struct psp_context *psp) 166 { 167 int ret; 168 uint32_t psp_gfxdrv_command_reg = 0; 169 struct amdgpu_bo *psp_sysdrv; 170 void *psp_sysdrv_virt = NULL; 171 uint64_t psp_sysdrv_mem; 172 struct amdgpu_device *adev = psp->adev; 173 uint32_t size, sol_reg; 174 175 /* Check sOS sign of life register to confirm sys driver and sOS 176 * are already been loaded. 177 */ 178 sol_reg = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81)); 179 if (sol_reg) 180 return 0; 181 182 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */ 183 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 184 0x80000000, 0x80000000, false); 185 if (ret) 186 return ret; 187 188 /* 189 * Create a 1 meg GART memory to store the psp sys driver 190 * binary with a 1 meg aligned address 191 */ 192 size = (psp->sys_bin_size + (PSP_BOOTLOADER_1_MEG_ALIGNMENT - 1)) & 193 (~(PSP_BOOTLOADER_1_MEG_ALIGNMENT - 1)); 194 195 ret = amdgpu_bo_create_kernel(adev, size, PSP_BOOTLOADER_1_MEG_ALIGNMENT, 196 AMDGPU_GEM_DOMAIN_GTT, 197 &psp_sysdrv, 198 &psp_sysdrv_mem, 199 &psp_sysdrv_virt); 200 if (ret) 201 return ret; 202 203 /* Copy PSP System Driver binary to memory */ 204 memcpy(psp_sysdrv_virt, psp->sys_start_addr, psp->sys_bin_size); 205 206 /* Provide the sys driver to bootrom */ 207 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_36), 208 (uint32_t)(psp_sysdrv_mem >> 20)); 209 psp_gfxdrv_command_reg = 1 << 16; 210 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 211 psp_gfxdrv_command_reg); 212 213 /* there might be handshake issue with hardware which needs delay */ 214 mdelay(20); 215 216 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 217 0x80000000, 0x80000000, false); 218 219 amdgpu_bo_free_kernel(&psp_sysdrv, &psp_sysdrv_mem, &psp_sysdrv_virt); 220 221 return ret; 222 } 223 224 int psp_v3_1_bootloader_load_sos(struct psp_context *psp) 225 { 226 int ret; 227 unsigned int psp_gfxdrv_command_reg = 0; 228 struct amdgpu_bo *psp_sos; 229 void *psp_sos_virt = NULL; 230 uint64_t psp_sos_mem; 231 struct amdgpu_device *adev = psp->adev; 232 uint32_t size, sol_reg; 233 234 /* Check sOS sign of life register to confirm sys driver and sOS 235 * are already been loaded. 236 */ 237 sol_reg = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81)); 238 if (sol_reg) 239 return 0; 240 241 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */ 242 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 243 0x80000000, 0x80000000, false); 244 if (ret) 245 return ret; 246 247 size = (psp->sos_bin_size + (PSP_BOOTLOADER_1_MEG_ALIGNMENT - 1)) & 248 (~((uint64_t)PSP_BOOTLOADER_1_MEG_ALIGNMENT - 1)); 249 250 ret = amdgpu_bo_create_kernel(adev, size, PSP_BOOTLOADER_1_MEG_ALIGNMENT, 251 AMDGPU_GEM_DOMAIN_GTT, 252 &psp_sos, 253 &psp_sos_mem, 254 &psp_sos_virt); 255 if (ret) 256 return ret; 257 258 /* Copy Secure OS binary to PSP memory */ 259 memcpy(psp_sos_virt, psp->sos_start_addr, psp->sos_bin_size); 260 261 /* Provide the PSP secure OS to bootrom */ 262 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_36), 263 (uint32_t)(psp_sos_mem >> 20)); 264 psp_gfxdrv_command_reg = 2 << 16; 265 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 266 psp_gfxdrv_command_reg); 267 268 /* there might be handshake issue with hardware which needs delay */ 269 mdelay(20); 270 #if 0 271 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81), 272 RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81)), 273 0, true); 274 #endif 275 276 amdgpu_bo_free_kernel(&psp_sos, &psp_sos_mem, &psp_sos_virt); 277 278 return ret; 279 } 280 281 int psp_v3_1_prep_cmd_buf(struct amdgpu_firmware_info *ucode, struct psp_gfx_cmd_resp *cmd) 282 { 283 int ret; 284 uint64_t fw_mem_mc_addr = ucode->mc_addr; 285 286 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 287 288 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 289 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = (uint32_t)fw_mem_mc_addr; 290 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = (uint32_t)((uint64_t)fw_mem_mc_addr >> 32); 291 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; 292 293 ret = psp_v3_1_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); 294 if (ret) 295 DRM_ERROR("Unknown firmware type\n"); 296 297 return ret; 298 } 299 300 int psp_v3_1_ring_init(struct psp_context *psp, enum psp_ring_type ring_type) 301 { 302 int ret = 0; 303 unsigned int psp_ring_reg = 0; 304 struct psp_ring *ring; 305 struct amdgpu_device *adev = psp->adev; 306 307 ring = &psp->km_ring; 308 309 ring->ring_type = ring_type; 310 311 /* allocate 4k Page of Local Frame Buffer memory for ring */ 312 ring->ring_size = 0x1000; 313 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE, 314 AMDGPU_GEM_DOMAIN_VRAM, 315 &adev->firmware.rbuf, 316 &ring->ring_mem_mc_addr, 317 (void **)&ring->ring_mem); 318 if (ret) { 319 ring->ring_size = 0; 320 return ret; 321 } 322 323 /* Write low address of the ring to C2PMSG_69 */ 324 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 325 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_69), psp_ring_reg); 326 /* Write high address of the ring to C2PMSG_70 */ 327 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 328 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_70), psp_ring_reg); 329 /* Write size of ring to C2PMSG_71 */ 330 psp_ring_reg = ring->ring_size; 331 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_71), psp_ring_reg); 332 /* Write the ring initialization command to C2PMSG_64 */ 333 psp_ring_reg = ring_type; 334 psp_ring_reg = psp_ring_reg << 16; 335 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), psp_ring_reg); 336 337 /* there might be handshake issue with hardware which needs delay */ 338 mdelay(20); 339 340 /* Wait for response flag (bit 31) in C2PMSG_64 */ 341 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 342 0x80000000, 0x8000FFFF, false); 343 344 return ret; 345 } 346 347 int psp_v3_1_cmd_submit(struct psp_context *psp, 348 struct amdgpu_firmware_info *ucode, 349 uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr, 350 int index) 351 { 352 unsigned int psp_write_ptr_reg = 0; 353 struct psp_gfx_rb_frame * write_frame = psp->km_ring.ring_mem; 354 struct psp_ring *ring = &psp->km_ring; 355 struct amdgpu_device *adev = psp->adev; 356 uint32_t ring_size_dw = ring->ring_size / 4; 357 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; 358 359 /* KM (GPCOM) prepare write pointer */ 360 psp_write_ptr_reg = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_67)); 361 362 /* Update KM RB frame pointer to new frame */ 363 /* write_frame ptr increments by size of rb_frame in bytes */ 364 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */ 365 if ((psp_write_ptr_reg % ring_size_dw) == 0) 366 write_frame = ring->ring_mem; 367 else 368 write_frame = ring->ring_mem + (psp_write_ptr_reg / rb_frame_size_dw); 369 370 /* Initialize KM RB frame */ 371 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); 372 373 /* Update KM RB frame */ 374 write_frame->cmd_buf_addr_hi = (unsigned int)(cmd_buf_mc_addr >> 32); 375 write_frame->cmd_buf_addr_lo = (unsigned int)(cmd_buf_mc_addr); 376 write_frame->fence_addr_hi = (unsigned int)(fence_mc_addr >> 32); 377 write_frame->fence_addr_lo = (unsigned int)(fence_mc_addr); 378 write_frame->fence_value = index; 379 380 /* Update the write Pointer in DWORDs */ 381 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; 382 WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_67), psp_write_ptr_reg); 383 384 return 0; 385 } 386 387 static int 388 psp_v3_1_sram_map(unsigned int *sram_offset, unsigned int *sram_addr_reg_offset, 389 unsigned int *sram_data_reg_offset, 390 enum AMDGPU_UCODE_ID ucode_id) 391 { 392 int ret = 0; 393 394 switch(ucode_id) { 395 /* TODO: needs to confirm */ 396 #if 0 397 case AMDGPU_UCODE_ID_SMC: 398 *sram_offset = 0; 399 *sram_addr_reg_offset = 0; 400 *sram_data_reg_offset = 0; 401 break; 402 #endif 403 404 case AMDGPU_UCODE_ID_CP_CE: 405 *sram_offset = 0x0; 406 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR); 407 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA); 408 break; 409 410 case AMDGPU_UCODE_ID_CP_PFP: 411 *sram_offset = 0x0; 412 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR); 413 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA); 414 break; 415 416 case AMDGPU_UCODE_ID_CP_ME: 417 *sram_offset = 0x0; 418 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR); 419 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA); 420 break; 421 422 case AMDGPU_UCODE_ID_CP_MEC1: 423 *sram_offset = 0x10000; 424 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR); 425 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA); 426 break; 427 428 case AMDGPU_UCODE_ID_CP_MEC2: 429 *sram_offset = 0x10000; 430 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR); 431 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA); 432 break; 433 434 case AMDGPU_UCODE_ID_RLC_G: 435 *sram_offset = 0x2000; 436 *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR); 437 *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA); 438 break; 439 440 case AMDGPU_UCODE_ID_SDMA0: 441 *sram_offset = 0x0; 442 *sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR); 443 *sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA); 444 break; 445 446 /* TODO: needs to confirm */ 447 #if 0 448 case AMDGPU_UCODE_ID_SDMA1: 449 *sram_offset = ; 450 *sram_addr_reg_offset = ; 451 break; 452 453 case AMDGPU_UCODE_ID_UVD: 454 *sram_offset = ; 455 *sram_addr_reg_offset = ; 456 break; 457 458 case AMDGPU_UCODE_ID_VCE: 459 *sram_offset = ; 460 *sram_addr_reg_offset = ; 461 break; 462 #endif 463 464 case AMDGPU_UCODE_ID_MAXIMUM: 465 default: 466 ret = -EINVAL; 467 break; 468 } 469 470 return ret; 471 } 472 473 bool psp_v3_1_compare_sram_data(struct psp_context *psp, 474 struct amdgpu_firmware_info *ucode, 475 enum AMDGPU_UCODE_ID ucode_type) 476 { 477 int err = 0; 478 unsigned int fw_sram_reg_val = 0; 479 unsigned int fw_sram_addr_reg_offset = 0; 480 unsigned int fw_sram_data_reg_offset = 0; 481 unsigned int ucode_size; 482 uint32_t *ucode_mem = NULL; 483 struct amdgpu_device *adev = psp->adev; 484 485 err = psp_v3_1_sram_map(&fw_sram_reg_val, &fw_sram_addr_reg_offset, 486 &fw_sram_data_reg_offset, ucode_type); 487 if (err) 488 return false; 489 490 WREG32(fw_sram_addr_reg_offset, fw_sram_reg_val); 491 492 ucode_size = ucode->ucode_size; 493 ucode_mem = (uint32_t *)ucode->kaddr; 494 while (!ucode_size) { 495 fw_sram_reg_val = RREG32(fw_sram_data_reg_offset); 496 497 if (*ucode_mem != fw_sram_reg_val) 498 return false; 499 500 ucode_mem++; 501 /* 4 bytes */ 502 ucode_size -= 4; 503 } 504 505 return true; 506 } 507 508 bool psp_v3_1_smu_reload_quirk(struct psp_context *psp) 509 { 510 struct amdgpu_device *adev = psp->adev; 511 uint32_t reg, reg_val; 512 513 reg_val = (smnMP1_FIRMWARE_FLAGS & 0xffffffff) | 0x03b00000; 514 WREG32(SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2), reg_val); 515 reg = RREG32(SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2)); 516 if ((reg & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >> 517 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT) 518 return true; 519 520 return false; 521 } 522