1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 #include <linux/module.h> 28 #include <linux/pci.h> 29 30 #include "amdgpu.h" 31 #include "amdgpu_psp.h" 32 #include "amdgpu_ucode.h" 33 #include "soc15_common.h" 34 #include "psp_v3_1.h" 35 36 #include "mp/mp_9_0_offset.h" 37 #include "mp/mp_9_0_sh_mask.h" 38 #include "gc/gc_9_0_offset.h" 39 #include "sdma0/sdma0_4_0_offset.h" 40 #include "nbio/nbio_6_1_offset.h" 41 42 #include "oss/osssys_4_0_offset.h" 43 #include "oss/osssys_4_0_sh_mask.h" 44 45 MODULE_FIRMWARE("amdgpu/vega10_sos.bin"); 46 MODULE_FIRMWARE("amdgpu/vega10_asd.bin"); 47 MODULE_FIRMWARE("amdgpu/vega10_cap.bin"); 48 MODULE_FIRMWARE("amdgpu/vega12_sos.bin"); 49 MODULE_FIRMWARE("amdgpu/vega12_asd.bin"); 50 51 52 #define smnMP1_FIRMWARE_FLAGS 0x3010028 53 54 static int psp_v3_1_ring_stop(struct psp_context *psp, 55 enum psp_ring_type ring_type); 56 57 static int psp_v3_1_init_microcode(struct psp_context *psp) 58 { 59 struct amdgpu_device *adev = psp->adev; 60 char ucode_prefix[30]; 61 int err = 0; 62 63 DRM_DEBUG("\n"); 64 65 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); 66 67 err = psp_init_sos_microcode(psp, ucode_prefix); 68 if (err) 69 return err; 70 71 err = psp_init_asd_microcode(psp, ucode_prefix); 72 if (err) 73 return err; 74 75 return 0; 76 } 77 78 static int psp_v3_1_bootloader_load_sysdrv(struct psp_context *psp) 79 { 80 int ret; 81 uint32_t psp_gfxdrv_command_reg = 0; 82 struct amdgpu_device *adev = psp->adev; 83 uint32_t sol_reg; 84 85 /* Check sOS sign of life register to confirm sys driver and sOS 86 * are already been loaded. 87 */ 88 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 89 if (sol_reg) 90 return 0; 91 92 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */ 93 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 94 0x80000000, 0x80000000, 0); 95 if (ret) 96 return ret; 97 98 /* Copy PSP System Driver binary to memory */ 99 ret = psp_copy_fw(psp, psp->sys.start_addr, psp->sys.size_bytes); 100 if (ret) 101 return ret; 102 103 /* Provide the sys driver to bootloader */ 104 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, 105 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 106 psp_gfxdrv_command_reg = PSP_BL__LOAD_SYSDRV; 107 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 108 psp_gfxdrv_command_reg); 109 110 /* there might be handshake issue with hardware which needs delay */ 111 mdelay(20); 112 113 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 114 0x80000000, 0x80000000, 0); 115 116 return ret; 117 } 118 119 static int psp_v3_1_bootloader_load_sos(struct psp_context *psp) 120 { 121 int ret; 122 unsigned int psp_gfxdrv_command_reg = 0; 123 struct amdgpu_device *adev = psp->adev; 124 uint32_t sol_reg; 125 126 /* Check sOS sign of life register to confirm sys driver and sOS 127 * are already been loaded. 128 */ 129 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 130 if (sol_reg) 131 return 0; 132 133 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */ 134 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 135 0x80000000, 0x80000000, 0); 136 if (ret) 137 return ret; 138 139 /* Copy Secure OS binary to PSP memory */ 140 ret = psp_copy_fw(psp, psp->sos.start_addr, psp->sos.size_bytes); 141 if (ret) 142 return ret; 143 144 /* Provide the PSP secure OS to bootloader */ 145 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, 146 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 147 psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV; 148 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 149 psp_gfxdrv_command_reg); 150 151 /* there might be handshake issue with hardware which needs delay */ 152 mdelay(20); 153 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81), 154 RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81), 0, 155 PSP_WAITREG_CHANGED); 156 return ret; 157 } 158 159 static void psp_v3_1_reroute_ih(struct psp_context *psp) 160 { 161 struct amdgpu_device *adev = psp->adev; 162 uint32_t tmp; 163 164 /* Change IH ring for VMC */ 165 tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1244b); 166 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1); 167 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1); 168 169 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 3); 170 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp); 171 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET); 172 173 mdelay(20); 174 psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 175 0x80000000, 0x8000FFFF, 0); 176 177 /* Change IH ring for UMC */ 178 tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1216b); 179 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1); 180 181 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 4); 182 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp); 183 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET); 184 185 mdelay(20); 186 psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 187 0x80000000, 0x8000FFFF, 0); 188 } 189 190 static int psp_v3_1_ring_create(struct psp_context *psp, 191 enum psp_ring_type ring_type) 192 { 193 int ret = 0; 194 unsigned int psp_ring_reg = 0; 195 struct psp_ring *ring = &psp->km_ring; 196 struct amdgpu_device *adev = psp->adev; 197 198 psp_v3_1_reroute_ih(psp); 199 200 if (amdgpu_sriov_vf(adev)) { 201 ring->ring_wptr = 0; 202 ret = psp_v3_1_ring_stop(psp, ring_type); 203 if (ret) { 204 DRM_ERROR("psp_v3_1_ring_stop_sriov failed!\n"); 205 return ret; 206 } 207 208 /* Write low address of the ring to C2PMSG_102 */ 209 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 210 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg); 211 /* Write high address of the ring to C2PMSG_103 */ 212 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 213 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg); 214 /* No size initialization for sriov */ 215 /* Write the ring initialization command to C2PMSG_101 */ 216 psp_ring_reg = ring_type; 217 psp_ring_reg = psp_ring_reg << 16; 218 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, psp_ring_reg); 219 220 /* there might be hardware handshake issue which needs delay */ 221 mdelay(20); 222 223 /* Wait for response flag (bit 31) in C2PMSG_101 */ 224 ret = psp_wait_for( 225 psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), 226 0x80000000, 0x8000FFFF, 0); 227 } else { 228 229 /* Write low address of the ring to C2PMSG_69 */ 230 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 231 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg); 232 /* Write high address of the ring to C2PMSG_70 */ 233 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 234 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg); 235 /* Write size of ring to C2PMSG_71 */ 236 psp_ring_reg = ring->ring_size; 237 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg); 238 /* Write the ring initialization command to C2PMSG_64 */ 239 psp_ring_reg = ring_type; 240 psp_ring_reg = psp_ring_reg << 16; 241 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg); 242 243 /* there might be hardware handshake issue which needs delay */ 244 mdelay(20); 245 246 /* Wait for response flag (bit 31) in C2PMSG_64 */ 247 ret = psp_wait_for( 248 psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 249 0x80000000, 0x8000FFFF, 0); 250 } 251 return ret; 252 } 253 254 static int psp_v3_1_ring_stop(struct psp_context *psp, 255 enum psp_ring_type ring_type) 256 { 257 int ret = 0; 258 struct amdgpu_device *adev = psp->adev; 259 260 /* Write the ring destroy command*/ 261 if (amdgpu_sriov_vf(adev)) 262 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, 263 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING); 264 else 265 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, 266 GFX_CTRL_CMD_ID_DESTROY_RINGS); 267 268 /* there might be handshake issue with hardware which needs delay */ 269 mdelay(20); 270 271 /* Wait for response flag (bit 31) */ 272 if (amdgpu_sriov_vf(adev)) 273 ret = psp_wait_for( 274 psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), 275 0x80000000, 0x80000000, 0); 276 else 277 ret = psp_wait_for( 278 psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 279 0x80000000, 0x80000000, 0); 280 281 return ret; 282 } 283 284 static int psp_v3_1_ring_destroy(struct psp_context *psp, 285 enum psp_ring_type ring_type) 286 { 287 int ret = 0; 288 struct psp_ring *ring = &psp->km_ring; 289 struct amdgpu_device *adev = psp->adev; 290 291 ret = psp_v3_1_ring_stop(psp, ring_type); 292 if (ret) 293 DRM_ERROR("Fail to stop psp ring\n"); 294 295 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 296 &ring->ring_mem_mc_addr, 297 (void **)&ring->ring_mem); 298 299 return ret; 300 } 301 302 static bool psp_v3_1_smu_reload_quirk(struct psp_context *psp) 303 { 304 struct amdgpu_device *adev = psp->adev; 305 uint32_t reg; 306 307 reg = RREG32_PCIE(smnMP1_FIRMWARE_FLAGS | 0x03b00000); 308 return (reg & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) ? true : false; 309 } 310 311 static int psp_v3_1_mode1_reset(struct psp_context *psp) 312 { 313 int ret; 314 uint32_t offset; 315 struct amdgpu_device *adev = psp->adev; 316 317 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64); 318 319 ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, 0); 320 321 if (ret) { 322 drm_info(adev_to_drm(adev), "psp is not working correctly before mode1 reset!\n"); 323 return -EINVAL; 324 } 325 326 /*send the mode 1 reset command*/ 327 WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST); 328 329 msleep(500); 330 331 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33); 332 333 ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, 0); 334 335 if (ret) { 336 drm_info(adev_to_drm(adev), "psp mode 1 reset failed!\n"); 337 return -EINVAL; 338 } 339 340 drm_info(adev_to_drm(adev), "psp mode1 reset succeed\n"); 341 342 return 0; 343 } 344 345 static uint32_t psp_v3_1_ring_get_wptr(struct psp_context *psp) 346 { 347 uint32_t data; 348 struct amdgpu_device *adev = psp->adev; 349 350 if (amdgpu_sriov_vf(adev)) 351 data = psp->km_ring.ring_wptr; 352 else 353 data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67); 354 return data; 355 } 356 357 static void psp_v3_1_ring_set_wptr(struct psp_context *psp, uint32_t value) 358 { 359 struct amdgpu_device *adev = psp->adev; 360 361 if (amdgpu_sriov_vf(adev)) { 362 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, value); 363 /* send interrupt to PSP for SRIOV ring write pointer update */ 364 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, 365 GFX_CTRL_CMD_ID_CONSUME_CMD); 366 psp->km_ring.ring_wptr = value; 367 } else 368 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value); 369 } 370 371 static const struct psp_funcs psp_v3_1_funcs = { 372 .init_microcode = psp_v3_1_init_microcode, 373 .bootloader_load_sysdrv = psp_v3_1_bootloader_load_sysdrv, 374 .bootloader_load_sos = psp_v3_1_bootloader_load_sos, 375 .ring_create = psp_v3_1_ring_create, 376 .ring_stop = psp_v3_1_ring_stop, 377 .ring_destroy = psp_v3_1_ring_destroy, 378 .smu_reload_quirk = psp_v3_1_smu_reload_quirk, 379 .mode1_reset = psp_v3_1_mode1_reset, 380 .ring_get_wptr = psp_v3_1_ring_get_wptr, 381 .ring_set_wptr = psp_v3_1_ring_set_wptr, 382 }; 383 384 void psp_v3_1_set_psp_funcs(struct psp_context *psp) 385 { 386 psp->funcs = &psp_v3_1_funcs; 387 } 388