1 /* 2 * Copyright 2025 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <drm/drm_drv.h> 24 #include <linux/vmalloc.h> 25 #include "amdgpu.h" 26 #include "amdgpu_psp.h" 27 #include "amdgpu_ucode.h" 28 #include "soc15_common.h" 29 #include "psp_v15_0_8.h" 30 31 #include "mp/mp_15_0_8_offset.h" 32 #include "mp/mp_15_0_8_sh_mask.h" 33 34 MODULE_FIRMWARE("amdgpu/psp_15_0_8_toc.bin"); 35 MODULE_FIRMWARE("amdgpu/psp_15_0_8_toc_1.bin"); 36 37 static int psp_v15_0_8_init_microcode(struct psp_context *psp) 38 { 39 struct amdgpu_device *adev = psp->adev; 40 char ucode_prefix[30]; 41 int err = 0; 42 43 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); 44 45 err = psp_init_toc_microcode(psp, ucode_prefix); 46 if (err) 47 return err; 48 49 return 0; 50 } 51 52 static int psp_v15_0_8_ring_stop(struct psp_context *psp, 53 enum psp_ring_type ring_type) 54 { 55 int ret = 0; 56 struct amdgpu_device *adev = psp->adev; 57 58 if (amdgpu_sriov_vf(adev)) { 59 /* Write the ring destroy command*/ 60 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_101, 61 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING); 62 /* there might be handshake issue with hardware which needs delay */ 63 mdelay(20); 64 /* Wait for response flag (bit 31) */ 65 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_101), 66 0x80000000, 0x80000000, false); 67 } else { 68 /* Write the ring destroy command*/ 69 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_64, 70 GFX_CTRL_CMD_ID_DESTROY_RINGS); 71 /* there might be handshake issue with hardware which needs delay */ 72 mdelay(20); 73 /* Wait for response flag (bit 31) */ 74 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_64), 75 0x80000000, 0x80000000, false); 76 } 77 78 return ret; 79 } 80 81 static int psp_v15_0_8_ring_create(struct psp_context *psp, 82 enum psp_ring_type ring_type) 83 { 84 int ret = 0; 85 unsigned int psp_ring_reg = 0; 86 struct psp_ring *ring = &psp->km_ring; 87 struct amdgpu_device *adev = psp->adev; 88 89 if (amdgpu_sriov_vf(adev)) { 90 ret = psp_v15_0_8_ring_stop(psp, ring_type); 91 if (ret) { 92 DRM_ERROR("psp_v14_0_ring_stop_sriov failed!\n"); 93 return ret; 94 } 95 96 /* Write low address of the ring to C2PMSG_102 */ 97 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 98 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_102, psp_ring_reg); 99 /* Write high address of the ring to C2PMSG_103 */ 100 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 101 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_103, psp_ring_reg); 102 103 /* Write the ring initialization command to C2PMSG_101 */ 104 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_101, 105 GFX_CTRL_CMD_ID_INIT_GPCOM_RING); 106 107 /* there might be handshake issue with hardware which needs delay */ 108 mdelay(20); 109 110 /* Wait for response flag (bit 31) in C2PMSG_101 */ 111 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_101), 112 0x80000000, 0x8000FFFF, false); 113 114 } else { 115 /* Wait for sOS ready for ring creation */ 116 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_64), 117 0x80000000, 0x80000000, false); 118 if (ret) { 119 DRM_ERROR("Failed to wait for trust OS ready for ring creation\n"); 120 return ret; 121 } 122 123 /* Write low address of the ring to C2PMSG_69 */ 124 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 125 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_69, psp_ring_reg); 126 /* Write high address of the ring to C2PMSG_70 */ 127 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 128 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_70, psp_ring_reg); 129 /* Write size of ring to C2PMSG_71 */ 130 psp_ring_reg = ring->ring_size; 131 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_71, psp_ring_reg); 132 /* Write the ring initialization command to C2PMSG_64 */ 133 psp_ring_reg = ring_type; 134 psp_ring_reg = psp_ring_reg << 16; 135 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_64, psp_ring_reg); 136 137 /* there might be handshake issue with hardware which needs delay */ 138 mdelay(20); 139 140 /* Wait for response flag (bit 31) in C2PMSG_64 */ 141 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_64), 142 0x80000000, 0x8000FFFF, false); 143 } 144 145 return ret; 146 } 147 148 static int psp_v15_0_8_ring_destroy(struct psp_context *psp, 149 enum psp_ring_type ring_type) 150 { 151 int ret = 0; 152 struct psp_ring *ring = &psp->km_ring; 153 struct amdgpu_device *adev = psp->adev; 154 155 ret = psp_v15_0_8_ring_stop(psp, ring_type); 156 if (ret) 157 DRM_ERROR("Fail to stop psp ring\n"); 158 159 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 160 &ring->ring_mem_mc_addr, 161 (void **)&ring->ring_mem); 162 163 return ret; 164 } 165 166 static uint32_t psp_v15_0_8_ring_get_wptr(struct psp_context *psp) 167 { 168 uint32_t data; 169 struct amdgpu_device *adev = psp->adev; 170 171 if (amdgpu_sriov_vf(adev)) 172 data = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_102); 173 else 174 data = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_67); 175 176 return data; 177 } 178 179 static void psp_v15_0_8_ring_set_wptr(struct psp_context *psp, uint32_t value) 180 { 181 struct amdgpu_device *adev = psp->adev; 182 183 if (amdgpu_sriov_vf(adev)) { 184 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_102, value); 185 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_101, 186 GFX_CTRL_CMD_ID_CONSUME_CMD); 187 } else 188 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_67, value); 189 } 190 191 static bool psp_v15_0_8_get_ras_capability(struct psp_context *psp) 192 { 193 struct amdgpu_device *adev = psp->adev; 194 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 195 u32 reg_data; 196 197 /* query ras cap should be done from host side */ 198 if (amdgpu_sriov_vf(adev)) 199 return false; 200 201 if (!con) 202 return false; 203 204 reg_data = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_127); 205 adev->ras_hw_enabled = (reg_data & GENMASK_ULL(23, 0)); 206 con->poison_supported = ((reg_data & GENMASK_ULL(24, 24)) >> 24) ? true : false; 207 208 return true; 209 } 210 211 static int psp_v15_0_8_get_fw_type(struct amdgpu_firmware_info *ucode, 212 enum psp_gfx_fw_type *type) 213 { 214 switch (ucode->ucode_id) { 215 case AMDGPU_UCODE_ID_CAP: 216 *type = GFX_FW_TYPE_CAP; 217 break; 218 case AMDGPU_UCODE_ID_SDMA0: 219 *type = GFX_FW_TYPE_SDMA0; 220 break; 221 case AMDGPU_UCODE_ID_SDMA1: 222 *type = GFX_FW_TYPE_SDMA1; 223 break; 224 case AMDGPU_UCODE_ID_SDMA2: 225 *type = GFX_FW_TYPE_SDMA2; 226 break; 227 case AMDGPU_UCODE_ID_SDMA3: 228 *type = GFX_FW_TYPE_SDMA3; 229 break; 230 case AMDGPU_UCODE_ID_SDMA4: 231 *type = GFX_FW_TYPE_SDMA4; 232 break; 233 case AMDGPU_UCODE_ID_SDMA5: 234 *type = GFX_FW_TYPE_SDMA5; 235 break; 236 case AMDGPU_UCODE_ID_SDMA6: 237 *type = GFX_FW_TYPE_SDMA6; 238 break; 239 case AMDGPU_UCODE_ID_SDMA7: 240 *type = GFX_FW_TYPE_SDMA7; 241 break; 242 case AMDGPU_UCODE_ID_CP_MES: 243 *type = GFX_FW_TYPE_RS64_MES; 244 break; 245 case AMDGPU_UCODE_ID_CP_MES_DATA: 246 *type = GFX_FW_TYPE_RS64_MES_STACK; 247 break; 248 case AMDGPU_UCODE_ID_CP_MES1: 249 *type = GFX_FW_TYPE_RS64_KIQ; 250 break; 251 case AMDGPU_UCODE_ID_CP_MES1_DATA: 252 *type = GFX_FW_TYPE_RS64_KIQ_STACK; 253 break; 254 case AMDGPU_UCODE_ID_RLC_P: 255 *type = GFX_FW_TYPE_RLC_P; 256 break; 257 case AMDGPU_UCODE_ID_RLC_V: 258 *type = GFX_FW_TYPE_RLC_V; 259 break; 260 case AMDGPU_UCODE_ID_RLC_G: 261 *type = GFX_FW_TYPE_RLC_G; 262 break; 263 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 264 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL; 265 break; 266 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 267 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM; 268 break; 269 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 270 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM; 271 break; 272 case AMDGPU_UCODE_ID_RLC_IRAM: 273 *type = GFX_FW_TYPE_RLC_IRAM; 274 break; 275 case AMDGPU_UCODE_ID_RLC_DRAM: 276 *type = GFX_FW_TYPE_RLC_DRAM_BOOT; 277 break; 278 case AMDGPU_UCODE_ID_RLC_IRAM_1: 279 *type = GFX_FW_TYPE_RLX6_UCODE_CORE1; 280 break; 281 case AMDGPU_UCODE_ID_RLC_DRAM_1: 282 *type = GFX_FW_TYPE_RLX6_DRAM_BOOT_CORE1; 283 break; 284 case AMDGPU_UCODE_ID_SMC: 285 *type = GFX_FW_TYPE_SMU; 286 break; 287 case AMDGPU_UCODE_ID_PPTABLE: 288 *type = GFX_FW_TYPE_PPTABLE; 289 break; 290 case AMDGPU_UCODE_ID_VCN: 291 *type = GFX_FW_TYPE_VCN; 292 break; 293 case AMDGPU_UCODE_ID_VCN1: 294 *type = GFX_FW_TYPE_VCN1; 295 break; 296 case AMDGPU_UCODE_ID_VCN0_RAM: 297 *type = GFX_FW_TYPE_VCN0_RAM; 298 break; 299 case AMDGPU_UCODE_ID_VCN1_RAM: 300 *type = GFX_FW_TYPE_VCN1_RAM; 301 break; 302 case AMDGPU_UCODE_ID_SDMA_UCODE_TH0: 303 case AMDGPU_UCODE_ID_SDMA_RS64: 304 *type = GFX_FW_TYPE_SDMA0; 305 break; 306 case AMDGPU_UCODE_ID_SDMA_UCODE_TH1: 307 *type = GFX_FW_TYPE_SDMA_UCODE_TH1; 308 break; 309 case AMDGPU_UCODE_ID_IMU_I: 310 *type = GFX_FW_TYPE_IMU_I; 311 break; 312 case AMDGPU_UCODE_ID_IMU_D: 313 *type = GFX_FW_TYPE_IMU_D; 314 break; 315 case AMDGPU_UCODE_ID_CP_RS64_MEC: 316 *type = GFX_FW_TYPE_RS64_MEC; 317 break; 318 case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK: 319 *type = GFX_FW_TYPE_RS64_MEC_P0_STACK; 320 break; 321 case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK: 322 *type = GFX_FW_TYPE_RS64_MEC_P1_STACK; 323 break; 324 case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK: 325 *type = GFX_FW_TYPE_RS64_MEC_P2_STACK; 326 break; 327 case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK: 328 *type = GFX_FW_TYPE_RS64_MEC_P3_STACK; 329 break; 330 case AMDGPU_UCODE_ID_UMSCH_MM_UCODE: 331 *type = GFX_FW_TYPE_UMSCH_UCODE; 332 break; 333 case AMDGPU_UCODE_ID_UMSCH_MM_DATA: 334 *type = GFX_FW_TYPE_UMSCH_DATA; 335 break; 336 case AMDGPU_UCODE_ID_UMSCH_MM_CMD_BUFFER: 337 *type = GFX_FW_TYPE_UMSCH_CMD_BUFFER; 338 break; 339 case AMDGPU_UCODE_ID_P2S_TABLE: 340 *type = GFX_FW_TYPE_P2S_TABLE; 341 break; 342 case AMDGPU_UCODE_ID_MAXIMUM: 343 default: 344 return -EINVAL; 345 } 346 347 return 0; 348 } 349 350 static const struct psp_funcs psp_v15_0_8_funcs = { 351 .init_microcode = psp_v15_0_8_init_microcode, 352 .ring_create = psp_v15_0_8_ring_create, 353 .ring_stop = psp_v15_0_8_ring_stop, 354 .ring_destroy = psp_v15_0_8_ring_destroy, 355 .ring_get_wptr = psp_v15_0_8_ring_get_wptr, 356 .ring_set_wptr = psp_v15_0_8_ring_set_wptr, 357 .get_fw_type = psp_v15_0_8_get_fw_type, 358 .get_ras_capability = psp_v15_0_8_get_ras_capability, 359 }; 360 361 void psp_v15_0_8_set_psp_funcs(struct psp_context *psp) 362 { 363 psp->funcs = &psp_v15_0_8_funcs; 364 } 365