1 /* 2 * Copyright 2025 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <drm/drm_drv.h> 24 #include <linux/vmalloc.h> 25 #include "amdgpu.h" 26 #include "amdgpu_psp.h" 27 #include "amdgpu_ucode.h" 28 #include "soc15_common.h" 29 #include "psp_v15_0_8.h" 30 31 #include "mp/mp_15_0_8_offset.h" 32 #include "mp/mp_15_0_8_sh_mask.h" 33 34 MODULE_FIRMWARE("amdgpu/psp_15_0_8_toc.bin"); 35 36 static int psp_v15_0_8_init_microcode(struct psp_context *psp) 37 { 38 struct amdgpu_device *adev = psp->adev; 39 char ucode_prefix[30]; 40 int err = 0; 41 42 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); 43 44 err = psp_init_toc_microcode(psp, ucode_prefix); 45 if (err) 46 return err; 47 48 return 0; 49 } 50 51 static int psp_v15_0_8_ring_stop(struct psp_context *psp, 52 enum psp_ring_type ring_type) 53 { 54 int ret = 0; 55 struct amdgpu_device *adev = psp->adev; 56 57 if (amdgpu_sriov_vf(adev)) { 58 /* Write the ring destroy command*/ 59 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_101, 60 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING); 61 /* there might be handshake issue with hardware which needs delay */ 62 mdelay(20); 63 /* Wait for response flag (bit 31) */ 64 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_101), 65 0x80000000, 0x80000000, false); 66 } else { 67 /* Write the ring destroy command*/ 68 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_64, 69 GFX_CTRL_CMD_ID_DESTROY_RINGS); 70 /* there might be handshake issue with hardware which needs delay */ 71 mdelay(20); 72 /* Wait for response flag (bit 31) */ 73 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_64), 74 0x80000000, 0x80000000, false); 75 } 76 77 return ret; 78 } 79 80 static int psp_v15_0_8_ring_create(struct psp_context *psp, 81 enum psp_ring_type ring_type) 82 { 83 int ret = 0; 84 unsigned int psp_ring_reg = 0; 85 struct psp_ring *ring = &psp->km_ring; 86 struct amdgpu_device *adev = psp->adev; 87 88 if (amdgpu_sriov_vf(adev)) { 89 ret = psp_v15_0_8_ring_stop(psp, ring_type); 90 if (ret) { 91 DRM_ERROR("psp_v14_0_ring_stop_sriov failed!\n"); 92 return ret; 93 } 94 95 /* Write low address of the ring to C2PMSG_102 */ 96 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 97 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_102, psp_ring_reg); 98 /* Write high address of the ring to C2PMSG_103 */ 99 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 100 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_103, psp_ring_reg); 101 102 /* Write the ring initialization command to C2PMSG_101 */ 103 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_101, 104 GFX_CTRL_CMD_ID_INIT_GPCOM_RING); 105 106 /* there might be handshake issue with hardware which needs delay */ 107 mdelay(20); 108 109 /* Wait for response flag (bit 31) in C2PMSG_101 */ 110 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_101), 111 0x80000000, 0x8000FFFF, false); 112 113 } else { 114 /* Wait for sOS ready for ring creation */ 115 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_64), 116 0x80000000, 0x80000000, false); 117 if (ret) { 118 DRM_ERROR("Failed to wait for trust OS ready for ring creation\n"); 119 return ret; 120 } 121 122 /* Write low address of the ring to C2PMSG_69 */ 123 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 124 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_69, psp_ring_reg); 125 /* Write high address of the ring to C2PMSG_70 */ 126 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 127 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_70, psp_ring_reg); 128 /* Write size of ring to C2PMSG_71 */ 129 psp_ring_reg = ring->ring_size; 130 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_71, psp_ring_reg); 131 /* Write the ring initialization command to C2PMSG_64 */ 132 psp_ring_reg = ring_type; 133 psp_ring_reg = psp_ring_reg << 16; 134 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_64, psp_ring_reg); 135 136 /* there might be handshake issue with hardware which needs delay */ 137 mdelay(20); 138 139 /* Wait for response flag (bit 31) in C2PMSG_64 */ 140 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_64), 141 0x80000000, 0x8000FFFF, false); 142 } 143 144 return ret; 145 } 146 147 static int psp_v15_0_8_ring_destroy(struct psp_context *psp, 148 enum psp_ring_type ring_type) 149 { 150 int ret = 0; 151 struct psp_ring *ring = &psp->km_ring; 152 struct amdgpu_device *adev = psp->adev; 153 154 ret = psp_v15_0_8_ring_stop(psp, ring_type); 155 if (ret) 156 DRM_ERROR("Fail to stop psp ring\n"); 157 158 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 159 &ring->ring_mem_mc_addr, 160 (void **)&ring->ring_mem); 161 162 return ret; 163 } 164 165 static uint32_t psp_v15_0_8_ring_get_wptr(struct psp_context *psp) 166 { 167 uint32_t data; 168 struct amdgpu_device *adev = psp->adev; 169 170 if (amdgpu_sriov_vf(adev)) 171 data = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_102); 172 else 173 data = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_67); 174 175 return data; 176 } 177 178 static void psp_v15_0_8_ring_set_wptr(struct psp_context *psp, uint32_t value) 179 { 180 struct amdgpu_device *adev = psp->adev; 181 182 if (amdgpu_sriov_vf(adev)) { 183 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_102, value); 184 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_101, 185 GFX_CTRL_CMD_ID_CONSUME_CMD); 186 } else 187 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_67, value); 188 } 189 190 static int psp_v15_0_8_get_fw_type(struct amdgpu_firmware_info *ucode, 191 enum psp_gfx_fw_type *type) 192 { 193 switch (ucode->ucode_id) { 194 case AMDGPU_UCODE_ID_CAP: 195 *type = GFX_FW_TYPE_CAP; 196 break; 197 case AMDGPU_UCODE_ID_SDMA0: 198 *type = GFX_FW_TYPE_SDMA0; 199 break; 200 case AMDGPU_UCODE_ID_SDMA1: 201 *type = GFX_FW_TYPE_SDMA1; 202 break; 203 case AMDGPU_UCODE_ID_SDMA2: 204 *type = GFX_FW_TYPE_SDMA2; 205 break; 206 case AMDGPU_UCODE_ID_SDMA3: 207 *type = GFX_FW_TYPE_SDMA3; 208 break; 209 case AMDGPU_UCODE_ID_SDMA4: 210 *type = GFX_FW_TYPE_SDMA4; 211 break; 212 case AMDGPU_UCODE_ID_SDMA5: 213 *type = GFX_FW_TYPE_SDMA5; 214 break; 215 case AMDGPU_UCODE_ID_SDMA6: 216 *type = GFX_FW_TYPE_SDMA6; 217 break; 218 case AMDGPU_UCODE_ID_SDMA7: 219 *type = GFX_FW_TYPE_SDMA7; 220 break; 221 case AMDGPU_UCODE_ID_CP_MES: 222 *type = GFX_FW_TYPE_RS64_MES; 223 break; 224 case AMDGPU_UCODE_ID_CP_MES_DATA: 225 *type = GFX_FW_TYPE_RS64_MES_STACK; 226 break; 227 case AMDGPU_UCODE_ID_CP_MES1: 228 *type = GFX_FW_TYPE_RS64_KIQ; 229 break; 230 case AMDGPU_UCODE_ID_CP_MES1_DATA: 231 *type = GFX_FW_TYPE_RS64_KIQ_STACK; 232 break; 233 case AMDGPU_UCODE_ID_RLC_P: 234 *type = GFX_FW_TYPE_RLC_P; 235 break; 236 case AMDGPU_UCODE_ID_RLC_V: 237 *type = GFX_FW_TYPE_RLC_V; 238 break; 239 case AMDGPU_UCODE_ID_RLC_G: 240 *type = GFX_FW_TYPE_RLC_G; 241 break; 242 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 243 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL; 244 break; 245 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 246 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM; 247 break; 248 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 249 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM; 250 break; 251 case AMDGPU_UCODE_ID_RLC_IRAM: 252 *type = GFX_FW_TYPE_RLC_IRAM; 253 break; 254 case AMDGPU_UCODE_ID_RLC_DRAM: 255 *type = GFX_FW_TYPE_RLC_DRAM_BOOT; 256 break; 257 case AMDGPU_UCODE_ID_RLC_IRAM_1: 258 *type = GFX_FW_TYPE_RLX6_UCODE_CORE1; 259 break; 260 case AMDGPU_UCODE_ID_RLC_DRAM_1: 261 *type = GFX_FW_TYPE_RLX6_DRAM_BOOT_CORE1; 262 break; 263 case AMDGPU_UCODE_ID_SMC: 264 *type = GFX_FW_TYPE_SMU; 265 break; 266 case AMDGPU_UCODE_ID_PPTABLE: 267 *type = GFX_FW_TYPE_PPTABLE; 268 break; 269 case AMDGPU_UCODE_ID_VCN: 270 *type = GFX_FW_TYPE_VCN; 271 break; 272 case AMDGPU_UCODE_ID_VCN1: 273 *type = GFX_FW_TYPE_VCN1; 274 break; 275 case AMDGPU_UCODE_ID_VCN0_RAM: 276 *type = GFX_FW_TYPE_VCN0_RAM; 277 break; 278 case AMDGPU_UCODE_ID_VCN1_RAM: 279 *type = GFX_FW_TYPE_VCN1_RAM; 280 break; 281 case AMDGPU_UCODE_ID_SDMA_UCODE_TH0: 282 case AMDGPU_UCODE_ID_SDMA_RS64: 283 *type = GFX_FW_TYPE_SDMA0; 284 break; 285 case AMDGPU_UCODE_ID_SDMA_UCODE_TH1: 286 *type = GFX_FW_TYPE_SDMA_UCODE_TH1; 287 break; 288 case AMDGPU_UCODE_ID_IMU_I: 289 *type = GFX_FW_TYPE_IMU_I; 290 break; 291 case AMDGPU_UCODE_ID_IMU_D: 292 *type = GFX_FW_TYPE_IMU_D; 293 break; 294 case AMDGPU_UCODE_ID_CP_RS64_MEC: 295 *type = GFX_FW_TYPE_RS64_MEC; 296 break; 297 case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK: 298 *type = GFX_FW_TYPE_RS64_MEC_P0_STACK; 299 break; 300 case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK: 301 *type = GFX_FW_TYPE_RS64_MEC_P1_STACK; 302 break; 303 case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK: 304 *type = GFX_FW_TYPE_RS64_MEC_P2_STACK; 305 break; 306 case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK: 307 *type = GFX_FW_TYPE_RS64_MEC_P3_STACK; 308 break; 309 case AMDGPU_UCODE_ID_UMSCH_MM_UCODE: 310 *type = GFX_FW_TYPE_UMSCH_UCODE; 311 break; 312 case AMDGPU_UCODE_ID_UMSCH_MM_DATA: 313 *type = GFX_FW_TYPE_UMSCH_DATA; 314 break; 315 case AMDGPU_UCODE_ID_UMSCH_MM_CMD_BUFFER: 316 *type = GFX_FW_TYPE_UMSCH_CMD_BUFFER; 317 break; 318 case AMDGPU_UCODE_ID_P2S_TABLE: 319 *type = GFX_FW_TYPE_P2S_TABLE; 320 break; 321 case AMDGPU_UCODE_ID_MAXIMUM: 322 default: 323 return -EINVAL; 324 } 325 326 return 0; 327 } 328 329 static const struct psp_funcs psp_v15_0_8_funcs = { 330 .init_microcode = psp_v15_0_8_init_microcode, 331 .ring_create = psp_v15_0_8_ring_create, 332 .ring_stop = psp_v15_0_8_ring_stop, 333 .ring_destroy = psp_v15_0_8_ring_destroy, 334 .ring_get_wptr = psp_v15_0_8_ring_get_wptr, 335 .ring_set_wptr = psp_v15_0_8_ring_set_wptr, 336 .get_fw_type = psp_v15_0_8_get_fw_type, 337 }; 338 339 void psp_v15_0_8_set_psp_funcs(struct psp_context *psp) 340 { 341 psp->funcs = &psp_v15_0_8_funcs; 342 } 343