1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <drm/drm_drv.h> 24 #include <linux/vmalloc.h> 25 #include "amdgpu.h" 26 #include "amdgpu_psp.h" 27 #include "amdgpu_ucode.h" 28 #include "soc15_common.h" 29 #include "psp_v14_0.h" 30 31 #include "mp/mp_14_0_2_offset.h" 32 #include "mp/mp_14_0_2_sh_mask.h" 33 34 MODULE_FIRMWARE("amdgpu/psp_14_0_2_sos.bin"); 35 MODULE_FIRMWARE("amdgpu/psp_14_0_2_ta.bin"); 36 MODULE_FIRMWARE("amdgpu/psp_14_0_3_sos.bin"); 37 MODULE_FIRMWARE("amdgpu/psp_14_0_3_ta.bin"); 38 MODULE_FIRMWARE("amdgpu/psp_14_0_5_toc.bin"); 39 MODULE_FIRMWARE("amdgpu/psp_14_0_5_ta.bin"); 40 41 /* For large FW files the time to complete can be very long */ 42 #define USBC_PD_POLLING_LIMIT_S 240 43 44 /* Read USB-PD from LFB */ 45 #define GFX_CMD_USB_PD_USE_LFB 0x480 46 47 /* VBIOS gfl defines */ 48 #define MBOX_READY_MASK 0x80000000 49 #define MBOX_STATUS_MASK 0x0000FFFF 50 #define MBOX_COMMAND_MASK 0x00FF0000 51 #define MBOX_READY_FLAG 0x80000000 52 #define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_LO 0x2 53 #define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI 0x3 54 #define C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE 0x4 55 56 /* memory training timeout define */ 57 #define MEM_TRAIN_SEND_MSG_TIMEOUT_US 3000000 58 59 static int psp_v14_0_init_microcode(struct psp_context *psp) 60 { 61 struct amdgpu_device *adev = psp->adev; 62 char ucode_prefix[30]; 63 int err = 0; 64 65 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); 66 67 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 68 case IP_VERSION(14, 0, 2): 69 case IP_VERSION(14, 0, 3): 70 err = psp_init_sos_microcode(psp, ucode_prefix); 71 if (err) 72 return err; 73 err = psp_init_ta_microcode(psp, ucode_prefix); 74 if (err) 75 return err; 76 break; 77 case IP_VERSION(14, 0, 5): 78 err = psp_init_toc_microcode(psp, ucode_prefix); 79 if (err) 80 return err; 81 err = psp_init_ta_microcode(psp, ucode_prefix); 82 if (err) 83 return err; 84 break; 85 default: 86 BUG(); 87 } 88 89 return 0; 90 } 91 92 static bool psp_v14_0_is_sos_alive(struct psp_context *psp) 93 { 94 struct amdgpu_device *adev = psp->adev; 95 uint32_t sol_reg; 96 97 sol_reg = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_81); 98 99 return sol_reg != 0x0; 100 } 101 102 static int psp_v14_0_wait_for_bootloader(struct psp_context *psp) 103 { 104 struct amdgpu_device *adev = psp->adev; 105 106 int ret; 107 int retry_loop; 108 109 for (retry_loop = 0; retry_loop < 10; retry_loop++) { 110 /* Wait for bootloader to signify that is 111 ready having bit 31 of C2PMSG_35 set to 1 */ 112 ret = psp_wait_for( 113 psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_35), 114 0x80000000, 0x80000000, PSP_WAITREG_NOVERBOSE); 115 116 if (ret == 0) 117 return 0; 118 } 119 120 return ret; 121 } 122 123 static int psp_v14_0_bootloader_load_component(struct psp_context *psp, 124 struct psp_bin_desc *bin_desc, 125 enum psp_bootloader_cmd bl_cmd) 126 { 127 int ret; 128 uint32_t psp_gfxdrv_command_reg = 0; 129 struct amdgpu_device *adev = psp->adev; 130 131 /* Check tOS sign of life register to confirm sys driver and sOS 132 * are already been loaded. 133 */ 134 if (psp_v14_0_is_sos_alive(psp)) 135 return 0; 136 137 ret = psp_v14_0_wait_for_bootloader(psp); 138 if (ret) 139 return ret; 140 141 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 142 143 /* Copy PSP KDB binary to memory */ 144 memcpy(psp->fw_pri_buf, bin_desc->start_addr, bin_desc->size_bytes); 145 146 /* Provide the PSP KDB to bootloader */ 147 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_36, 148 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 149 psp_gfxdrv_command_reg = bl_cmd; 150 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_35, 151 psp_gfxdrv_command_reg); 152 153 ret = psp_v14_0_wait_for_bootloader(psp); 154 155 return ret; 156 } 157 158 static int psp_v14_0_bootloader_load_kdb(struct psp_context *psp) 159 { 160 return psp_v14_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_KEY_DATABASE); 161 } 162 163 static int psp_v14_0_bootloader_load_spl(struct psp_context *psp) 164 { 165 return psp_v14_0_bootloader_load_component(psp, &psp->spl, PSP_BL__LOAD_TOS_SPL_TABLE); 166 } 167 168 static int psp_v14_0_bootloader_load_sysdrv(struct psp_context *psp) 169 { 170 return psp_v14_0_bootloader_load_component(psp, &psp->sys, PSP_BL__LOAD_SYSDRV); 171 } 172 173 static int psp_v14_0_bootloader_load_soc_drv(struct psp_context *psp) 174 { 175 return psp_v14_0_bootloader_load_component(psp, &psp->soc_drv, PSP_BL__LOAD_SOCDRV); 176 } 177 178 static int psp_v14_0_bootloader_load_intf_drv(struct psp_context *psp) 179 { 180 return psp_v14_0_bootloader_load_component(psp, &psp->intf_drv, PSP_BL__LOAD_INTFDRV); 181 } 182 183 static int psp_v14_0_bootloader_load_dbg_drv(struct psp_context *psp) 184 { 185 /* dbg_drv was renamed to had_drv in psp v14 */ 186 return psp_v14_0_bootloader_load_component(psp, &psp->dbg_drv, PSP_BL__LOAD_HADDRV); 187 } 188 189 static int psp_v14_0_bootloader_load_ras_drv(struct psp_context *psp) 190 { 191 return psp_v14_0_bootloader_load_component(psp, &psp->ras_drv, PSP_BL__LOAD_RASDRV); 192 } 193 194 static int psp_v14_0_bootloader_load_ipkeymgr_drv(struct psp_context *psp) 195 { 196 return psp_v14_0_bootloader_load_component(psp, &psp->ipkeymgr_drv, PSP_BL__LOAD_IPKEYMGRDRV); 197 } 198 199 static int psp_v14_0_bootloader_load_sos(struct psp_context *psp) 200 { 201 int ret; 202 unsigned int psp_gfxdrv_command_reg = 0; 203 struct amdgpu_device *adev = psp->adev; 204 205 /* Check sOS sign of life register to confirm sys driver and sOS 206 * are already been loaded. 207 */ 208 if (psp_v14_0_is_sos_alive(psp)) 209 return 0; 210 211 ret = psp_v14_0_wait_for_bootloader(psp); 212 if (ret) 213 return ret; 214 215 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 216 217 /* Copy Secure OS binary to PSP memory */ 218 memcpy(psp->fw_pri_buf, psp->sos.start_addr, psp->sos.size_bytes); 219 220 /* Provide the PSP secure OS to bootloader */ 221 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_36, 222 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 223 psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV; 224 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_35, 225 psp_gfxdrv_command_reg); 226 227 /* there might be handshake issue with hardware which needs delay */ 228 mdelay(20); 229 ret = psp_wait_for(psp, 230 SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_81), 231 RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_81), 0, 232 PSP_WAITREG_CHANGED); 233 234 return ret; 235 } 236 237 static int psp_v14_0_ring_stop(struct psp_context *psp, 238 enum psp_ring_type ring_type) 239 { 240 int ret = 0; 241 struct amdgpu_device *adev = psp->adev; 242 243 if (amdgpu_sriov_vf(adev)) { 244 /* Write the ring destroy command*/ 245 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_101, 246 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING); 247 /* there might be handshake issue with hardware which needs delay */ 248 mdelay(20); 249 /* Wait for response flag (bit 31) */ 250 ret = psp_wait_for( 251 psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_101), 252 MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0); 253 } else { 254 /* Write the ring destroy command*/ 255 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_64, 256 GFX_CTRL_CMD_ID_DESTROY_RINGS); 257 /* there might be handshake issue with hardware which needs delay */ 258 mdelay(20); 259 /* Wait for response flag (bit 31) */ 260 ret = psp_wait_for( 261 psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_64), 262 MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0); 263 } 264 265 return ret; 266 } 267 268 static int psp_v14_0_ring_create(struct psp_context *psp, 269 enum psp_ring_type ring_type) 270 { 271 int ret = 0; 272 unsigned int psp_ring_reg = 0; 273 struct psp_ring *ring = &psp->km_ring; 274 struct amdgpu_device *adev = psp->adev; 275 276 if (amdgpu_sriov_vf(adev)) { 277 ret = psp_v14_0_ring_stop(psp, ring_type); 278 if (ret) { 279 DRM_ERROR("psp_v14_0_ring_stop_sriov failed!\n"); 280 return ret; 281 } 282 283 /* Write low address of the ring to C2PMSG_102 */ 284 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 285 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_102, psp_ring_reg); 286 /* Write high address of the ring to C2PMSG_103 */ 287 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 288 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_103, psp_ring_reg); 289 290 /* Write the ring initialization command to C2PMSG_101 */ 291 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_101, 292 GFX_CTRL_CMD_ID_INIT_GPCOM_RING); 293 294 /* there might be handshake issue with hardware which needs delay */ 295 mdelay(20); 296 297 /* Wait for response flag (bit 31) in C2PMSG_101 */ 298 ret = psp_wait_for( 299 psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_101), 300 MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0); 301 302 } else { 303 /* Wait for sOS ready for ring creation */ 304 ret = psp_wait_for( 305 psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_64), 306 MBOX_TOS_READY_FLAG, MBOX_TOS_READY_MASK, 0); 307 if (ret) { 308 DRM_ERROR("Failed to wait for trust OS ready for ring creation\n"); 309 return ret; 310 } 311 312 /* Write low address of the ring to C2PMSG_69 */ 313 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 314 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_69, psp_ring_reg); 315 /* Write high address of the ring to C2PMSG_70 */ 316 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 317 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_70, psp_ring_reg); 318 /* Write size of ring to C2PMSG_71 */ 319 psp_ring_reg = ring->ring_size; 320 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_71, psp_ring_reg); 321 /* Write the ring initialization command to C2PMSG_64 */ 322 psp_ring_reg = ring_type; 323 psp_ring_reg = psp_ring_reg << 16; 324 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_64, psp_ring_reg); 325 326 /* there might be handshake issue with hardware which needs delay */ 327 mdelay(20); 328 329 /* Wait for response flag (bit 31) in C2PMSG_64 */ 330 ret = psp_wait_for( 331 psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_64), 332 MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0); 333 } 334 335 return ret; 336 } 337 338 static int psp_v14_0_ring_destroy(struct psp_context *psp, 339 enum psp_ring_type ring_type) 340 { 341 int ret = 0; 342 struct psp_ring *ring = &psp->km_ring; 343 struct amdgpu_device *adev = psp->adev; 344 345 ret = psp_v14_0_ring_stop(psp, ring_type); 346 if (ret) 347 DRM_ERROR("Fail to stop psp ring\n"); 348 349 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 350 &ring->ring_mem_mc_addr, 351 (void **)&ring->ring_mem); 352 353 return ret; 354 } 355 356 static uint32_t psp_v14_0_ring_get_wptr(struct psp_context *psp) 357 { 358 uint32_t data; 359 struct amdgpu_device *adev = psp->adev; 360 361 if (amdgpu_sriov_vf(adev)) 362 data = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_102); 363 else 364 data = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_67); 365 366 return data; 367 } 368 369 static void psp_v14_0_ring_set_wptr(struct psp_context *psp, uint32_t value) 370 { 371 struct amdgpu_device *adev = psp->adev; 372 373 if (amdgpu_sriov_vf(adev)) { 374 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_102, value); 375 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_101, 376 GFX_CTRL_CMD_ID_CONSUME_CMD); 377 } else 378 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_67, value); 379 } 380 381 static int psp_v14_0_memory_training_send_msg(struct psp_context *psp, int msg) 382 { 383 int ret; 384 int i; 385 uint32_t data_32; 386 int max_wait; 387 struct amdgpu_device *adev = psp->adev; 388 389 data_32 = (psp->mem_train_ctx.c2p_train_data_offset >> 20); 390 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_36, data_32); 391 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_35, msg); 392 393 max_wait = MEM_TRAIN_SEND_MSG_TIMEOUT_US / adev->usec_timeout; 394 for (i = 0; i < max_wait; i++) { 395 ret = psp_wait_for( 396 psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_35), 397 0x80000000, 0x80000000, PSP_WAITREG_NOVERBOSE); 398 if (ret == 0) 399 break; 400 } 401 if (i < max_wait) 402 ret = 0; 403 else 404 ret = -ETIME; 405 406 dev_dbg(adev->dev, "training %s %s, cost %d @ %d ms\n", 407 (msg == PSP_BL__DRAM_SHORT_TRAIN) ? "short" : "long", 408 (ret == 0) ? "succeed" : "failed", 409 i, adev->usec_timeout/1000); 410 return ret; 411 } 412 413 414 static int psp_v14_0_memory_training(struct psp_context *psp, uint32_t ops) 415 { 416 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 417 uint32_t *pcache = (uint32_t *)ctx->sys_cache; 418 struct amdgpu_device *adev = psp->adev; 419 uint32_t p2c_header[4]; 420 uint32_t sz; 421 void *buf; 422 int ret, idx; 423 424 if (ctx->init == PSP_MEM_TRAIN_NOT_SUPPORT) { 425 dev_dbg(adev->dev, "Memory training is not supported.\n"); 426 return 0; 427 } else if (ctx->init != PSP_MEM_TRAIN_INIT_SUCCESS) { 428 dev_err(adev->dev, "Memory training initialization failure.\n"); 429 return -EINVAL; 430 } 431 432 if (psp_v14_0_is_sos_alive(psp)) { 433 dev_dbg(adev->dev, "SOS is alive, skip memory training.\n"); 434 return 0; 435 } 436 437 amdgpu_device_vram_access(adev, ctx->p2c_train_data_offset, p2c_header, sizeof(p2c_header), false); 438 dev_dbg(adev->dev, "sys_cache[%08x,%08x,%08x,%08x] p2c_header[%08x,%08x,%08x,%08x]\n", 439 pcache[0], pcache[1], pcache[2], pcache[3], 440 p2c_header[0], p2c_header[1], p2c_header[2], p2c_header[3]); 441 442 if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) { 443 dev_dbg(adev->dev, "Short training depends on restore.\n"); 444 ops |= PSP_MEM_TRAIN_RESTORE; 445 } 446 447 if ((ops & PSP_MEM_TRAIN_RESTORE) && 448 pcache[0] != MEM_TRAIN_SYSTEM_SIGNATURE) { 449 dev_dbg(adev->dev, "sys_cache[0] is invalid, restore depends on save.\n"); 450 ops |= PSP_MEM_TRAIN_SAVE; 451 } 452 453 if (p2c_header[0] == MEM_TRAIN_SYSTEM_SIGNATURE && 454 !(pcache[0] == MEM_TRAIN_SYSTEM_SIGNATURE && 455 pcache[3] == p2c_header[3])) { 456 dev_dbg(adev->dev, "sys_cache is invalid or out-of-date, need save training data to sys_cache.\n"); 457 ops |= PSP_MEM_TRAIN_SAVE; 458 } 459 460 if ((ops & PSP_MEM_TRAIN_SAVE) && 461 p2c_header[0] != MEM_TRAIN_SYSTEM_SIGNATURE) { 462 dev_dbg(adev->dev, "p2c_header[0] is invalid, save depends on long training.\n"); 463 ops |= PSP_MEM_TRAIN_SEND_LONG_MSG; 464 } 465 466 if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) { 467 ops &= ~PSP_MEM_TRAIN_SEND_SHORT_MSG; 468 ops |= PSP_MEM_TRAIN_SAVE; 469 } 470 471 dev_dbg(adev->dev, "Memory training ops:%x.\n", ops); 472 473 if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) { 474 /* 475 * Long training will encroach a certain amount on the bottom of VRAM; 476 * save the content from the bottom of VRAM to system memory 477 * before training, and restore it after training to avoid 478 * VRAM corruption. 479 */ 480 sz = BIST_MEM_TRAINING_ENCROACHED_SIZE; 481 482 if (adev->gmc.visible_vram_size < sz || !adev->mman.aper_base_kaddr) { 483 dev_err(adev->dev, "visible_vram_size %llx or aper_base_kaddr %p is not initialized.\n", 484 adev->gmc.visible_vram_size, 485 adev->mman.aper_base_kaddr); 486 return -EINVAL; 487 } 488 489 buf = vmalloc(sz); 490 if (!buf) { 491 dev_err(adev->dev, "failed to allocate system memory.\n"); 492 return -ENOMEM; 493 } 494 495 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 496 memcpy_fromio(buf, adev->mman.aper_base_kaddr, sz); 497 ret = psp_v14_0_memory_training_send_msg(psp, PSP_BL__DRAM_LONG_TRAIN); 498 if (ret) { 499 DRM_ERROR("Send long training msg failed.\n"); 500 vfree(buf); 501 drm_dev_exit(idx); 502 return ret; 503 } 504 505 memcpy_toio(adev->mman.aper_base_kaddr, buf, sz); 506 amdgpu_device_flush_hdp(adev, NULL); 507 vfree(buf); 508 drm_dev_exit(idx); 509 } else { 510 vfree(buf); 511 return -ENODEV; 512 } 513 } 514 515 if (ops & PSP_MEM_TRAIN_SAVE) { 516 amdgpu_device_vram_access(psp->adev, ctx->p2c_train_data_offset, ctx->sys_cache, ctx->train_data_size, false); 517 } 518 519 if (ops & PSP_MEM_TRAIN_RESTORE) { 520 amdgpu_device_vram_access(psp->adev, ctx->c2p_train_data_offset, ctx->sys_cache, ctx->train_data_size, true); 521 } 522 523 if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) { 524 ret = psp_v14_0_memory_training_send_msg(psp, (amdgpu_force_long_training > 0) ? 525 PSP_BL__DRAM_LONG_TRAIN : PSP_BL__DRAM_SHORT_TRAIN); 526 if (ret) { 527 dev_err(adev->dev, "send training msg failed.\n"); 528 return ret; 529 } 530 } 531 ctx->training_cnt++; 532 return 0; 533 } 534 535 static int psp_v14_0_load_usbc_pd_fw(struct psp_context *psp, uint64_t fw_pri_mc_addr) 536 { 537 struct amdgpu_device *adev = psp->adev; 538 uint32_t reg_status; 539 int ret, i = 0; 540 541 /* 542 * LFB address which is aligned to 1MB address and has to be 543 * right-shifted by 20 so that LFB address can be passed on a 32-bit C2P 544 * register 545 */ 546 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_36, (fw_pri_mc_addr >> 20)); 547 548 ret = psp_wait_for(psp, 549 SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_35), 550 0x80000000, 0x80000000, 0); 551 if (ret) 552 return ret; 553 554 /* Fireup interrupt so PSP can pick up the address */ 555 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_35, (GFX_CMD_USB_PD_USE_LFB << 16)); 556 557 /* FW load takes very long time */ 558 do { 559 msleep(1000); 560 reg_status = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_35); 561 562 if (reg_status & 0x80000000) 563 goto done; 564 565 } while (++i < USBC_PD_POLLING_LIMIT_S); 566 567 return -ETIME; 568 done: 569 570 if ((reg_status & 0xFFFF) != 0) { 571 DRM_ERROR("Address load failed - MP0_SMN_C2PMSG_35.Bits [15:0] = %04x\n", 572 reg_status & 0xFFFF); 573 return -EIO; 574 } 575 576 return 0; 577 } 578 579 static int psp_v14_0_read_usbc_pd_fw(struct psp_context *psp, uint32_t *fw_ver) 580 { 581 struct amdgpu_device *adev = psp->adev; 582 int ret; 583 584 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_35, C2PMSG_CMD_GFX_USB_PD_FW_VER); 585 586 ret = psp_wait_for(psp, 587 SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_35), 588 0x80000000, 0x80000000, 0); 589 if (!ret) 590 *fw_ver = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_36); 591 592 return ret; 593 } 594 595 static int psp_v14_0_exec_spi_cmd(struct psp_context *psp, int cmd) 596 { 597 uint32_t reg_status = 0, reg_val = 0; 598 struct amdgpu_device *adev = psp->adev; 599 int ret; 600 601 /* clear MBX ready (MBOX_READY_MASK bit is 0) and set update command */ 602 reg_val |= (cmd << 16); 603 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_115, reg_val); 604 605 /* Ring the doorbell */ 606 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_73, 1); 607 608 if (cmd == C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE) 609 ret = psp_wait_for_spirom_update(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_115), 610 MBOX_READY_FLAG, MBOX_READY_MASK, PSP_SPIROM_UPDATE_TIMEOUT); 611 else 612 ret = psp_wait_for( 613 psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_115), 614 MBOX_READY_FLAG, MBOX_READY_MASK, 0); 615 616 ret = psp_wait_for(psp, 617 SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_115), 618 MBOX_READY_FLAG, MBOX_READY_MASK, 0); 619 if (ret) { 620 dev_err(adev->dev, "SPI cmd %x timed out, ret = %d", cmd, ret); 621 return ret; 622 } 623 624 reg_status = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_115); 625 if ((reg_status & 0xFFFF) != 0) { 626 dev_err(adev->dev, "SPI cmd %x failed, fail status = %04x\n", 627 cmd, reg_status & 0xFFFF); 628 return -EIO; 629 } 630 631 return 0; 632 } 633 634 static int psp_v14_0_update_spirom(struct psp_context *psp, 635 uint64_t fw_pri_mc_addr) 636 { 637 struct amdgpu_device *adev = psp->adev; 638 int ret; 639 640 /* Confirm PSP is ready to start */ 641 ret = psp_wait_for(psp, 642 SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_115), 643 MBOX_READY_FLAG, MBOX_READY_MASK, 0); 644 if (ret) { 645 dev_err(adev->dev, "PSP Not ready to start processing, ret = %d", ret); 646 return ret; 647 } 648 649 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_116, lower_32_bits(fw_pri_mc_addr)); 650 651 ret = psp_v14_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_LO); 652 if (ret) 653 return ret; 654 655 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_116, upper_32_bits(fw_pri_mc_addr)); 656 657 ret = psp_v14_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI); 658 if (ret) 659 return ret; 660 661 psp->vbflash_done = true; 662 663 ret = psp_v14_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE); 664 if (ret) 665 return ret; 666 667 return 0; 668 } 669 670 static int psp_v14_0_vbflash_status(struct psp_context *psp) 671 { 672 struct amdgpu_device *adev = psp->adev; 673 674 return RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_115); 675 } 676 677 static const struct psp_funcs psp_v14_0_funcs = { 678 .init_microcode = psp_v14_0_init_microcode, 679 .bootloader_load_kdb = psp_v14_0_bootloader_load_kdb, 680 .bootloader_load_spl = psp_v14_0_bootloader_load_spl, 681 .bootloader_load_sysdrv = psp_v14_0_bootloader_load_sysdrv, 682 .bootloader_load_soc_drv = psp_v14_0_bootloader_load_soc_drv, 683 .bootloader_load_intf_drv = psp_v14_0_bootloader_load_intf_drv, 684 .bootloader_load_dbg_drv = psp_v14_0_bootloader_load_dbg_drv, 685 .bootloader_load_ras_drv = psp_v14_0_bootloader_load_ras_drv, 686 .bootloader_load_ipkeymgr_drv = psp_v14_0_bootloader_load_ipkeymgr_drv, 687 .bootloader_load_sos = psp_v14_0_bootloader_load_sos, 688 .ring_create = psp_v14_0_ring_create, 689 .ring_stop = psp_v14_0_ring_stop, 690 .ring_destroy = psp_v14_0_ring_destroy, 691 .ring_get_wptr = psp_v14_0_ring_get_wptr, 692 .ring_set_wptr = psp_v14_0_ring_set_wptr, 693 .mem_training = psp_v14_0_memory_training, 694 .load_usbc_pd_fw = psp_v14_0_load_usbc_pd_fw, 695 .read_usbc_pd_fw = psp_v14_0_read_usbc_pd_fw, 696 .update_spirom = psp_v14_0_update_spirom, 697 .vbflash_stat = psp_v14_0_vbflash_status 698 }; 699 700 void psp_v14_0_set_psp_funcs(struct psp_context *psp) 701 { 702 psp->funcs = &psp_v14_0_funcs; 703 } 704