1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <drm/drm_drv.h> 24 #include <linux/vmalloc.h> 25 #include "amdgpu.h" 26 #include "amdgpu_psp.h" 27 #include "amdgpu_ucode.h" 28 #include "soc15_common.h" 29 #include "psp_v14_0.h" 30 31 #include "mp/mp_14_0_2_offset.h" 32 #include "mp/mp_14_0_2_sh_mask.h" 33 34 MODULE_FIRMWARE("amdgpu/psp_14_0_2_sos.bin"); 35 MODULE_FIRMWARE("amdgpu/psp_14_0_2_ta.bin"); 36 MODULE_FIRMWARE("amdgpu/psp_14_0_3_sos.bin"); 37 MODULE_FIRMWARE("amdgpu/psp_14_0_3_ta.bin"); 38 MODULE_FIRMWARE("amdgpu/psp_14_0_5_toc.bin"); 39 MODULE_FIRMWARE("amdgpu/psp_14_0_5_ta.bin"); 40 41 /* For large FW files the time to complete can be very long */ 42 #define USBC_PD_POLLING_LIMIT_S 240 43 44 /* Read USB-PD from LFB */ 45 #define GFX_CMD_USB_PD_USE_LFB 0x480 46 47 /* VBIOS gfl defines */ 48 #define MBOX_READY_MASK 0x80000000 49 #define MBOX_STATUS_MASK 0x0000FFFF 50 #define MBOX_COMMAND_MASK 0x00FF0000 51 #define MBOX_READY_FLAG 0x80000000 52 #define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_LO 0x2 53 #define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI 0x3 54 #define C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE 0x4 55 56 /* memory training timeout define */ 57 #define MEM_TRAIN_SEND_MSG_TIMEOUT_US 3000000 58 59 static int psp_v14_0_init_microcode(struct psp_context *psp) 60 { 61 struct amdgpu_device *adev = psp->adev; 62 char ucode_prefix[30]; 63 int err = 0; 64 65 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); 66 67 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 68 case IP_VERSION(14, 0, 2): 69 case IP_VERSION(14, 0, 3): 70 err = psp_init_sos_microcode(psp, ucode_prefix); 71 if (err) 72 return err; 73 err = psp_init_ta_microcode(psp, ucode_prefix); 74 if (err) 75 return err; 76 break; 77 case IP_VERSION(14, 0, 5): 78 err = psp_init_toc_microcode(psp, ucode_prefix); 79 if (err) 80 return err; 81 err = psp_init_ta_microcode(psp, ucode_prefix); 82 if (err) 83 return err; 84 break; 85 default: 86 BUG(); 87 } 88 89 return 0; 90 } 91 92 static bool psp_v14_0_is_sos_alive(struct psp_context *psp) 93 { 94 struct amdgpu_device *adev = psp->adev; 95 uint32_t sol_reg; 96 97 sol_reg = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_81); 98 99 return sol_reg != 0x0; 100 } 101 102 static int psp_v14_0_wait_for_bootloader(struct psp_context *psp) 103 { 104 struct amdgpu_device *adev = psp->adev; 105 106 int ret; 107 int retry_loop; 108 109 for (retry_loop = 0; retry_loop < 10; retry_loop++) { 110 /* Wait for bootloader to signify that is 111 ready having bit 31 of C2PMSG_35 set to 1 */ 112 ret = psp_wait_for(psp, 113 SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_35), 114 0x80000000, 115 0x80000000, 116 false); 117 118 if (ret == 0) 119 return 0; 120 } 121 122 return ret; 123 } 124 125 static int psp_v14_0_bootloader_load_component(struct psp_context *psp, 126 struct psp_bin_desc *bin_desc, 127 enum psp_bootloader_cmd bl_cmd) 128 { 129 int ret; 130 uint32_t psp_gfxdrv_command_reg = 0; 131 struct amdgpu_device *adev = psp->adev; 132 133 /* Check tOS sign of life register to confirm sys driver and sOS 134 * are already been loaded. 135 */ 136 if (psp_v14_0_is_sos_alive(psp)) 137 return 0; 138 139 ret = psp_v14_0_wait_for_bootloader(psp); 140 if (ret) 141 return ret; 142 143 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 144 145 /* Copy PSP KDB binary to memory */ 146 memcpy(psp->fw_pri_buf, bin_desc->start_addr, bin_desc->size_bytes); 147 148 /* Provide the PSP KDB to bootloader */ 149 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_36, 150 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 151 psp_gfxdrv_command_reg = bl_cmd; 152 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_35, 153 psp_gfxdrv_command_reg); 154 155 ret = psp_v14_0_wait_for_bootloader(psp); 156 157 return ret; 158 } 159 160 static int psp_v14_0_bootloader_load_kdb(struct psp_context *psp) 161 { 162 return psp_v14_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_KEY_DATABASE); 163 } 164 165 static int psp_v14_0_bootloader_load_spl(struct psp_context *psp) 166 { 167 return psp_v14_0_bootloader_load_component(psp, &psp->spl, PSP_BL__LOAD_TOS_SPL_TABLE); 168 } 169 170 static int psp_v14_0_bootloader_load_sysdrv(struct psp_context *psp) 171 { 172 return psp_v14_0_bootloader_load_component(psp, &psp->sys, PSP_BL__LOAD_SYSDRV); 173 } 174 175 static int psp_v14_0_bootloader_load_soc_drv(struct psp_context *psp) 176 { 177 return psp_v14_0_bootloader_load_component(psp, &psp->soc_drv, PSP_BL__LOAD_SOCDRV); 178 } 179 180 static int psp_v14_0_bootloader_load_intf_drv(struct psp_context *psp) 181 { 182 return psp_v14_0_bootloader_load_component(psp, &psp->intf_drv, PSP_BL__LOAD_INTFDRV); 183 } 184 185 static int psp_v14_0_bootloader_load_dbg_drv(struct psp_context *psp) 186 { 187 /* dbg_drv was renamed to had_drv in psp v14 */ 188 return psp_v14_0_bootloader_load_component(psp, &psp->dbg_drv, PSP_BL__LOAD_HADDRV); 189 } 190 191 static int psp_v14_0_bootloader_load_ras_drv(struct psp_context *psp) 192 { 193 return psp_v14_0_bootloader_load_component(psp, &psp->ras_drv, PSP_BL__LOAD_RASDRV); 194 } 195 196 static int psp_v14_0_bootloader_load_ipkeymgr_drv(struct psp_context *psp) 197 { 198 return psp_v14_0_bootloader_load_component(psp, &psp->ipkeymgr_drv, PSP_BL__LOAD_IPKEYMGRDRV); 199 } 200 201 static int psp_v14_0_bootloader_load_sos(struct psp_context *psp) 202 { 203 int ret; 204 unsigned int psp_gfxdrv_command_reg = 0; 205 struct amdgpu_device *adev = psp->adev; 206 207 /* Check sOS sign of life register to confirm sys driver and sOS 208 * are already been loaded. 209 */ 210 if (psp_v14_0_is_sos_alive(psp)) 211 return 0; 212 213 ret = psp_v14_0_wait_for_bootloader(psp); 214 if (ret) 215 return ret; 216 217 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 218 219 /* Copy Secure OS binary to PSP memory */ 220 memcpy(psp->fw_pri_buf, psp->sos.start_addr, psp->sos.size_bytes); 221 222 /* Provide the PSP secure OS to bootloader */ 223 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_36, 224 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 225 psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV; 226 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_35, 227 psp_gfxdrv_command_reg); 228 229 /* there might be handshake issue with hardware which needs delay */ 230 mdelay(20); 231 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_81), 232 RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_81), 233 0, true); 234 235 return ret; 236 } 237 238 static int psp_v14_0_ring_stop(struct psp_context *psp, 239 enum psp_ring_type ring_type) 240 { 241 int ret = 0; 242 struct amdgpu_device *adev = psp->adev; 243 244 if (amdgpu_sriov_vf(adev)) { 245 /* Write the ring destroy command*/ 246 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_101, 247 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING); 248 /* there might be handshake issue with hardware which needs delay */ 249 mdelay(20); 250 /* Wait for response flag (bit 31) */ 251 ret = psp_wait_for( 252 psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_101), 253 MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false); 254 } else { 255 /* Write the ring destroy command*/ 256 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_64, 257 GFX_CTRL_CMD_ID_DESTROY_RINGS); 258 /* there might be handshake issue with hardware which needs delay */ 259 mdelay(20); 260 /* Wait for response flag (bit 31) */ 261 ret = psp_wait_for( 262 psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_64), 263 MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false); 264 } 265 266 return ret; 267 } 268 269 static int psp_v14_0_ring_create(struct psp_context *psp, 270 enum psp_ring_type ring_type) 271 { 272 int ret = 0; 273 unsigned int psp_ring_reg = 0; 274 struct psp_ring *ring = &psp->km_ring; 275 struct amdgpu_device *adev = psp->adev; 276 277 if (amdgpu_sriov_vf(adev)) { 278 ret = psp_v14_0_ring_stop(psp, ring_type); 279 if (ret) { 280 DRM_ERROR("psp_v14_0_ring_stop_sriov failed!\n"); 281 return ret; 282 } 283 284 /* Write low address of the ring to C2PMSG_102 */ 285 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 286 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_102, psp_ring_reg); 287 /* Write high address of the ring to C2PMSG_103 */ 288 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 289 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_103, psp_ring_reg); 290 291 /* Write the ring initialization command to C2PMSG_101 */ 292 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_101, 293 GFX_CTRL_CMD_ID_INIT_GPCOM_RING); 294 295 /* there might be handshake issue with hardware which needs delay */ 296 mdelay(20); 297 298 /* Wait for response flag (bit 31) in C2PMSG_101 */ 299 ret = psp_wait_for( 300 psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_101), 301 MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false); 302 303 } else { 304 /* Wait for sOS ready for ring creation */ 305 ret = psp_wait_for( 306 psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_64), 307 MBOX_TOS_READY_FLAG, MBOX_TOS_READY_MASK, false); 308 if (ret) { 309 DRM_ERROR("Failed to wait for trust OS ready for ring creation\n"); 310 return ret; 311 } 312 313 /* Write low address of the ring to C2PMSG_69 */ 314 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 315 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_69, psp_ring_reg); 316 /* Write high address of the ring to C2PMSG_70 */ 317 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 318 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_70, psp_ring_reg); 319 /* Write size of ring to C2PMSG_71 */ 320 psp_ring_reg = ring->ring_size; 321 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_71, psp_ring_reg); 322 /* Write the ring initialization command to C2PMSG_64 */ 323 psp_ring_reg = ring_type; 324 psp_ring_reg = psp_ring_reg << 16; 325 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_64, psp_ring_reg); 326 327 /* there might be handshake issue with hardware which needs delay */ 328 mdelay(20); 329 330 /* Wait for response flag (bit 31) in C2PMSG_64 */ 331 ret = psp_wait_for( 332 psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_64), 333 MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false); 334 } 335 336 return ret; 337 } 338 339 static int psp_v14_0_ring_destroy(struct psp_context *psp, 340 enum psp_ring_type ring_type) 341 { 342 int ret = 0; 343 struct psp_ring *ring = &psp->km_ring; 344 struct amdgpu_device *adev = psp->adev; 345 346 ret = psp_v14_0_ring_stop(psp, ring_type); 347 if (ret) 348 DRM_ERROR("Fail to stop psp ring\n"); 349 350 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 351 &ring->ring_mem_mc_addr, 352 (void **)&ring->ring_mem); 353 354 return ret; 355 } 356 357 static uint32_t psp_v14_0_ring_get_wptr(struct psp_context *psp) 358 { 359 uint32_t data; 360 struct amdgpu_device *adev = psp->adev; 361 362 if (amdgpu_sriov_vf(adev)) 363 data = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_102); 364 else 365 data = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_67); 366 367 return data; 368 } 369 370 static void psp_v14_0_ring_set_wptr(struct psp_context *psp, uint32_t value) 371 { 372 struct amdgpu_device *adev = psp->adev; 373 374 if (amdgpu_sriov_vf(adev)) { 375 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_102, value); 376 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_101, 377 GFX_CTRL_CMD_ID_CONSUME_CMD); 378 } else 379 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_67, value); 380 } 381 382 static int psp_v14_0_memory_training_send_msg(struct psp_context *psp, int msg) 383 { 384 int ret; 385 int i; 386 uint32_t data_32; 387 int max_wait; 388 struct amdgpu_device *adev = psp->adev; 389 390 data_32 = (psp->mem_train_ctx.c2p_train_data_offset >> 20); 391 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_36, data_32); 392 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_35, msg); 393 394 max_wait = MEM_TRAIN_SEND_MSG_TIMEOUT_US / adev->usec_timeout; 395 for (i = 0; i < max_wait; i++) { 396 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_35), 397 0x80000000, 0x80000000, false); 398 if (ret == 0) 399 break; 400 } 401 if (i < max_wait) 402 ret = 0; 403 else 404 ret = -ETIME; 405 406 dev_dbg(adev->dev, "training %s %s, cost %d @ %d ms\n", 407 (msg == PSP_BL__DRAM_SHORT_TRAIN) ? "short" : "long", 408 (ret == 0) ? "succeed" : "failed", 409 i, adev->usec_timeout/1000); 410 return ret; 411 } 412 413 414 static int psp_v14_0_memory_training(struct psp_context *psp, uint32_t ops) 415 { 416 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 417 uint32_t *pcache = (uint32_t *)ctx->sys_cache; 418 struct amdgpu_device *adev = psp->adev; 419 uint32_t p2c_header[4]; 420 uint32_t sz; 421 void *buf; 422 int ret, idx; 423 424 if (ctx->init == PSP_MEM_TRAIN_NOT_SUPPORT) { 425 dev_dbg(adev->dev, "Memory training is not supported.\n"); 426 return 0; 427 } else if (ctx->init != PSP_MEM_TRAIN_INIT_SUCCESS) { 428 dev_err(adev->dev, "Memory training initialization failure.\n"); 429 return -EINVAL; 430 } 431 432 if (psp_v14_0_is_sos_alive(psp)) { 433 dev_dbg(adev->dev, "SOS is alive, skip memory training.\n"); 434 return 0; 435 } 436 437 amdgpu_device_vram_access(adev, ctx->p2c_train_data_offset, p2c_header, sizeof(p2c_header), false); 438 dev_dbg(adev->dev, "sys_cache[%08x,%08x,%08x,%08x] p2c_header[%08x,%08x,%08x,%08x]\n", 439 pcache[0], pcache[1], pcache[2], pcache[3], 440 p2c_header[0], p2c_header[1], p2c_header[2], p2c_header[3]); 441 442 if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) { 443 dev_dbg(adev->dev, "Short training depends on restore.\n"); 444 ops |= PSP_MEM_TRAIN_RESTORE; 445 } 446 447 if ((ops & PSP_MEM_TRAIN_RESTORE) && 448 pcache[0] != MEM_TRAIN_SYSTEM_SIGNATURE) { 449 dev_dbg(adev->dev, "sys_cache[0] is invalid, restore depends on save.\n"); 450 ops |= PSP_MEM_TRAIN_SAVE; 451 } 452 453 if (p2c_header[0] == MEM_TRAIN_SYSTEM_SIGNATURE && 454 !(pcache[0] == MEM_TRAIN_SYSTEM_SIGNATURE && 455 pcache[3] == p2c_header[3])) { 456 dev_dbg(adev->dev, "sys_cache is invalid or out-of-date, need save training data to sys_cache.\n"); 457 ops |= PSP_MEM_TRAIN_SAVE; 458 } 459 460 if ((ops & PSP_MEM_TRAIN_SAVE) && 461 p2c_header[0] != MEM_TRAIN_SYSTEM_SIGNATURE) { 462 dev_dbg(adev->dev, "p2c_header[0] is invalid, save depends on long training.\n"); 463 ops |= PSP_MEM_TRAIN_SEND_LONG_MSG; 464 } 465 466 if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) { 467 ops &= ~PSP_MEM_TRAIN_SEND_SHORT_MSG; 468 ops |= PSP_MEM_TRAIN_SAVE; 469 } 470 471 dev_dbg(adev->dev, "Memory training ops:%x.\n", ops); 472 473 if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) { 474 /* 475 * Long training will encroach a certain amount on the bottom of VRAM; 476 * save the content from the bottom of VRAM to system memory 477 * before training, and restore it after training to avoid 478 * VRAM corruption. 479 */ 480 sz = BIST_MEM_TRAINING_ENCROACHED_SIZE; 481 482 if (adev->gmc.visible_vram_size < sz || !adev->mman.aper_base_kaddr) { 483 dev_err(adev->dev, "visible_vram_size %llx or aper_base_kaddr %p is not initialized.\n", 484 adev->gmc.visible_vram_size, 485 adev->mman.aper_base_kaddr); 486 return -EINVAL; 487 } 488 489 buf = vmalloc(sz); 490 if (!buf) { 491 dev_err(adev->dev, "failed to allocate system memory.\n"); 492 return -ENOMEM; 493 } 494 495 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 496 memcpy_fromio(buf, adev->mman.aper_base_kaddr, sz); 497 ret = psp_v14_0_memory_training_send_msg(psp, PSP_BL__DRAM_LONG_TRAIN); 498 if (ret) { 499 DRM_ERROR("Send long training msg failed.\n"); 500 vfree(buf); 501 drm_dev_exit(idx); 502 return ret; 503 } 504 505 memcpy_toio(adev->mman.aper_base_kaddr, buf, sz); 506 amdgpu_device_flush_hdp(adev, NULL); 507 vfree(buf); 508 drm_dev_exit(idx); 509 } else { 510 vfree(buf); 511 return -ENODEV; 512 } 513 } 514 515 if (ops & PSP_MEM_TRAIN_SAVE) { 516 amdgpu_device_vram_access(psp->adev, ctx->p2c_train_data_offset, ctx->sys_cache, ctx->train_data_size, false); 517 } 518 519 if (ops & PSP_MEM_TRAIN_RESTORE) { 520 amdgpu_device_vram_access(psp->adev, ctx->c2p_train_data_offset, ctx->sys_cache, ctx->train_data_size, true); 521 } 522 523 if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) { 524 ret = psp_v14_0_memory_training_send_msg(psp, (amdgpu_force_long_training > 0) ? 525 PSP_BL__DRAM_LONG_TRAIN : PSP_BL__DRAM_SHORT_TRAIN); 526 if (ret) { 527 dev_err(adev->dev, "send training msg failed.\n"); 528 return ret; 529 } 530 } 531 ctx->training_cnt++; 532 return 0; 533 } 534 535 static int psp_v14_0_load_usbc_pd_fw(struct psp_context *psp, uint64_t fw_pri_mc_addr) 536 { 537 struct amdgpu_device *adev = psp->adev; 538 uint32_t reg_status; 539 int ret, i = 0; 540 541 /* 542 * LFB address which is aligned to 1MB address and has to be 543 * right-shifted by 20 so that LFB address can be passed on a 32-bit C2P 544 * register 545 */ 546 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_36, (fw_pri_mc_addr >> 20)); 547 548 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_35), 549 0x80000000, 0x80000000, false); 550 if (ret) 551 return ret; 552 553 /* Fireup interrupt so PSP can pick up the address */ 554 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_35, (GFX_CMD_USB_PD_USE_LFB << 16)); 555 556 /* FW load takes very long time */ 557 do { 558 msleep(1000); 559 reg_status = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_35); 560 561 if (reg_status & 0x80000000) 562 goto done; 563 564 } while (++i < USBC_PD_POLLING_LIMIT_S); 565 566 return -ETIME; 567 done: 568 569 if ((reg_status & 0xFFFF) != 0) { 570 DRM_ERROR("Address load failed - MP0_SMN_C2PMSG_35.Bits [15:0] = %04x\n", 571 reg_status & 0xFFFF); 572 return -EIO; 573 } 574 575 return 0; 576 } 577 578 static int psp_v14_0_read_usbc_pd_fw(struct psp_context *psp, uint32_t *fw_ver) 579 { 580 struct amdgpu_device *adev = psp->adev; 581 int ret; 582 583 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_35, C2PMSG_CMD_GFX_USB_PD_FW_VER); 584 585 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_35), 586 0x80000000, 0x80000000, false); 587 if (!ret) 588 *fw_ver = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_36); 589 590 return ret; 591 } 592 593 static int psp_v14_0_exec_spi_cmd(struct psp_context *psp, int cmd) 594 { 595 uint32_t reg_status = 0, reg_val = 0; 596 struct amdgpu_device *adev = psp->adev; 597 int ret; 598 599 /* clear MBX ready (MBOX_READY_MASK bit is 0) and set update command */ 600 reg_val |= (cmd << 16); 601 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_115, reg_val); 602 603 /* Ring the doorbell */ 604 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_73, 1); 605 606 if (cmd == C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE) 607 ret = psp_wait_for_spirom_update(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_115), 608 MBOX_READY_FLAG, MBOX_READY_MASK, PSP_SPIROM_UPDATE_TIMEOUT); 609 else 610 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_115), 611 MBOX_READY_FLAG, MBOX_READY_MASK, false); 612 613 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_115), 614 MBOX_READY_FLAG, MBOX_READY_MASK, false); 615 if (ret) { 616 dev_err(adev->dev, "SPI cmd %x timed out, ret = %d", cmd, ret); 617 return ret; 618 } 619 620 reg_status = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_115); 621 if ((reg_status & 0xFFFF) != 0) { 622 dev_err(adev->dev, "SPI cmd %x failed, fail status = %04x\n", 623 cmd, reg_status & 0xFFFF); 624 return -EIO; 625 } 626 627 return 0; 628 } 629 630 static int psp_v14_0_update_spirom(struct psp_context *psp, 631 uint64_t fw_pri_mc_addr) 632 { 633 struct amdgpu_device *adev = psp->adev; 634 int ret; 635 636 /* Confirm PSP is ready to start */ 637 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_115), 638 MBOX_READY_FLAG, MBOX_READY_MASK, false); 639 if (ret) { 640 dev_err(adev->dev, "PSP Not ready to start processing, ret = %d", ret); 641 return ret; 642 } 643 644 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_116, lower_32_bits(fw_pri_mc_addr)); 645 646 ret = psp_v14_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_LO); 647 if (ret) 648 return ret; 649 650 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_116, upper_32_bits(fw_pri_mc_addr)); 651 652 ret = psp_v14_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI); 653 if (ret) 654 return ret; 655 656 psp->vbflash_done = true; 657 658 ret = psp_v14_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE); 659 if (ret) 660 return ret; 661 662 return 0; 663 } 664 665 static int psp_v14_0_vbflash_status(struct psp_context *psp) 666 { 667 struct amdgpu_device *adev = psp->adev; 668 669 return RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_115); 670 } 671 672 static const struct psp_funcs psp_v14_0_funcs = { 673 .init_microcode = psp_v14_0_init_microcode, 674 .bootloader_load_kdb = psp_v14_0_bootloader_load_kdb, 675 .bootloader_load_spl = psp_v14_0_bootloader_load_spl, 676 .bootloader_load_sysdrv = psp_v14_0_bootloader_load_sysdrv, 677 .bootloader_load_soc_drv = psp_v14_0_bootloader_load_soc_drv, 678 .bootloader_load_intf_drv = psp_v14_0_bootloader_load_intf_drv, 679 .bootloader_load_dbg_drv = psp_v14_0_bootloader_load_dbg_drv, 680 .bootloader_load_ras_drv = psp_v14_0_bootloader_load_ras_drv, 681 .bootloader_load_ipkeymgr_drv = psp_v14_0_bootloader_load_ipkeymgr_drv, 682 .bootloader_load_sos = psp_v14_0_bootloader_load_sos, 683 .ring_create = psp_v14_0_ring_create, 684 .ring_stop = psp_v14_0_ring_stop, 685 .ring_destroy = psp_v14_0_ring_destroy, 686 .ring_get_wptr = psp_v14_0_ring_get_wptr, 687 .ring_set_wptr = psp_v14_0_ring_set_wptr, 688 .mem_training = psp_v14_0_memory_training, 689 .load_usbc_pd_fw = psp_v14_0_load_usbc_pd_fw, 690 .read_usbc_pd_fw = psp_v14_0_read_usbc_pd_fw, 691 .update_spirom = psp_v14_0_update_spirom, 692 .vbflash_stat = psp_v14_0_vbflash_status 693 }; 694 695 void psp_v14_0_set_psp_funcs(struct psp_context *psp) 696 { 697 psp->funcs = &psp_v14_0_funcs; 698 } 699