1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "amdgpu.h" 24 #include "amdgpu_psp.h" 25 #include "amdgpu_ucode.h" 26 #include "soc15_common.h" 27 #include "psp_v13_0_4.h" 28 29 #include "mp/mp_13_0_4_offset.h" 30 #include "mp/mp_13_0_4_sh_mask.h" 31 32 MODULE_FIRMWARE("amdgpu/psp_13_0_4_toc.bin"); 33 MODULE_FIRMWARE("amdgpu/psp_13_0_4_ta.bin"); 34 35 static int psp_v13_0_4_init_microcode(struct psp_context *psp) 36 { 37 struct amdgpu_device *adev = psp->adev; 38 char ucode_prefix[30]; 39 int err = 0; 40 41 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); 42 43 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 44 case IP_VERSION(13, 0, 4): 45 err = psp_init_toc_microcode(psp, ucode_prefix); 46 if (err) 47 return err; 48 err = psp_init_ta_microcode(psp, ucode_prefix); 49 if (err) 50 return err; 51 break; 52 default: 53 BUG(); 54 } 55 56 return 0; 57 } 58 59 static bool psp_v13_0_4_is_sos_alive(struct psp_context *psp) 60 { 61 struct amdgpu_device *adev = psp->adev; 62 uint32_t sol_reg; 63 64 sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81); 65 66 return sol_reg != 0x0; 67 } 68 69 static int psp_v13_0_4_wait_for_bootloader(struct psp_context *psp) 70 { 71 struct amdgpu_device *adev = psp->adev; 72 73 int ret; 74 int retry_loop; 75 76 for (retry_loop = 0; retry_loop < 10; retry_loop++) { 77 /* Wait for bootloader to signify that is 78 ready having bit 31 of C2PMSG_35 set to 1 */ 79 ret = psp_wait_for( 80 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 81 0x80000000, 0x80000000, PSP_WAITREG_NOVERBOSE); 82 83 if (ret == 0) 84 return 0; 85 } 86 87 return ret; 88 } 89 90 static int psp_v13_0_4_bootloader_load_component(struct psp_context *psp, 91 struct psp_bin_desc *bin_desc, 92 enum psp_bootloader_cmd bl_cmd) 93 { 94 int ret; 95 uint32_t psp_gfxdrv_command_reg = 0; 96 struct amdgpu_device *adev = psp->adev; 97 98 /* Check tOS sign of life register to confirm sys driver and sOS 99 * are already been loaded. 100 */ 101 if (psp_v13_0_4_is_sos_alive(psp)) 102 return 0; 103 104 ret = psp_v13_0_4_wait_for_bootloader(psp); 105 if (ret) 106 return ret; 107 108 ret = psp_copy_fw(psp, bin_desc->start_addr, bin_desc->size_bytes); 109 if (ret) 110 return ret; 111 112 /* Provide the PSP KDB to bootloader */ 113 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, 114 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 115 psp_gfxdrv_command_reg = bl_cmd; 116 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, 117 psp_gfxdrv_command_reg); 118 119 ret = psp_v13_0_4_wait_for_bootloader(psp); 120 121 return ret; 122 } 123 124 static int psp_v13_0_4_bootloader_load_kdb(struct psp_context *psp) 125 { 126 return psp_v13_0_4_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_KEY_DATABASE); 127 } 128 129 static int psp_v13_0_4_bootloader_load_spl(struct psp_context *psp) 130 { 131 return psp_v13_0_4_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_TOS_SPL_TABLE); 132 } 133 134 static int psp_v13_0_4_bootloader_load_sysdrv(struct psp_context *psp) 135 { 136 return psp_v13_0_4_bootloader_load_component(psp, &psp->sys, PSP_BL__LOAD_SYSDRV); 137 } 138 139 static int psp_v13_0_4_bootloader_load_soc_drv(struct psp_context *psp) 140 { 141 return psp_v13_0_4_bootloader_load_component(psp, &psp->soc_drv, PSP_BL__LOAD_SOCDRV); 142 } 143 144 static int psp_v13_0_4_bootloader_load_intf_drv(struct psp_context *psp) 145 { 146 return psp_v13_0_4_bootloader_load_component(psp, &psp->intf_drv, PSP_BL__LOAD_INTFDRV); 147 } 148 149 static int psp_v13_0_4_bootloader_load_dbg_drv(struct psp_context *psp) 150 { 151 return psp_v13_0_4_bootloader_load_component(psp, &psp->dbg_drv, PSP_BL__LOAD_DBGDRV); 152 } 153 154 static int psp_v13_0_4_bootloader_load_sos(struct psp_context *psp) 155 { 156 int ret; 157 unsigned int psp_gfxdrv_command_reg = 0; 158 struct amdgpu_device *adev = psp->adev; 159 160 /* Check sOS sign of life register to confirm sys driver and sOS 161 * are already been loaded. 162 */ 163 if (psp_v13_0_4_is_sos_alive(psp)) 164 return 0; 165 166 ret = psp_v13_0_4_wait_for_bootloader(psp); 167 if (ret) 168 return ret; 169 170 ret = psp_copy_fw(psp, psp->sos.start_addr, psp->sos.size_bytes); 171 if (ret) 172 return ret; 173 174 /* Provide the PSP secure OS to bootloader */ 175 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, 176 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 177 psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV; 178 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, 179 psp_gfxdrv_command_reg); 180 181 /* there might be handshake issue with hardware which needs delay */ 182 mdelay(20); 183 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_81), 184 RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81), 0, 185 PSP_WAITREG_CHANGED); 186 187 return ret; 188 } 189 190 static int psp_v13_0_4_ring_stop(struct psp_context *psp, 191 enum psp_ring_type ring_type) 192 { 193 int ret = 0; 194 struct amdgpu_device *adev = psp->adev; 195 196 if (amdgpu_sriov_vf(adev)) { 197 /* Write the ring destroy command*/ 198 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, 199 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING); 200 /* there might be handshake issue with hardware which needs delay */ 201 mdelay(20); 202 /* Wait for response flag (bit 31) */ 203 ret = psp_wait_for( 204 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101), 205 MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0); 206 } else { 207 /* Write the ring destroy command*/ 208 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, 209 GFX_CTRL_CMD_ID_DESTROY_RINGS); 210 /* there might be handshake issue with hardware which needs delay */ 211 mdelay(20); 212 /* Wait for response flag (bit 31) */ 213 ret = psp_wait_for( 214 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), 215 MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0); 216 } 217 218 return ret; 219 } 220 221 static int psp_v13_0_4_ring_create(struct psp_context *psp, 222 enum psp_ring_type ring_type) 223 { 224 int ret = 0; 225 unsigned int psp_ring_reg = 0; 226 struct psp_ring *ring = &psp->km_ring; 227 struct amdgpu_device *adev = psp->adev; 228 229 if (amdgpu_sriov_vf(adev)) { 230 ret = psp_v13_0_4_ring_stop(psp, ring_type); 231 if (ret) { 232 DRM_ERROR("psp_v13_0_ring_stop_sriov failed!\n"); 233 return ret; 234 } 235 236 /* Write low address of the ring to C2PMSG_102 */ 237 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 238 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, psp_ring_reg); 239 /* Write high address of the ring to C2PMSG_103 */ 240 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 241 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_103, psp_ring_reg); 242 243 /* Write the ring initialization command to C2PMSG_101 */ 244 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, 245 GFX_CTRL_CMD_ID_INIT_GPCOM_RING); 246 247 /* there might be handshake issue with hardware which needs delay */ 248 mdelay(20); 249 250 /* Wait for response flag (bit 31) in C2PMSG_101 */ 251 ret = psp_wait_for( 252 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101), 253 MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0); 254 255 } else { 256 /* Wait for sOS ready for ring creation */ 257 ret = psp_wait_for( 258 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), 259 MBOX_TOS_READY_FLAG, MBOX_TOS_READY_MASK, 0); 260 if (ret) { 261 DRM_ERROR("Failed to wait for trust OS ready for ring creation\n"); 262 return ret; 263 } 264 265 /* Write low address of the ring to C2PMSG_69 */ 266 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 267 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_69, psp_ring_reg); 268 /* Write high address of the ring to C2PMSG_70 */ 269 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 270 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_70, psp_ring_reg); 271 /* Write size of ring to C2PMSG_71 */ 272 psp_ring_reg = ring->ring_size; 273 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_71, psp_ring_reg); 274 /* Write the ring initialization command to C2PMSG_64 */ 275 psp_ring_reg = ring_type; 276 psp_ring_reg = psp_ring_reg << 16; 277 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, psp_ring_reg); 278 279 /* there might be handshake issue with hardware which needs delay */ 280 mdelay(20); 281 282 /* Wait for response flag (bit 31) in C2PMSG_64 */ 283 ret = psp_wait_for( 284 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), 285 MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0); 286 } 287 288 return ret; 289 } 290 291 static int psp_v13_0_4_ring_destroy(struct psp_context *psp, 292 enum psp_ring_type ring_type) 293 { 294 int ret = 0; 295 struct psp_ring *ring = &psp->km_ring; 296 struct amdgpu_device *adev = psp->adev; 297 298 ret = psp_v13_0_4_ring_stop(psp, ring_type); 299 if (ret) 300 DRM_ERROR("Fail to stop psp ring\n"); 301 302 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 303 &ring->ring_mem_mc_addr, 304 (void **)&ring->ring_mem); 305 306 return ret; 307 } 308 309 static uint32_t psp_v13_0_4_ring_get_wptr(struct psp_context *psp) 310 { 311 uint32_t data; 312 struct amdgpu_device *adev = psp->adev; 313 314 if (amdgpu_sriov_vf(adev)) 315 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102); 316 else 317 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67); 318 319 return data; 320 } 321 322 static void psp_v13_0_4_ring_set_wptr(struct psp_context *psp, uint32_t value) 323 { 324 struct amdgpu_device *adev = psp->adev; 325 326 if (amdgpu_sriov_vf(adev)) { 327 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, value); 328 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, 329 GFX_CTRL_CMD_ID_CONSUME_CMD); 330 } else 331 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67, value); 332 } 333 334 static const struct psp_funcs psp_v13_0_4_funcs = { 335 .init_microcode = psp_v13_0_4_init_microcode, 336 .bootloader_load_kdb = psp_v13_0_4_bootloader_load_kdb, 337 .bootloader_load_spl = psp_v13_0_4_bootloader_load_spl, 338 .bootloader_load_sysdrv = psp_v13_0_4_bootloader_load_sysdrv, 339 .bootloader_load_soc_drv = psp_v13_0_4_bootloader_load_soc_drv, 340 .bootloader_load_intf_drv = psp_v13_0_4_bootloader_load_intf_drv, 341 .bootloader_load_dbg_drv = psp_v13_0_4_bootloader_load_dbg_drv, 342 .bootloader_load_sos = psp_v13_0_4_bootloader_load_sos, 343 .ring_create = psp_v13_0_4_ring_create, 344 .ring_stop = psp_v13_0_4_ring_stop, 345 .ring_destroy = psp_v13_0_4_ring_destroy, 346 .ring_get_wptr = psp_v13_0_4_ring_get_wptr, 347 .ring_set_wptr = psp_v13_0_4_ring_set_wptr, 348 }; 349 350 void psp_v13_0_4_set_psp_funcs(struct psp_context *psp) 351 { 352 psp->funcs = &psp_v13_0_4_funcs; 353 } 354