1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "amdgpu.h" 24 #include "amdgpu_psp.h" 25 #include "amdgpu_ucode.h" 26 #include "soc15_common.h" 27 #include "psp_v13_0_4.h" 28 29 #include "mp/mp_13_0_4_offset.h" 30 #include "mp/mp_13_0_4_sh_mask.h" 31 32 MODULE_FIRMWARE("amdgpu/psp_13_0_4_toc.bin"); 33 MODULE_FIRMWARE("amdgpu/psp_13_0_4_ta.bin"); 34 35 static int psp_v13_0_4_init_microcode(struct psp_context *psp) 36 { 37 struct amdgpu_device *adev = psp->adev; 38 char ucode_prefix[30]; 39 int err = 0; 40 41 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); 42 43 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 44 case IP_VERSION(13, 0, 4): 45 err = psp_init_toc_microcode(psp, ucode_prefix); 46 if (err) 47 return err; 48 err = psp_init_ta_microcode(psp, ucode_prefix); 49 if (err) 50 return err; 51 break; 52 default: 53 BUG(); 54 } 55 56 return 0; 57 } 58 59 static bool psp_v13_0_4_is_sos_alive(struct psp_context *psp) 60 { 61 struct amdgpu_device *adev = psp->adev; 62 uint32_t sol_reg; 63 64 sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81); 65 66 return sol_reg != 0x0; 67 } 68 69 static int psp_v13_0_4_wait_for_bootloader(struct psp_context *psp) 70 { 71 struct amdgpu_device *adev = psp->adev; 72 73 int ret; 74 int retry_loop; 75 76 for (retry_loop = 0; retry_loop < 10; retry_loop++) { 77 /* Wait for bootloader to signify that is 78 ready having bit 31 of C2PMSG_35 set to 1 */ 79 ret = psp_wait_for(psp, 80 SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 81 0x80000000, 82 0x80000000, 83 false); 84 85 if (ret == 0) 86 return 0; 87 } 88 89 return ret; 90 } 91 92 static int psp_v13_0_4_bootloader_load_component(struct psp_context *psp, 93 struct psp_bin_desc *bin_desc, 94 enum psp_bootloader_cmd bl_cmd) 95 { 96 int ret; 97 uint32_t psp_gfxdrv_command_reg = 0; 98 struct amdgpu_device *adev = psp->adev; 99 100 /* Check tOS sign of life register to confirm sys driver and sOS 101 * are already been loaded. 102 */ 103 if (psp_v13_0_4_is_sos_alive(psp)) 104 return 0; 105 106 ret = psp_v13_0_4_wait_for_bootloader(psp); 107 if (ret) 108 return ret; 109 110 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 111 112 /* Copy PSP KDB binary to memory */ 113 memcpy(psp->fw_pri_buf, bin_desc->start_addr, bin_desc->size_bytes); 114 115 /* Provide the PSP KDB to bootloader */ 116 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, 117 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 118 psp_gfxdrv_command_reg = bl_cmd; 119 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, 120 psp_gfxdrv_command_reg); 121 122 ret = psp_v13_0_4_wait_for_bootloader(psp); 123 124 return ret; 125 } 126 127 static int psp_v13_0_4_bootloader_load_kdb(struct psp_context *psp) 128 { 129 return psp_v13_0_4_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_KEY_DATABASE); 130 } 131 132 static int psp_v13_0_4_bootloader_load_spl(struct psp_context *psp) 133 { 134 return psp_v13_0_4_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_TOS_SPL_TABLE); 135 } 136 137 static int psp_v13_0_4_bootloader_load_sysdrv(struct psp_context *psp) 138 { 139 return psp_v13_0_4_bootloader_load_component(psp, &psp->sys, PSP_BL__LOAD_SYSDRV); 140 } 141 142 static int psp_v13_0_4_bootloader_load_soc_drv(struct psp_context *psp) 143 { 144 return psp_v13_0_4_bootloader_load_component(psp, &psp->soc_drv, PSP_BL__LOAD_SOCDRV); 145 } 146 147 static int psp_v13_0_4_bootloader_load_intf_drv(struct psp_context *psp) 148 { 149 return psp_v13_0_4_bootloader_load_component(psp, &psp->intf_drv, PSP_BL__LOAD_INTFDRV); 150 } 151 152 static int psp_v13_0_4_bootloader_load_dbg_drv(struct psp_context *psp) 153 { 154 return psp_v13_0_4_bootloader_load_component(psp, &psp->dbg_drv, PSP_BL__LOAD_DBGDRV); 155 } 156 157 static int psp_v13_0_4_bootloader_load_sos(struct psp_context *psp) 158 { 159 int ret; 160 unsigned int psp_gfxdrv_command_reg = 0; 161 struct amdgpu_device *adev = psp->adev; 162 163 /* Check sOS sign of life register to confirm sys driver and sOS 164 * are already been loaded. 165 */ 166 if (psp_v13_0_4_is_sos_alive(psp)) 167 return 0; 168 169 ret = psp_v13_0_4_wait_for_bootloader(psp); 170 if (ret) 171 return ret; 172 173 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 174 175 /* Copy Secure OS binary to PSP memory */ 176 memcpy(psp->fw_pri_buf, psp->sos.start_addr, psp->sos.size_bytes); 177 178 /* Provide the PSP secure OS to bootloader */ 179 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, 180 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 181 psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV; 182 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, 183 psp_gfxdrv_command_reg); 184 185 /* there might be handshake issue with hardware which needs delay */ 186 mdelay(20); 187 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_81), 188 RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81), 189 0, true); 190 191 return ret; 192 } 193 194 static int psp_v13_0_4_ring_stop(struct psp_context *psp, 195 enum psp_ring_type ring_type) 196 { 197 int ret = 0; 198 struct amdgpu_device *adev = psp->adev; 199 200 if (amdgpu_sriov_vf(adev)) { 201 /* Write the ring destroy command*/ 202 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, 203 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING); 204 /* there might be handshake issue with hardware which needs delay */ 205 mdelay(20); 206 /* Wait for response flag (bit 31) */ 207 ret = psp_wait_for( 208 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101), 209 MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false); 210 } else { 211 /* Write the ring destroy command*/ 212 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, 213 GFX_CTRL_CMD_ID_DESTROY_RINGS); 214 /* there might be handshake issue with hardware which needs delay */ 215 mdelay(20); 216 /* Wait for response flag (bit 31) */ 217 ret = psp_wait_for( 218 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), 219 MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false); 220 } 221 222 return ret; 223 } 224 225 static int psp_v13_0_4_ring_create(struct psp_context *psp, 226 enum psp_ring_type ring_type) 227 { 228 int ret = 0; 229 unsigned int psp_ring_reg = 0; 230 struct psp_ring *ring = &psp->km_ring; 231 struct amdgpu_device *adev = psp->adev; 232 233 if (amdgpu_sriov_vf(adev)) { 234 ret = psp_v13_0_4_ring_stop(psp, ring_type); 235 if (ret) { 236 DRM_ERROR("psp_v13_0_ring_stop_sriov failed!\n"); 237 return ret; 238 } 239 240 /* Write low address of the ring to C2PMSG_102 */ 241 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 242 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, psp_ring_reg); 243 /* Write high address of the ring to C2PMSG_103 */ 244 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 245 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_103, psp_ring_reg); 246 247 /* Write the ring initialization command to C2PMSG_101 */ 248 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, 249 GFX_CTRL_CMD_ID_INIT_GPCOM_RING); 250 251 /* there might be handshake issue with hardware which needs delay */ 252 mdelay(20); 253 254 /* Wait for response flag (bit 31) in C2PMSG_101 */ 255 ret = psp_wait_for( 256 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101), 257 MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false); 258 259 } else { 260 /* Wait for sOS ready for ring creation */ 261 ret = psp_wait_for( 262 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), 263 MBOX_TOS_READY_FLAG, MBOX_TOS_READY_MASK, false); 264 if (ret) { 265 DRM_ERROR("Failed to wait for trust OS ready for ring creation\n"); 266 return ret; 267 } 268 269 /* Write low address of the ring to C2PMSG_69 */ 270 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 271 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_69, psp_ring_reg); 272 /* Write high address of the ring to C2PMSG_70 */ 273 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 274 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_70, psp_ring_reg); 275 /* Write size of ring to C2PMSG_71 */ 276 psp_ring_reg = ring->ring_size; 277 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_71, psp_ring_reg); 278 /* Write the ring initialization command to C2PMSG_64 */ 279 psp_ring_reg = ring_type; 280 psp_ring_reg = psp_ring_reg << 16; 281 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, psp_ring_reg); 282 283 /* there might be handshake issue with hardware which needs delay */ 284 mdelay(20); 285 286 /* Wait for response flag (bit 31) in C2PMSG_64 */ 287 ret = psp_wait_for( 288 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), 289 MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false); 290 } 291 292 return ret; 293 } 294 295 static int psp_v13_0_4_ring_destroy(struct psp_context *psp, 296 enum psp_ring_type ring_type) 297 { 298 int ret = 0; 299 struct psp_ring *ring = &psp->km_ring; 300 struct amdgpu_device *adev = psp->adev; 301 302 ret = psp_v13_0_4_ring_stop(psp, ring_type); 303 if (ret) 304 DRM_ERROR("Fail to stop psp ring\n"); 305 306 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 307 &ring->ring_mem_mc_addr, 308 (void **)&ring->ring_mem); 309 310 return ret; 311 } 312 313 static uint32_t psp_v13_0_4_ring_get_wptr(struct psp_context *psp) 314 { 315 uint32_t data; 316 struct amdgpu_device *adev = psp->adev; 317 318 if (amdgpu_sriov_vf(adev)) 319 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102); 320 else 321 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67); 322 323 return data; 324 } 325 326 static void psp_v13_0_4_ring_set_wptr(struct psp_context *psp, uint32_t value) 327 { 328 struct amdgpu_device *adev = psp->adev; 329 330 if (amdgpu_sriov_vf(adev)) { 331 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, value); 332 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, 333 GFX_CTRL_CMD_ID_CONSUME_CMD); 334 } else 335 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67, value); 336 } 337 338 static const struct psp_funcs psp_v13_0_4_funcs = { 339 .init_microcode = psp_v13_0_4_init_microcode, 340 .bootloader_load_kdb = psp_v13_0_4_bootloader_load_kdb, 341 .bootloader_load_spl = psp_v13_0_4_bootloader_load_spl, 342 .bootloader_load_sysdrv = psp_v13_0_4_bootloader_load_sysdrv, 343 .bootloader_load_soc_drv = psp_v13_0_4_bootloader_load_soc_drv, 344 .bootloader_load_intf_drv = psp_v13_0_4_bootloader_load_intf_drv, 345 .bootloader_load_dbg_drv = psp_v13_0_4_bootloader_load_dbg_drv, 346 .bootloader_load_sos = psp_v13_0_4_bootloader_load_sos, 347 .ring_create = psp_v13_0_4_ring_create, 348 .ring_stop = psp_v13_0_4_ring_stop, 349 .ring_destroy = psp_v13_0_4_ring_destroy, 350 .ring_get_wptr = psp_v13_0_4_ring_get_wptr, 351 .ring_set_wptr = psp_v13_0_4_ring_set_wptr, 352 }; 353 354 void psp_v13_0_4_set_psp_funcs(struct psp_context *psp) 355 { 356 psp->funcs = &psp_v13_0_4_funcs; 357 } 358