1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <drm/drm_drv.h> 24 #include <linux/vmalloc.h> 25 #include "amdgpu.h" 26 #include "amdgpu_psp.h" 27 #include "amdgpu_ucode.h" 28 #include "soc15_common.h" 29 #include "psp_v13_0.h" 30 31 #include "mp/mp_13_0_2_offset.h" 32 #include "mp/mp_13_0_2_sh_mask.h" 33 34 MODULE_FIRMWARE("amdgpu/aldebaran_sos.bin"); 35 MODULE_FIRMWARE("amdgpu/aldebaran_ta.bin"); 36 MODULE_FIRMWARE("amdgpu/aldebaran_cap.bin"); 37 MODULE_FIRMWARE("amdgpu/yellow_carp_toc.bin"); 38 MODULE_FIRMWARE("amdgpu/yellow_carp_ta.bin"); 39 MODULE_FIRMWARE("amdgpu/psp_13_0_5_toc.bin"); 40 MODULE_FIRMWARE("amdgpu/psp_13_0_5_ta.bin"); 41 MODULE_FIRMWARE("amdgpu/psp_13_0_8_toc.bin"); 42 MODULE_FIRMWARE("amdgpu/psp_13_0_8_ta.bin"); 43 MODULE_FIRMWARE("amdgpu/psp_13_0_0_sos.bin"); 44 MODULE_FIRMWARE("amdgpu/psp_13_0_0_ta.bin"); 45 MODULE_FIRMWARE("amdgpu/psp_13_0_7_sos.bin"); 46 MODULE_FIRMWARE("amdgpu/psp_13_0_7_ta.bin"); 47 MODULE_FIRMWARE("amdgpu/psp_13_0_10_sos.bin"); 48 MODULE_FIRMWARE("amdgpu/psp_13_0_10_ta.bin"); 49 MODULE_FIRMWARE("amdgpu/psp_13_0_11_toc.bin"); 50 MODULE_FIRMWARE("amdgpu/psp_13_0_11_ta.bin"); 51 MODULE_FIRMWARE("amdgpu/psp_13_0_6_sos.bin"); 52 MODULE_FIRMWARE("amdgpu/psp_13_0_6_ta.bin"); 53 MODULE_FIRMWARE("amdgpu/psp_14_0_0_toc.bin"); 54 MODULE_FIRMWARE("amdgpu/psp_14_0_0_ta.bin"); 55 56 /* For large FW files the time to complete can be very long */ 57 #define USBC_PD_POLLING_LIMIT_S 240 58 59 /* Read USB-PD from LFB */ 60 #define GFX_CMD_USB_PD_USE_LFB 0x480 61 62 /* VBIOS gfl defines */ 63 #define MBOX_READY_MASK 0x80000000 64 #define MBOX_STATUS_MASK 0x0000FFFF 65 #define MBOX_COMMAND_MASK 0x00FF0000 66 #define MBOX_READY_FLAG 0x80000000 67 #define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_LO 0x2 68 #define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI 0x3 69 #define C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE 0x4 70 71 /* memory training timeout define */ 72 #define MEM_TRAIN_SEND_MSG_TIMEOUT_US 3000000 73 74 static int psp_v13_0_init_microcode(struct psp_context *psp) 75 { 76 struct amdgpu_device *adev = psp->adev; 77 char ucode_prefix[30]; 78 int err = 0; 79 80 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); 81 82 switch (adev->ip_versions[MP0_HWIP][0]) { 83 case IP_VERSION(13, 0, 2): 84 err = psp_init_sos_microcode(psp, ucode_prefix); 85 if (err) 86 return err; 87 /* It's not necessary to load ras ta on Guest side */ 88 if (!amdgpu_sriov_vf(adev)) { 89 err = psp_init_ta_microcode(psp, ucode_prefix); 90 if (err) 91 return err; 92 } 93 break; 94 case IP_VERSION(13, 0, 1): 95 case IP_VERSION(13, 0, 3): 96 case IP_VERSION(13, 0, 5): 97 case IP_VERSION(13, 0, 8): 98 case IP_VERSION(13, 0, 11): 99 case IP_VERSION(14, 0, 0): 100 err = psp_init_toc_microcode(psp, ucode_prefix); 101 if (err) 102 return err; 103 err = psp_init_ta_microcode(psp, ucode_prefix); 104 if (err) 105 return err; 106 break; 107 case IP_VERSION(13, 0, 0): 108 case IP_VERSION(13, 0, 6): 109 case IP_VERSION(13, 0, 7): 110 case IP_VERSION(13, 0, 10): 111 err = psp_init_sos_microcode(psp, ucode_prefix); 112 if (err) 113 return err; 114 /* It's not necessary to load ras ta on Guest side */ 115 err = psp_init_ta_microcode(psp, ucode_prefix); 116 if (err) 117 return err; 118 break; 119 default: 120 BUG(); 121 } 122 123 return 0; 124 } 125 126 static bool psp_v13_0_is_sos_alive(struct psp_context *psp) 127 { 128 struct amdgpu_device *adev = psp->adev; 129 uint32_t sol_reg; 130 131 sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81); 132 133 return sol_reg != 0x0; 134 } 135 136 static int psp_v13_0_wait_for_vmbx_ready(struct psp_context *psp) 137 { 138 struct amdgpu_device *adev = psp->adev; 139 int retry_loop, ret; 140 141 for (retry_loop = 0; retry_loop < 70; retry_loop++) { 142 /* Wait for bootloader to signify that is 143 ready having bit 31 of C2PMSG_33 set to 1 */ 144 ret = psp_wait_for( 145 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_33), 146 0x80000000, 0xffffffff, false); 147 148 if (ret == 0) 149 break; 150 } 151 152 if (ret) 153 dev_warn(adev->dev, "Bootloader wait timed out"); 154 155 return ret; 156 } 157 158 static int psp_v13_0_wait_for_bootloader(struct psp_context *psp) 159 { 160 struct amdgpu_device *adev = psp->adev; 161 int retry_loop, ret; 162 163 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 6)) 164 psp_v13_0_wait_for_vmbx_ready(psp); 165 166 /* Wait for bootloader to signify that it is ready having bit 31 of 167 * C2PMSG_35 set to 1. All other bits are expected to be cleared. 168 * If there is an error in processing command, bits[7:0] will be set. 169 * This is applicable for PSP v13.0.6 and newer. 170 */ 171 for (retry_loop = 0; retry_loop < 10; retry_loop++) { 172 ret = psp_wait_for( 173 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 174 0x80000000, 0xffffffff, false); 175 176 if (ret == 0) 177 return 0; 178 } 179 180 return ret; 181 } 182 183 static int psp_v13_0_bootloader_load_component(struct psp_context *psp, 184 struct psp_bin_desc *bin_desc, 185 enum psp_bootloader_cmd bl_cmd) 186 { 187 int ret; 188 uint32_t psp_gfxdrv_command_reg = 0; 189 struct amdgpu_device *adev = psp->adev; 190 191 /* Check tOS sign of life register to confirm sys driver and sOS 192 * are already been loaded. 193 */ 194 if (psp_v13_0_is_sos_alive(psp)) 195 return 0; 196 197 ret = psp_v13_0_wait_for_bootloader(psp); 198 if (ret) 199 return ret; 200 201 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 202 203 /* Copy PSP KDB binary to memory */ 204 memcpy(psp->fw_pri_buf, bin_desc->start_addr, bin_desc->size_bytes); 205 206 /* Provide the PSP KDB to bootloader */ 207 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, 208 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 209 psp_gfxdrv_command_reg = bl_cmd; 210 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, 211 psp_gfxdrv_command_reg); 212 213 ret = psp_v13_0_wait_for_bootloader(psp); 214 215 return ret; 216 } 217 218 static int psp_v13_0_bootloader_load_kdb(struct psp_context *psp) 219 { 220 return psp_v13_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_KEY_DATABASE); 221 } 222 223 static int psp_v13_0_bootloader_load_spl(struct psp_context *psp) 224 { 225 return psp_v13_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_TOS_SPL_TABLE); 226 } 227 228 static int psp_v13_0_bootloader_load_sysdrv(struct psp_context *psp) 229 { 230 return psp_v13_0_bootloader_load_component(psp, &psp->sys, PSP_BL__LOAD_SYSDRV); 231 } 232 233 static int psp_v13_0_bootloader_load_soc_drv(struct psp_context *psp) 234 { 235 return psp_v13_0_bootloader_load_component(psp, &psp->soc_drv, PSP_BL__LOAD_SOCDRV); 236 } 237 238 static int psp_v13_0_bootloader_load_intf_drv(struct psp_context *psp) 239 { 240 return psp_v13_0_bootloader_load_component(psp, &psp->intf_drv, PSP_BL__LOAD_INTFDRV); 241 } 242 243 static int psp_v13_0_bootloader_load_dbg_drv(struct psp_context *psp) 244 { 245 return psp_v13_0_bootloader_load_component(psp, &psp->dbg_drv, PSP_BL__LOAD_DBGDRV); 246 } 247 248 static int psp_v13_0_bootloader_load_ras_drv(struct psp_context *psp) 249 { 250 return psp_v13_0_bootloader_load_component(psp, &psp->ras_drv, PSP_BL__LOAD_RASDRV); 251 } 252 253 254 static int psp_v13_0_bootloader_load_sos(struct psp_context *psp) 255 { 256 int ret; 257 unsigned int psp_gfxdrv_command_reg = 0; 258 struct amdgpu_device *adev = psp->adev; 259 260 /* Check sOS sign of life register to confirm sys driver and sOS 261 * are already been loaded. 262 */ 263 if (psp_v13_0_is_sos_alive(psp)) 264 return 0; 265 266 ret = psp_v13_0_wait_for_bootloader(psp); 267 if (ret) 268 return ret; 269 270 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 271 272 /* Copy Secure OS binary to PSP memory */ 273 memcpy(psp->fw_pri_buf, psp->sos.start_addr, psp->sos.size_bytes); 274 275 /* Provide the PSP secure OS to bootloader */ 276 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, 277 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 278 psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV; 279 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, 280 psp_gfxdrv_command_reg); 281 282 /* there might be handshake issue with hardware which needs delay */ 283 mdelay(20); 284 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_81), 285 RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81), 286 0, true); 287 288 return ret; 289 } 290 291 static int psp_v13_0_ring_stop(struct psp_context *psp, 292 enum psp_ring_type ring_type) 293 { 294 int ret = 0; 295 struct amdgpu_device *adev = psp->adev; 296 297 if (amdgpu_sriov_vf(adev)) { 298 /* Write the ring destroy command*/ 299 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, 300 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING); 301 /* there might be handshake issue with hardware which needs delay */ 302 mdelay(20); 303 /* Wait for response flag (bit 31) */ 304 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101), 305 0x80000000, 0x80000000, false); 306 } else { 307 /* Write the ring destroy command*/ 308 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, 309 GFX_CTRL_CMD_ID_DESTROY_RINGS); 310 /* there might be handshake issue with hardware which needs delay */ 311 mdelay(20); 312 /* Wait for response flag (bit 31) */ 313 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), 314 0x80000000, 0x80000000, false); 315 } 316 317 return ret; 318 } 319 320 static int psp_v13_0_ring_create(struct psp_context *psp, 321 enum psp_ring_type ring_type) 322 { 323 int ret = 0; 324 unsigned int psp_ring_reg = 0; 325 struct psp_ring *ring = &psp->km_ring; 326 struct amdgpu_device *adev = psp->adev; 327 328 if (amdgpu_sriov_vf(adev)) { 329 ret = psp_v13_0_ring_stop(psp, ring_type); 330 if (ret) { 331 DRM_ERROR("psp_v13_0_ring_stop_sriov failed!\n"); 332 return ret; 333 } 334 335 /* Write low address of the ring to C2PMSG_102 */ 336 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 337 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, psp_ring_reg); 338 /* Write high address of the ring to C2PMSG_103 */ 339 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 340 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_103, psp_ring_reg); 341 342 /* Write the ring initialization command to C2PMSG_101 */ 343 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, 344 GFX_CTRL_CMD_ID_INIT_GPCOM_RING); 345 346 /* there might be handshake issue with hardware which needs delay */ 347 mdelay(20); 348 349 /* Wait for response flag (bit 31) in C2PMSG_101 */ 350 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101), 351 0x80000000, 0x8000FFFF, false); 352 353 } else { 354 /* Wait for sOS ready for ring creation */ 355 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), 356 0x80000000, 0x80000000, false); 357 if (ret) { 358 DRM_ERROR("Failed to wait for trust OS ready for ring creation\n"); 359 return ret; 360 } 361 362 /* Write low address of the ring to C2PMSG_69 */ 363 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 364 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_69, psp_ring_reg); 365 /* Write high address of the ring to C2PMSG_70 */ 366 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 367 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_70, psp_ring_reg); 368 /* Write size of ring to C2PMSG_71 */ 369 psp_ring_reg = ring->ring_size; 370 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_71, psp_ring_reg); 371 /* Write the ring initialization command to C2PMSG_64 */ 372 psp_ring_reg = ring_type; 373 psp_ring_reg = psp_ring_reg << 16; 374 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, psp_ring_reg); 375 376 /* there might be handshake issue with hardware which needs delay */ 377 mdelay(20); 378 379 /* Wait for response flag (bit 31) in C2PMSG_64 */ 380 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), 381 0x80000000, 0x8000FFFF, false); 382 } 383 384 return ret; 385 } 386 387 static int psp_v13_0_ring_destroy(struct psp_context *psp, 388 enum psp_ring_type ring_type) 389 { 390 int ret = 0; 391 struct psp_ring *ring = &psp->km_ring; 392 struct amdgpu_device *adev = psp->adev; 393 394 ret = psp_v13_0_ring_stop(psp, ring_type); 395 if (ret) 396 DRM_ERROR("Fail to stop psp ring\n"); 397 398 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 399 &ring->ring_mem_mc_addr, 400 (void **)&ring->ring_mem); 401 402 return ret; 403 } 404 405 static uint32_t psp_v13_0_ring_get_wptr(struct psp_context *psp) 406 { 407 uint32_t data; 408 struct amdgpu_device *adev = psp->adev; 409 410 if (amdgpu_sriov_vf(adev)) 411 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102); 412 else 413 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67); 414 415 return data; 416 } 417 418 static void psp_v13_0_ring_set_wptr(struct psp_context *psp, uint32_t value) 419 { 420 struct amdgpu_device *adev = psp->adev; 421 422 if (amdgpu_sriov_vf(adev)) { 423 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, value); 424 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, 425 GFX_CTRL_CMD_ID_CONSUME_CMD); 426 } else 427 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67, value); 428 } 429 430 static int psp_v13_0_memory_training_send_msg(struct psp_context *psp, int msg) 431 { 432 int ret; 433 int i; 434 uint32_t data_32; 435 int max_wait; 436 struct amdgpu_device *adev = psp->adev; 437 438 data_32 = (psp->mem_train_ctx.c2p_train_data_offset >> 20); 439 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, data_32); 440 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, msg); 441 442 max_wait = MEM_TRAIN_SEND_MSG_TIMEOUT_US / adev->usec_timeout; 443 for (i = 0; i < max_wait; i++) { 444 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 445 0x80000000, 0x80000000, false); 446 if (ret == 0) 447 break; 448 } 449 if (i < max_wait) 450 ret = 0; 451 else 452 ret = -ETIME; 453 454 dev_dbg(adev->dev, "training %s %s, cost %d @ %d ms\n", 455 (msg == PSP_BL__DRAM_SHORT_TRAIN) ? "short" : "long", 456 (ret == 0) ? "succeed" : "failed", 457 i, adev->usec_timeout/1000); 458 return ret; 459 } 460 461 462 static int psp_v13_0_memory_training(struct psp_context *psp, uint32_t ops) 463 { 464 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 465 uint32_t *pcache = (uint32_t *)ctx->sys_cache; 466 struct amdgpu_device *adev = psp->adev; 467 uint32_t p2c_header[4]; 468 uint32_t sz; 469 void *buf; 470 int ret, idx; 471 472 if (ctx->init == PSP_MEM_TRAIN_NOT_SUPPORT) { 473 dev_dbg(adev->dev, "Memory training is not supported.\n"); 474 return 0; 475 } else if (ctx->init != PSP_MEM_TRAIN_INIT_SUCCESS) { 476 dev_err(adev->dev, "Memory training initialization failure.\n"); 477 return -EINVAL; 478 } 479 480 if (psp_v13_0_is_sos_alive(psp)) { 481 dev_dbg(adev->dev, "SOS is alive, skip memory training.\n"); 482 return 0; 483 } 484 485 amdgpu_device_vram_access(adev, ctx->p2c_train_data_offset, p2c_header, sizeof(p2c_header), false); 486 dev_dbg(adev->dev, "sys_cache[%08x,%08x,%08x,%08x] p2c_header[%08x,%08x,%08x,%08x]\n", 487 pcache[0], pcache[1], pcache[2], pcache[3], 488 p2c_header[0], p2c_header[1], p2c_header[2], p2c_header[3]); 489 490 if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) { 491 dev_dbg(adev->dev, "Short training depends on restore.\n"); 492 ops |= PSP_MEM_TRAIN_RESTORE; 493 } 494 495 if ((ops & PSP_MEM_TRAIN_RESTORE) && 496 pcache[0] != MEM_TRAIN_SYSTEM_SIGNATURE) { 497 dev_dbg(adev->dev, "sys_cache[0] is invalid, restore depends on save.\n"); 498 ops |= PSP_MEM_TRAIN_SAVE; 499 } 500 501 if (p2c_header[0] == MEM_TRAIN_SYSTEM_SIGNATURE && 502 !(pcache[0] == MEM_TRAIN_SYSTEM_SIGNATURE && 503 pcache[3] == p2c_header[3])) { 504 dev_dbg(adev->dev, "sys_cache is invalid or out-of-date, need save training data to sys_cache.\n"); 505 ops |= PSP_MEM_TRAIN_SAVE; 506 } 507 508 if ((ops & PSP_MEM_TRAIN_SAVE) && 509 p2c_header[0] != MEM_TRAIN_SYSTEM_SIGNATURE) { 510 dev_dbg(adev->dev, "p2c_header[0] is invalid, save depends on long training.\n"); 511 ops |= PSP_MEM_TRAIN_SEND_LONG_MSG; 512 } 513 514 if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) { 515 ops &= ~PSP_MEM_TRAIN_SEND_SHORT_MSG; 516 ops |= PSP_MEM_TRAIN_SAVE; 517 } 518 519 dev_dbg(adev->dev, "Memory training ops:%x.\n", ops); 520 521 if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) { 522 /* 523 * Long training will encroach a certain amount on the bottom of VRAM; 524 * save the content from the bottom of VRAM to system memory 525 * before training, and restore it after training to avoid 526 * VRAM corruption. 527 */ 528 sz = GDDR6_MEM_TRAINING_ENCROACHED_SIZE; 529 530 if (adev->gmc.visible_vram_size < sz || !adev->mman.aper_base_kaddr) { 531 dev_err(adev->dev, "visible_vram_size %llx or aper_base_kaddr %p is not initialized.\n", 532 adev->gmc.visible_vram_size, 533 adev->mman.aper_base_kaddr); 534 return -EINVAL; 535 } 536 537 buf = vmalloc(sz); 538 if (!buf) { 539 dev_err(adev->dev, "failed to allocate system memory.\n"); 540 return -ENOMEM; 541 } 542 543 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 544 memcpy_fromio(buf, adev->mman.aper_base_kaddr, sz); 545 ret = psp_v13_0_memory_training_send_msg(psp, PSP_BL__DRAM_LONG_TRAIN); 546 if (ret) { 547 DRM_ERROR("Send long training msg failed.\n"); 548 vfree(buf); 549 drm_dev_exit(idx); 550 return ret; 551 } 552 553 memcpy_toio(adev->mman.aper_base_kaddr, buf, sz); 554 adev->hdp.funcs->flush_hdp(adev, NULL); 555 vfree(buf); 556 drm_dev_exit(idx); 557 } else { 558 vfree(buf); 559 return -ENODEV; 560 } 561 } 562 563 if (ops & PSP_MEM_TRAIN_SAVE) { 564 amdgpu_device_vram_access(psp->adev, ctx->p2c_train_data_offset, ctx->sys_cache, ctx->train_data_size, false); 565 } 566 567 if (ops & PSP_MEM_TRAIN_RESTORE) { 568 amdgpu_device_vram_access(psp->adev, ctx->c2p_train_data_offset, ctx->sys_cache, ctx->train_data_size, true); 569 } 570 571 if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) { 572 ret = psp_v13_0_memory_training_send_msg(psp, (amdgpu_force_long_training > 0) ? 573 PSP_BL__DRAM_LONG_TRAIN : PSP_BL__DRAM_SHORT_TRAIN); 574 if (ret) { 575 dev_err(adev->dev, "send training msg failed.\n"); 576 return ret; 577 } 578 } 579 ctx->training_cnt++; 580 return 0; 581 } 582 583 static int psp_v13_0_load_usbc_pd_fw(struct psp_context *psp, uint64_t fw_pri_mc_addr) 584 { 585 struct amdgpu_device *adev = psp->adev; 586 uint32_t reg_status; 587 int ret, i = 0; 588 589 /* 590 * LFB address which is aligned to 1MB address and has to be 591 * right-shifted by 20 so that LFB address can be passed on a 32-bit C2P 592 * register 593 */ 594 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, (fw_pri_mc_addr >> 20)); 595 596 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 597 0x80000000, 0x80000000, false); 598 if (ret) 599 return ret; 600 601 /* Fireup interrupt so PSP can pick up the address */ 602 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, (GFX_CMD_USB_PD_USE_LFB << 16)); 603 604 /* FW load takes very long time */ 605 do { 606 msleep(1000); 607 reg_status = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35); 608 609 if (reg_status & 0x80000000) 610 goto done; 611 612 } while (++i < USBC_PD_POLLING_LIMIT_S); 613 614 return -ETIME; 615 done: 616 617 if ((reg_status & 0xFFFF) != 0) { 618 DRM_ERROR("Address load failed - MP0_SMN_C2PMSG_35.Bits [15:0] = %04x\n", 619 reg_status & 0xFFFF); 620 return -EIO; 621 } 622 623 return 0; 624 } 625 626 static int psp_v13_0_read_usbc_pd_fw(struct psp_context *psp, uint32_t *fw_ver) 627 { 628 struct amdgpu_device *adev = psp->adev; 629 int ret; 630 631 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, C2PMSG_CMD_GFX_USB_PD_FW_VER); 632 633 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 634 0x80000000, 0x80000000, false); 635 if (!ret) 636 *fw_ver = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36); 637 638 return ret; 639 } 640 641 static int psp_v13_0_exec_spi_cmd(struct psp_context *psp, int cmd) 642 { 643 uint32_t reg_status = 0, reg_val = 0; 644 struct amdgpu_device *adev = psp->adev; 645 int ret; 646 647 /* clear MBX ready (MBOX_READY_MASK bit is 0) and set update command */ 648 reg_val |= (cmd << 16); 649 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115, reg_val); 650 651 /* Ring the doorbell */ 652 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_73, 1); 653 654 if (cmd == C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE) 655 ret = psp_wait_for_spirom_update(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115), 656 MBOX_READY_FLAG, MBOX_READY_MASK, PSP_SPIROM_UPDATE_TIMEOUT); 657 else 658 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115), 659 MBOX_READY_FLAG, MBOX_READY_MASK, false); 660 if (ret) { 661 dev_err(adev->dev, "SPI cmd %x timed out, ret = %d", cmd, ret); 662 return ret; 663 } 664 665 reg_status = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115); 666 if ((reg_status & 0xFFFF) != 0) { 667 dev_err(adev->dev, "SPI cmd %x failed, fail status = %04x\n", 668 cmd, reg_status & 0xFFFF); 669 return -EIO; 670 } 671 672 return 0; 673 } 674 675 static int psp_v13_0_update_spirom(struct psp_context *psp, 676 uint64_t fw_pri_mc_addr) 677 { 678 struct amdgpu_device *adev = psp->adev; 679 int ret; 680 681 /* Confirm PSP is ready to start */ 682 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115), 683 MBOX_READY_FLAG, MBOX_READY_MASK, false); 684 if (ret) { 685 dev_err(adev->dev, "PSP Not ready to start processing, ret = %d", ret); 686 return ret; 687 } 688 689 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, lower_32_bits(fw_pri_mc_addr)); 690 691 ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_LO); 692 if (ret) 693 return ret; 694 695 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, upper_32_bits(fw_pri_mc_addr)); 696 697 ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI); 698 if (ret) 699 return ret; 700 701 psp->vbflash_done = true; 702 703 ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE); 704 if (ret) 705 return ret; 706 707 return 0; 708 } 709 710 static int psp_v13_0_vbflash_status(struct psp_context *psp) 711 { 712 struct amdgpu_device *adev = psp->adev; 713 714 return RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115); 715 } 716 717 static int psp_v13_0_fatal_error_recovery_quirk(struct psp_context *psp) 718 { 719 struct amdgpu_device *adev = psp->adev; 720 721 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 10)) { 722 uint32_t reg_data; 723 /* MP1 fatal error: trigger PSP dram read to unhalt PSP 724 * during MP1 triggered sync flood. 725 */ 726 reg_data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67); 727 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67, reg_data + 0x10); 728 729 /* delay 1000ms for the mode1 reset for fatal error 730 * to be recovered back. 731 */ 732 msleep(1000); 733 } 734 735 return 0; 736 } 737 738 static const struct psp_funcs psp_v13_0_funcs = { 739 .init_microcode = psp_v13_0_init_microcode, 740 .wait_for_bootloader = psp_v13_0_wait_for_bootloader, 741 .bootloader_load_kdb = psp_v13_0_bootloader_load_kdb, 742 .bootloader_load_spl = psp_v13_0_bootloader_load_spl, 743 .bootloader_load_sysdrv = psp_v13_0_bootloader_load_sysdrv, 744 .bootloader_load_soc_drv = psp_v13_0_bootloader_load_soc_drv, 745 .bootloader_load_intf_drv = psp_v13_0_bootloader_load_intf_drv, 746 .bootloader_load_dbg_drv = psp_v13_0_bootloader_load_dbg_drv, 747 .bootloader_load_ras_drv = psp_v13_0_bootloader_load_ras_drv, 748 .bootloader_load_sos = psp_v13_0_bootloader_load_sos, 749 .ring_create = psp_v13_0_ring_create, 750 .ring_stop = psp_v13_0_ring_stop, 751 .ring_destroy = psp_v13_0_ring_destroy, 752 .ring_get_wptr = psp_v13_0_ring_get_wptr, 753 .ring_set_wptr = psp_v13_0_ring_set_wptr, 754 .mem_training = psp_v13_0_memory_training, 755 .load_usbc_pd_fw = psp_v13_0_load_usbc_pd_fw, 756 .read_usbc_pd_fw = psp_v13_0_read_usbc_pd_fw, 757 .update_spirom = psp_v13_0_update_spirom, 758 .vbflash_stat = psp_v13_0_vbflash_status, 759 .fatal_error_recovery_quirk = psp_v13_0_fatal_error_recovery_quirk, 760 }; 761 762 void psp_v13_0_set_psp_funcs(struct psp_context *psp) 763 { 764 psp->funcs = &psp_v13_0_funcs; 765 } 766