1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "amdgpu.h" 24 #include "amdgpu_psp.h" 25 #include "amdgpu_ucode.h" 26 #include "soc15_common.h" 27 #include "psp_v13_0.h" 28 29 #include "mp/mp_13_0_2_offset.h" 30 #include "mp/mp_13_0_2_sh_mask.h" 31 32 MODULE_FIRMWARE("amdgpu/aldebaran_sos.bin"); 33 MODULE_FIRMWARE("amdgpu/aldebaran_ta.bin"); 34 MODULE_FIRMWARE("amdgpu/aldebaran_cap.bin"); 35 MODULE_FIRMWARE("amdgpu/yellow_carp_toc.bin"); 36 MODULE_FIRMWARE("amdgpu/yellow_carp_ta.bin"); 37 MODULE_FIRMWARE("amdgpu/psp_13_0_5_toc.bin"); 38 MODULE_FIRMWARE("amdgpu/psp_13_0_5_ta.bin"); 39 MODULE_FIRMWARE("amdgpu/psp_13_0_8_toc.bin"); 40 MODULE_FIRMWARE("amdgpu/psp_13_0_8_ta.bin"); 41 MODULE_FIRMWARE("amdgpu/psp_13_0_0_sos.bin"); 42 MODULE_FIRMWARE("amdgpu/psp_13_0_7_sos.bin"); 43 44 /* For large FW files the time to complete can be very long */ 45 #define USBC_PD_POLLING_LIMIT_S 240 46 47 /* Read USB-PD from LFB */ 48 #define GFX_CMD_USB_PD_USE_LFB 0x480 49 50 /* VBIOS gfl defines */ 51 #define MBOX_READY_MASK 0x80000000 52 #define MBOX_STATUS_MASK 0x0000FFFF 53 #define MBOX_COMMAND_MASK 0x00FF0000 54 #define MBOX_READY_FLAG 0x80000000 55 #define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_LO 0x2 56 #define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI 0x3 57 #define C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE 0x4 58 59 static int psp_v13_0_init_microcode(struct psp_context *psp) 60 { 61 struct amdgpu_device *adev = psp->adev; 62 const char *chip_name; 63 char ucode_prefix[30]; 64 int err = 0; 65 66 switch (adev->ip_versions[MP0_HWIP][0]) { 67 case IP_VERSION(13, 0, 2): 68 chip_name = "aldebaran"; 69 break; 70 case IP_VERSION(13, 0, 1): 71 case IP_VERSION(13, 0, 3): 72 chip_name = "yellow_carp"; 73 break; 74 default: 75 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); 76 chip_name = ucode_prefix; 77 break; 78 } 79 80 switch (adev->ip_versions[MP0_HWIP][0]) { 81 case IP_VERSION(13, 0, 2): 82 err = psp_init_sos_microcode(psp, chip_name); 83 if (err) 84 return err; 85 /* It's not necessary to load ras ta on Guest side */ 86 if (!amdgpu_sriov_vf(adev)) { 87 err = psp_init_ta_microcode(&adev->psp, chip_name); 88 if (err) 89 return err; 90 } 91 break; 92 case IP_VERSION(13, 0, 1): 93 case IP_VERSION(13, 0, 3): 94 case IP_VERSION(13, 0, 5): 95 case IP_VERSION(13, 0, 8): 96 err = psp_init_toc_microcode(psp, chip_name); 97 if (err) 98 return err; 99 err = psp_init_ta_microcode(psp, chip_name); 100 if (err) 101 return err; 102 break; 103 case IP_VERSION(13, 0, 0): 104 case IP_VERSION(13, 0, 7): 105 err = psp_init_sos_microcode(psp, chip_name); 106 if (err) 107 return err; 108 break; 109 default: 110 BUG(); 111 } 112 113 return 0; 114 } 115 116 static bool psp_v13_0_is_sos_alive(struct psp_context *psp) 117 { 118 struct amdgpu_device *adev = psp->adev; 119 uint32_t sol_reg; 120 121 sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81); 122 123 return sol_reg != 0x0; 124 } 125 126 static int psp_v13_0_wait_for_bootloader(struct psp_context *psp) 127 { 128 struct amdgpu_device *adev = psp->adev; 129 130 int ret; 131 int retry_loop; 132 133 for (retry_loop = 0; retry_loop < 10; retry_loop++) { 134 /* Wait for bootloader to signify that is 135 ready having bit 31 of C2PMSG_35 set to 1 */ 136 ret = psp_wait_for(psp, 137 SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 138 0x80000000, 139 0x80000000, 140 false); 141 142 if (ret == 0) 143 return 0; 144 } 145 146 return ret; 147 } 148 149 static int psp_v13_0_bootloader_load_component(struct psp_context *psp, 150 struct psp_bin_desc *bin_desc, 151 enum psp_bootloader_cmd bl_cmd) 152 { 153 int ret; 154 uint32_t psp_gfxdrv_command_reg = 0; 155 struct amdgpu_device *adev = psp->adev; 156 157 /* Check tOS sign of life register to confirm sys driver and sOS 158 * are already been loaded. 159 */ 160 if (psp_v13_0_is_sos_alive(psp)) 161 return 0; 162 163 ret = psp_v13_0_wait_for_bootloader(psp); 164 if (ret) 165 return ret; 166 167 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 168 169 /* Copy PSP KDB binary to memory */ 170 memcpy(psp->fw_pri_buf, bin_desc->start_addr, bin_desc->size_bytes); 171 172 /* Provide the PSP KDB to bootloader */ 173 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, 174 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 175 psp_gfxdrv_command_reg = bl_cmd; 176 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, 177 psp_gfxdrv_command_reg); 178 179 ret = psp_v13_0_wait_for_bootloader(psp); 180 181 return ret; 182 } 183 184 static int psp_v13_0_bootloader_load_kdb(struct psp_context *psp) 185 { 186 return psp_v13_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_KEY_DATABASE); 187 } 188 189 static int psp_v13_0_bootloader_load_spl(struct psp_context *psp) 190 { 191 return psp_v13_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_TOS_SPL_TABLE); 192 } 193 194 static int psp_v13_0_bootloader_load_sysdrv(struct psp_context *psp) 195 { 196 return psp_v13_0_bootloader_load_component(psp, &psp->sys, PSP_BL__LOAD_SYSDRV); 197 } 198 199 static int psp_v13_0_bootloader_load_soc_drv(struct psp_context *psp) 200 { 201 return psp_v13_0_bootloader_load_component(psp, &psp->soc_drv, PSP_BL__LOAD_SOCDRV); 202 } 203 204 static int psp_v13_0_bootloader_load_intf_drv(struct psp_context *psp) 205 { 206 return psp_v13_0_bootloader_load_component(psp, &psp->intf_drv, PSP_BL__LOAD_INTFDRV); 207 } 208 209 static int psp_v13_0_bootloader_load_dbg_drv(struct psp_context *psp) 210 { 211 return psp_v13_0_bootloader_load_component(psp, &psp->dbg_drv, PSP_BL__LOAD_DBGDRV); 212 } 213 214 static int psp_v13_0_bootloader_load_sos(struct psp_context *psp) 215 { 216 int ret; 217 unsigned int psp_gfxdrv_command_reg = 0; 218 struct amdgpu_device *adev = psp->adev; 219 220 /* Check sOS sign of life register to confirm sys driver and sOS 221 * are already been loaded. 222 */ 223 if (psp_v13_0_is_sos_alive(psp)) 224 return 0; 225 226 ret = psp_v13_0_wait_for_bootloader(psp); 227 if (ret) 228 return ret; 229 230 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 231 232 /* Copy Secure OS binary to PSP memory */ 233 memcpy(psp->fw_pri_buf, psp->sos.start_addr, psp->sos.size_bytes); 234 235 /* Provide the PSP secure OS to bootloader */ 236 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, 237 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 238 psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV; 239 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, 240 psp_gfxdrv_command_reg); 241 242 /* there might be handshake issue with hardware which needs delay */ 243 mdelay(20); 244 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_81), 245 RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81), 246 0, true); 247 248 return ret; 249 } 250 251 static int psp_v13_0_ring_init(struct psp_context *psp, 252 enum psp_ring_type ring_type) 253 { 254 int ret = 0; 255 struct psp_ring *ring; 256 struct amdgpu_device *adev = psp->adev; 257 258 ring = &psp->km_ring; 259 260 ring->ring_type = ring_type; 261 262 /* allocate 4k Page of Local Frame Buffer memory for ring */ 263 ring->ring_size = 0x1000; 264 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE, 265 AMDGPU_GEM_DOMAIN_VRAM, 266 &adev->firmware.rbuf, 267 &ring->ring_mem_mc_addr, 268 (void **)&ring->ring_mem); 269 if (ret) { 270 ring->ring_size = 0; 271 return ret; 272 } 273 274 return 0; 275 } 276 277 static int psp_v13_0_ring_stop(struct psp_context *psp, 278 enum psp_ring_type ring_type) 279 { 280 int ret = 0; 281 struct amdgpu_device *adev = psp->adev; 282 283 if (amdgpu_sriov_vf(adev)) { 284 /* Write the ring destroy command*/ 285 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, 286 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING); 287 /* there might be handshake issue with hardware which needs delay */ 288 mdelay(20); 289 /* Wait for response flag (bit 31) */ 290 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101), 291 0x80000000, 0x80000000, false); 292 } else { 293 /* Write the ring destroy command*/ 294 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, 295 GFX_CTRL_CMD_ID_DESTROY_RINGS); 296 /* there might be handshake issue with hardware which needs delay */ 297 mdelay(20); 298 /* Wait for response flag (bit 31) */ 299 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), 300 0x80000000, 0x80000000, false); 301 } 302 303 return ret; 304 } 305 306 static int psp_v13_0_ring_create(struct psp_context *psp, 307 enum psp_ring_type ring_type) 308 { 309 int ret = 0; 310 unsigned int psp_ring_reg = 0; 311 struct psp_ring *ring = &psp->km_ring; 312 struct amdgpu_device *adev = psp->adev; 313 314 if (amdgpu_sriov_vf(adev)) { 315 ret = psp_v13_0_ring_stop(psp, ring_type); 316 if (ret) { 317 DRM_ERROR("psp_v13_0_ring_stop_sriov failed!\n"); 318 return ret; 319 } 320 321 /* Write low address of the ring to C2PMSG_102 */ 322 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 323 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, psp_ring_reg); 324 /* Write high address of the ring to C2PMSG_103 */ 325 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 326 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_103, psp_ring_reg); 327 328 /* Write the ring initialization command to C2PMSG_101 */ 329 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, 330 GFX_CTRL_CMD_ID_INIT_GPCOM_RING); 331 332 /* there might be handshake issue with hardware which needs delay */ 333 mdelay(20); 334 335 /* Wait for response flag (bit 31) in C2PMSG_101 */ 336 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101), 337 0x80000000, 0x8000FFFF, false); 338 339 } else { 340 /* Wait for sOS ready for ring creation */ 341 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), 342 0x80000000, 0x80000000, false); 343 if (ret) { 344 DRM_ERROR("Failed to wait for trust OS ready for ring creation\n"); 345 return ret; 346 } 347 348 /* Write low address of the ring to C2PMSG_69 */ 349 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 350 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_69, psp_ring_reg); 351 /* Write high address of the ring to C2PMSG_70 */ 352 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 353 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_70, psp_ring_reg); 354 /* Write size of ring to C2PMSG_71 */ 355 psp_ring_reg = ring->ring_size; 356 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_71, psp_ring_reg); 357 /* Write the ring initialization command to C2PMSG_64 */ 358 psp_ring_reg = ring_type; 359 psp_ring_reg = psp_ring_reg << 16; 360 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, psp_ring_reg); 361 362 /* there might be handshake issue with hardware which needs delay */ 363 mdelay(20); 364 365 /* Wait for response flag (bit 31) in C2PMSG_64 */ 366 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), 367 0x80000000, 0x8000FFFF, false); 368 } 369 370 return ret; 371 } 372 373 static int psp_v13_0_ring_destroy(struct psp_context *psp, 374 enum psp_ring_type ring_type) 375 { 376 int ret = 0; 377 struct psp_ring *ring = &psp->km_ring; 378 struct amdgpu_device *adev = psp->adev; 379 380 ret = psp_v13_0_ring_stop(psp, ring_type); 381 if (ret) 382 DRM_ERROR("Fail to stop psp ring\n"); 383 384 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 385 &ring->ring_mem_mc_addr, 386 (void **)&ring->ring_mem); 387 388 return ret; 389 } 390 391 static uint32_t psp_v13_0_ring_get_wptr(struct psp_context *psp) 392 { 393 uint32_t data; 394 struct amdgpu_device *adev = psp->adev; 395 396 if (amdgpu_sriov_vf(adev)) 397 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102); 398 else 399 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67); 400 401 return data; 402 } 403 404 static void psp_v13_0_ring_set_wptr(struct psp_context *psp, uint32_t value) 405 { 406 struct amdgpu_device *adev = psp->adev; 407 408 if (amdgpu_sriov_vf(adev)) { 409 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, value); 410 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, 411 GFX_CTRL_CMD_ID_CONSUME_CMD); 412 } else 413 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67, value); 414 } 415 416 static int psp_v13_0_load_usbc_pd_fw(struct psp_context *psp, uint64_t fw_pri_mc_addr) 417 { 418 struct amdgpu_device *adev = psp->adev; 419 uint32_t reg_status; 420 int ret, i = 0; 421 422 /* 423 * LFB address which is aligned to 1MB address and has to be 424 * right-shifted by 20 so that LFB address can be passed on a 32-bit C2P 425 * register 426 */ 427 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, (fw_pri_mc_addr >> 20)); 428 429 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 430 0x80000000, 0x80000000, false); 431 if (ret) 432 return ret; 433 434 /* Fireup interrupt so PSP can pick up the address */ 435 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, (GFX_CMD_USB_PD_USE_LFB << 16)); 436 437 /* FW load takes very long time */ 438 do { 439 msleep(1000); 440 reg_status = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35); 441 442 if (reg_status & 0x80000000) 443 goto done; 444 445 } while (++i < USBC_PD_POLLING_LIMIT_S); 446 447 return -ETIME; 448 done: 449 450 if ((reg_status & 0xFFFF) != 0) { 451 DRM_ERROR("Address load failed - MP0_SMN_C2PMSG_35.Bits [15:0] = %04x\n", 452 reg_status & 0xFFFF); 453 return -EIO; 454 } 455 456 return 0; 457 } 458 459 static int psp_v13_0_read_usbc_pd_fw(struct psp_context *psp, uint32_t *fw_ver) 460 { 461 struct amdgpu_device *adev = psp->adev; 462 int ret; 463 464 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, C2PMSG_CMD_GFX_USB_PD_FW_VER); 465 466 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 467 0x80000000, 0x80000000, false); 468 if (!ret) 469 *fw_ver = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36); 470 471 return ret; 472 } 473 474 static int psp_v13_0_exec_spi_cmd(struct psp_context *psp, int cmd) 475 { 476 uint32_t reg_status = 0, reg_val = 0; 477 struct amdgpu_device *adev = psp->adev; 478 int ret; 479 480 /* clear MBX ready (MBOX_READY_MASK bit is 0) and set update command */ 481 reg_val |= (cmd << 16); 482 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115, reg_val); 483 484 /* Ring the doorbell */ 485 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_73, 1); 486 487 if (cmd == C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE) 488 return 0; 489 490 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115), 491 MBOX_READY_FLAG, MBOX_READY_MASK, false); 492 if (ret) { 493 dev_err(adev->dev, "SPI cmd %x timed out, ret = %d", cmd, ret); 494 return ret; 495 } 496 497 reg_status = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115); 498 if ((reg_status & 0xFFFF) != 0) { 499 dev_err(adev->dev, "SPI cmd %x failed, fail status = %04x\n", 500 cmd, reg_status & 0xFFFF); 501 return -EIO; 502 } 503 504 return 0; 505 } 506 507 static int psp_v13_0_update_spirom(struct psp_context *psp, 508 uint64_t fw_pri_mc_addr) 509 { 510 struct amdgpu_device *adev = psp->adev; 511 int ret; 512 513 /* Confirm PSP is ready to start */ 514 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115), 515 MBOX_READY_FLAG, MBOX_READY_MASK, false); 516 if (ret) { 517 dev_err(adev->dev, "PSP Not ready to start processing, ret = %d", ret); 518 return ret; 519 } 520 521 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, lower_32_bits(fw_pri_mc_addr)); 522 523 ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_LO); 524 if (ret) 525 return ret; 526 527 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, upper_32_bits(fw_pri_mc_addr)); 528 529 ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI); 530 if (ret) 531 return ret; 532 533 psp->vbflash_done = true; 534 535 ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE); 536 if (ret) 537 return ret; 538 539 return 0; 540 } 541 542 static int psp_v13_0_vbflash_status(struct psp_context *psp) 543 { 544 struct amdgpu_device *adev = psp->adev; 545 546 return RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115); 547 } 548 549 static const struct psp_funcs psp_v13_0_funcs = { 550 .init_microcode = psp_v13_0_init_microcode, 551 .bootloader_load_kdb = psp_v13_0_bootloader_load_kdb, 552 .bootloader_load_spl = psp_v13_0_bootloader_load_spl, 553 .bootloader_load_sysdrv = psp_v13_0_bootloader_load_sysdrv, 554 .bootloader_load_soc_drv = psp_v13_0_bootloader_load_soc_drv, 555 .bootloader_load_intf_drv = psp_v13_0_bootloader_load_intf_drv, 556 .bootloader_load_dbg_drv = psp_v13_0_bootloader_load_dbg_drv, 557 .bootloader_load_sos = psp_v13_0_bootloader_load_sos, 558 .ring_init = psp_v13_0_ring_init, 559 .ring_create = psp_v13_0_ring_create, 560 .ring_stop = psp_v13_0_ring_stop, 561 .ring_destroy = psp_v13_0_ring_destroy, 562 .ring_get_wptr = psp_v13_0_ring_get_wptr, 563 .ring_set_wptr = psp_v13_0_ring_set_wptr, 564 .load_usbc_pd_fw = psp_v13_0_load_usbc_pd_fw, 565 .read_usbc_pd_fw = psp_v13_0_read_usbc_pd_fw, 566 .update_spirom = psp_v13_0_update_spirom, 567 .vbflash_stat = psp_v13_0_vbflash_status 568 }; 569 570 void psp_v13_0_set_psp_funcs(struct psp_context *psp) 571 { 572 psp->funcs = &psp_v13_0_funcs; 573 } 574