1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <drm/drm_drv.h> 24 #include <linux/vmalloc.h> 25 #include "amdgpu.h" 26 #include "amdgpu_psp.h" 27 #include "amdgpu_ucode.h" 28 #include "soc15_common.h" 29 #include "psp_v13_0.h" 30 #include "amdgpu_ras.h" 31 32 #include "mp/mp_13_0_2_offset.h" 33 #include "mp/mp_13_0_2_sh_mask.h" 34 35 MODULE_FIRMWARE("amdgpu/aldebaran_sos.bin"); 36 MODULE_FIRMWARE("amdgpu/aldebaran_ta.bin"); 37 MODULE_FIRMWARE("amdgpu/aldebaran_cap.bin"); 38 MODULE_FIRMWARE("amdgpu/yellow_carp_toc.bin"); 39 MODULE_FIRMWARE("amdgpu/yellow_carp_ta.bin"); 40 MODULE_FIRMWARE("amdgpu/psp_13_0_5_toc.bin"); 41 MODULE_FIRMWARE("amdgpu/psp_13_0_5_ta.bin"); 42 MODULE_FIRMWARE("amdgpu/psp_13_0_8_toc.bin"); 43 MODULE_FIRMWARE("amdgpu/psp_13_0_8_ta.bin"); 44 MODULE_FIRMWARE("amdgpu/psp_13_0_0_sos.bin"); 45 MODULE_FIRMWARE("amdgpu/psp_13_0_0_ta.bin"); 46 MODULE_FIRMWARE("amdgpu/psp_13_0_7_sos.bin"); 47 MODULE_FIRMWARE("amdgpu/psp_13_0_7_ta.bin"); 48 MODULE_FIRMWARE("amdgpu/psp_13_0_10_sos.bin"); 49 MODULE_FIRMWARE("amdgpu/psp_13_0_10_ta.bin"); 50 MODULE_FIRMWARE("amdgpu/psp_13_0_11_toc.bin"); 51 MODULE_FIRMWARE("amdgpu/psp_13_0_11_ta.bin"); 52 MODULE_FIRMWARE("amdgpu/psp_13_0_6_sos.bin"); 53 MODULE_FIRMWARE("amdgpu/psp_13_0_6_ta.bin"); 54 MODULE_FIRMWARE("amdgpu/psp_13_0_12_sos.bin"); 55 MODULE_FIRMWARE("amdgpu/psp_13_0_12_ta.bin"); 56 MODULE_FIRMWARE("amdgpu/psp_13_0_14_sos.bin"); 57 MODULE_FIRMWARE("amdgpu/psp_13_0_14_ta.bin"); 58 MODULE_FIRMWARE("amdgpu/psp_14_0_0_toc.bin"); 59 MODULE_FIRMWARE("amdgpu/psp_14_0_0_ta.bin"); 60 MODULE_FIRMWARE("amdgpu/psp_14_0_1_toc.bin"); 61 MODULE_FIRMWARE("amdgpu/psp_14_0_1_ta.bin"); 62 MODULE_FIRMWARE("amdgpu/psp_14_0_4_toc.bin"); 63 MODULE_FIRMWARE("amdgpu/psp_14_0_4_ta.bin"); 64 65 /* For large FW files the time to complete can be very long */ 66 #define USBC_PD_POLLING_LIMIT_S 240 67 68 /* Read USB-PD from LFB */ 69 #define GFX_CMD_USB_PD_USE_LFB 0x480 70 71 /* Retry times for vmbx ready wait */ 72 #define PSP_VMBX_POLLING_LIMIT 3000 73 74 /* VBIOS gfl defines */ 75 #define MBOX_READY_MASK 0x80000000 76 #define MBOX_STATUS_MASK 0x0000FFFF 77 #define MBOX_COMMAND_MASK 0x00FF0000 78 #define MBOX_READY_FLAG 0x80000000 79 #define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_LO 0x2 80 #define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI 0x3 81 #define C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE 0x4 82 83 /* memory training timeout define */ 84 #define MEM_TRAIN_SEND_MSG_TIMEOUT_US 3000000 85 86 #define regMP1_PUB_SCRATCH0 0x3b10090 87 88 #define PSP13_BL_STATUS_SIZE 100 89 90 static int psp_v13_0_init_microcode(struct psp_context *psp) 91 { 92 struct amdgpu_device *adev = psp->adev; 93 char ucode_prefix[30]; 94 int err = 0; 95 96 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); 97 98 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 99 case IP_VERSION(13, 0, 2): 100 err = psp_init_sos_microcode(psp, ucode_prefix); 101 if (err) 102 return err; 103 /* It's not necessary to load ras ta on Guest side */ 104 if (!amdgpu_sriov_vf(adev)) { 105 err = psp_init_ta_microcode(psp, ucode_prefix); 106 if (err) 107 return err; 108 } 109 break; 110 case IP_VERSION(13, 0, 1): 111 case IP_VERSION(13, 0, 3): 112 case IP_VERSION(13, 0, 5): 113 case IP_VERSION(13, 0, 8): 114 case IP_VERSION(13, 0, 11): 115 case IP_VERSION(14, 0, 0): 116 case IP_VERSION(14, 0, 1): 117 case IP_VERSION(14, 0, 4): 118 err = psp_init_toc_microcode(psp, ucode_prefix); 119 if (err) 120 return err; 121 err = psp_init_ta_microcode(psp, ucode_prefix); 122 if (err) 123 return err; 124 break; 125 case IP_VERSION(13, 0, 0): 126 case IP_VERSION(13, 0, 6): 127 case IP_VERSION(13, 0, 7): 128 case IP_VERSION(13, 0, 10): 129 case IP_VERSION(13, 0, 12): 130 case IP_VERSION(13, 0, 14): 131 err = psp_init_sos_microcode(psp, ucode_prefix); 132 if (err) 133 return err; 134 /* It's not necessary to load ras ta on Guest side */ 135 err = psp_init_ta_microcode(psp, ucode_prefix); 136 if (err) 137 return err; 138 break; 139 default: 140 BUG(); 141 } 142 143 return 0; 144 } 145 146 static bool psp_v13_0_is_sos_alive(struct psp_context *psp) 147 { 148 struct amdgpu_device *adev = psp->adev; 149 uint32_t sol_reg; 150 151 sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81); 152 153 return sol_reg != 0x0; 154 } 155 156 static void psp_v13_0_bootloader_print_status(struct psp_context *psp, 157 const char *msg) 158 { 159 struct amdgpu_device *adev = psp->adev; 160 u32 bl_status_reg; 161 char bl_status_msg[PSP13_BL_STATUS_SIZE]; 162 int i, at; 163 164 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) || 165 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 12) || 166 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14)) { 167 at = 0; 168 for_each_inst(i, adev->aid_mask) { 169 bl_status_reg = 170 (SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_92) 171 << 2) + 172 adev->asic_funcs->encode_ext_smn_addressing(i); 173 at += snprintf(bl_status_msg + at, 174 PSP13_BL_STATUS_SIZE - at, 175 " status(%02i): 0x%08x", i, 176 RREG32_PCIE_EXT(bl_status_reg)); 177 } 178 dev_info(adev->dev, "%s - %s", msg, bl_status_msg); 179 } 180 } 181 182 static int psp_v13_0_wait_for_vmbx_ready(struct psp_context *psp) 183 { 184 struct amdgpu_device *adev = psp->adev; 185 int retry_loop, ret; 186 187 for (retry_loop = 0; retry_loop < PSP_VMBX_POLLING_LIMIT; retry_loop++) { 188 /* Wait for bootloader to signify that is 189 ready having bit 31 of C2PMSG_33 set to 1 */ 190 ret = psp_wait_for( 191 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_33), 192 0x80000000, 0xffffffff, false); 193 194 if (ret == 0) 195 break; 196 } 197 198 if (ret) 199 dev_warn(adev->dev, "Bootloader wait timed out"); 200 201 return ret; 202 } 203 204 static int psp_v13_0_wait_for_bootloader(struct psp_context *psp) 205 { 206 struct amdgpu_device *adev = psp->adev; 207 int retry_loop, retry_cnt, ret; 208 209 retry_cnt = 210 ((amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) || 211 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 12) || 212 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14))) ? 213 PSP_VMBX_POLLING_LIMIT : 214 10; 215 /* Wait for bootloader to signify that it is ready having bit 31 of 216 * C2PMSG_35 set to 1. All other bits are expected to be cleared. 217 * If there is an error in processing command, bits[7:0] will be set. 218 * This is applicable for PSP v13.0.6 and newer. 219 */ 220 for (retry_loop = 0; retry_loop < retry_cnt; retry_loop++) { 221 ret = psp_wait_for( 222 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 223 0x80000000, 0xffffffff, false); 224 225 if (ret == 0) 226 return 0; 227 if (retry_loop && !(retry_loop % 10)) 228 psp_v13_0_bootloader_print_status( 229 psp, "Waiting for bootloader completion"); 230 } 231 232 return ret; 233 } 234 235 static int psp_v13_0_wait_for_bootloader_steady_state(struct psp_context *psp) 236 { 237 struct amdgpu_device *adev = psp->adev; 238 int ret; 239 240 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) || 241 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 12) || 242 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14)) { 243 ret = psp_v13_0_wait_for_vmbx_ready(psp); 244 if (ret) 245 amdgpu_ras_query_boot_status(adev, 4); 246 247 ret = psp_v13_0_wait_for_bootloader(psp); 248 if (ret) 249 amdgpu_ras_query_boot_status(adev, 4); 250 251 return ret; 252 } 253 254 return 0; 255 } 256 257 static int psp_v13_0_bootloader_load_component(struct psp_context *psp, 258 struct psp_bin_desc *bin_desc, 259 enum psp_bootloader_cmd bl_cmd) 260 { 261 int ret; 262 uint32_t psp_gfxdrv_command_reg = 0; 263 struct amdgpu_device *adev = psp->adev; 264 265 /* Check tOS sign of life register to confirm sys driver and sOS 266 * are already been loaded. 267 */ 268 if (psp_v13_0_is_sos_alive(psp)) 269 return 0; 270 271 ret = psp_v13_0_wait_for_bootloader(psp); 272 if (ret) 273 return ret; 274 275 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 276 277 /* Copy PSP KDB binary to memory */ 278 memcpy(psp->fw_pri_buf, bin_desc->start_addr, bin_desc->size_bytes); 279 280 /* Provide the PSP KDB to bootloader */ 281 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, 282 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 283 psp_gfxdrv_command_reg = bl_cmd; 284 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, 285 psp_gfxdrv_command_reg); 286 287 ret = psp_v13_0_wait_for_bootloader(psp); 288 289 return ret; 290 } 291 292 static int psp_v13_0_bootloader_load_kdb(struct psp_context *psp) 293 { 294 return psp_v13_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_KEY_DATABASE); 295 } 296 297 static int psp_v13_0_bootloader_load_spl(struct psp_context *psp) 298 { 299 return psp_v13_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_TOS_SPL_TABLE); 300 } 301 302 static int psp_v13_0_bootloader_load_sysdrv(struct psp_context *psp) 303 { 304 return psp_v13_0_bootloader_load_component(psp, &psp->sys, PSP_BL__LOAD_SYSDRV); 305 } 306 307 static int psp_v13_0_bootloader_load_soc_drv(struct psp_context *psp) 308 { 309 return psp_v13_0_bootloader_load_component(psp, &psp->soc_drv, PSP_BL__LOAD_SOCDRV); 310 } 311 312 static int psp_v13_0_bootloader_load_intf_drv(struct psp_context *psp) 313 { 314 return psp_v13_0_bootloader_load_component(psp, &psp->intf_drv, PSP_BL__LOAD_INTFDRV); 315 } 316 317 static int psp_v13_0_bootloader_load_dbg_drv(struct psp_context *psp) 318 { 319 return psp_v13_0_bootloader_load_component(psp, &psp->dbg_drv, PSP_BL__LOAD_DBGDRV); 320 } 321 322 static int psp_v13_0_bootloader_load_ras_drv(struct psp_context *psp) 323 { 324 return psp_v13_0_bootloader_load_component(psp, &psp->ras_drv, PSP_BL__LOAD_RASDRV); 325 } 326 327 static int psp_v13_0_bootloader_load_spdm_drv(struct psp_context *psp) 328 { 329 return psp_v13_0_bootloader_load_component(psp, &psp->spdm_drv, PSP_BL__LOAD_SPDMDRV); 330 } 331 332 static inline void psp_v13_0_init_sos_version(struct psp_context *psp) 333 { 334 struct amdgpu_device *adev = psp->adev; 335 336 psp->sos.fw_version = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_58); 337 } 338 339 static int psp_v13_0_bootloader_load_sos(struct psp_context *psp) 340 { 341 int ret; 342 unsigned int psp_gfxdrv_command_reg = 0; 343 struct amdgpu_device *adev = psp->adev; 344 345 /* Check sOS sign of life register to confirm sys driver and sOS 346 * are already been loaded. 347 */ 348 if (psp_v13_0_is_sos_alive(psp)) { 349 psp_v13_0_init_sos_version(psp); 350 return 0; 351 } 352 353 ret = psp_v13_0_wait_for_bootloader(psp); 354 if (ret) 355 return ret; 356 357 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 358 359 /* Copy Secure OS binary to PSP memory */ 360 memcpy(psp->fw_pri_buf, psp->sos.start_addr, psp->sos.size_bytes); 361 362 /* Provide the PSP secure OS to bootloader */ 363 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, 364 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 365 psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV; 366 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, 367 psp_gfxdrv_command_reg); 368 369 /* there might be handshake issue with hardware which needs delay */ 370 mdelay(20); 371 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_81), 372 RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81), 373 0, true); 374 375 if (!ret) 376 psp_v13_0_init_sos_version(psp); 377 378 return ret; 379 } 380 381 static int psp_v13_0_ring_stop(struct psp_context *psp, 382 enum psp_ring_type ring_type) 383 { 384 int ret = 0; 385 struct amdgpu_device *adev = psp->adev; 386 387 if (amdgpu_sriov_vf(adev)) { 388 /* Write the ring destroy command*/ 389 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, 390 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING); 391 /* there might be handshake issue with hardware which needs delay */ 392 mdelay(20); 393 /* Wait for response flag (bit 31) */ 394 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101), 395 0x80000000, 0x80000000, false); 396 } else { 397 /* Write the ring destroy command*/ 398 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, 399 GFX_CTRL_CMD_ID_DESTROY_RINGS); 400 /* there might be handshake issue with hardware which needs delay */ 401 mdelay(20); 402 /* Wait for response flag (bit 31) */ 403 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), 404 0x80000000, 0x80000000, false); 405 } 406 407 return ret; 408 } 409 410 static int psp_v13_0_ring_create(struct psp_context *psp, 411 enum psp_ring_type ring_type) 412 { 413 int ret = 0; 414 unsigned int psp_ring_reg = 0; 415 struct psp_ring *ring = &psp->km_ring; 416 struct amdgpu_device *adev = psp->adev; 417 418 if (amdgpu_sriov_vf(adev)) { 419 ret = psp_v13_0_ring_stop(psp, ring_type); 420 if (ret) { 421 DRM_ERROR("psp_v13_0_ring_stop_sriov failed!\n"); 422 return ret; 423 } 424 425 /* Write low address of the ring to C2PMSG_102 */ 426 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 427 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, psp_ring_reg); 428 /* Write high address of the ring to C2PMSG_103 */ 429 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 430 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_103, psp_ring_reg); 431 432 /* Write the ring initialization command to C2PMSG_101 */ 433 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, 434 GFX_CTRL_CMD_ID_INIT_GPCOM_RING); 435 436 /* there might be handshake issue with hardware which needs delay */ 437 mdelay(20); 438 439 /* Wait for response flag (bit 31) in C2PMSG_101 */ 440 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101), 441 0x80000000, 0x8000FFFF, false); 442 443 } else { 444 /* Wait for sOS ready for ring creation */ 445 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), 446 0x80000000, 0x80000000, false); 447 if (ret) { 448 DRM_ERROR("Failed to wait for trust OS ready for ring creation\n"); 449 return ret; 450 } 451 452 /* Write low address of the ring to C2PMSG_69 */ 453 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 454 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_69, psp_ring_reg); 455 /* Write high address of the ring to C2PMSG_70 */ 456 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 457 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_70, psp_ring_reg); 458 /* Write size of ring to C2PMSG_71 */ 459 psp_ring_reg = ring->ring_size; 460 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_71, psp_ring_reg); 461 /* Write the ring initialization command to C2PMSG_64 */ 462 psp_ring_reg = ring_type; 463 psp_ring_reg = psp_ring_reg << 16; 464 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, psp_ring_reg); 465 466 /* there might be handshake issue with hardware which needs delay */ 467 mdelay(20); 468 469 /* Wait for response flag (bit 31) in C2PMSG_64 */ 470 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), 471 0x80000000, 0x8000FFFF, false); 472 } 473 474 return ret; 475 } 476 477 static int psp_v13_0_ring_destroy(struct psp_context *psp, 478 enum psp_ring_type ring_type) 479 { 480 int ret = 0; 481 struct psp_ring *ring = &psp->km_ring; 482 struct amdgpu_device *adev = psp->adev; 483 484 ret = psp_v13_0_ring_stop(psp, ring_type); 485 if (ret) 486 DRM_ERROR("Fail to stop psp ring\n"); 487 488 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 489 &ring->ring_mem_mc_addr, 490 (void **)&ring->ring_mem); 491 492 return ret; 493 } 494 495 static uint32_t psp_v13_0_ring_get_wptr(struct psp_context *psp) 496 { 497 uint32_t data; 498 struct amdgpu_device *adev = psp->adev; 499 500 if (amdgpu_sriov_vf(adev)) 501 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102); 502 else 503 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67); 504 505 return data; 506 } 507 508 static void psp_v13_0_ring_set_wptr(struct psp_context *psp, uint32_t value) 509 { 510 struct amdgpu_device *adev = psp->adev; 511 512 if (amdgpu_sriov_vf(adev)) { 513 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, value); 514 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, 515 GFX_CTRL_CMD_ID_CONSUME_CMD); 516 } else 517 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67, value); 518 } 519 520 static int psp_v13_0_memory_training_send_msg(struct psp_context *psp, int msg) 521 { 522 int ret; 523 int i; 524 uint32_t data_32; 525 int max_wait; 526 struct amdgpu_device *adev = psp->adev; 527 528 data_32 = (psp->mem_train_ctx.c2p_train_data_offset >> 20); 529 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, data_32); 530 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, msg); 531 532 max_wait = MEM_TRAIN_SEND_MSG_TIMEOUT_US / adev->usec_timeout; 533 for (i = 0; i < max_wait; i++) { 534 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 535 0x80000000, 0x80000000, false); 536 if (ret == 0) 537 break; 538 } 539 if (i < max_wait) 540 ret = 0; 541 else 542 ret = -ETIME; 543 544 dev_dbg(adev->dev, "training %s %s, cost %d @ %d ms\n", 545 (msg == PSP_BL__DRAM_SHORT_TRAIN) ? "short" : "long", 546 (ret == 0) ? "succeed" : "failed", 547 i, adev->usec_timeout/1000); 548 return ret; 549 } 550 551 552 static int psp_v13_0_memory_training(struct psp_context *psp, uint32_t ops) 553 { 554 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 555 uint32_t *pcache = (uint32_t *)ctx->sys_cache; 556 struct amdgpu_device *adev = psp->adev; 557 uint32_t p2c_header[4]; 558 uint32_t sz; 559 void *buf; 560 int ret, idx; 561 562 if (ctx->init == PSP_MEM_TRAIN_NOT_SUPPORT) { 563 dev_dbg(adev->dev, "Memory training is not supported.\n"); 564 return 0; 565 } else if (ctx->init != PSP_MEM_TRAIN_INIT_SUCCESS) { 566 dev_err(adev->dev, "Memory training initialization failure.\n"); 567 return -EINVAL; 568 } 569 570 if (psp_v13_0_is_sos_alive(psp)) { 571 dev_dbg(adev->dev, "SOS is alive, skip memory training.\n"); 572 return 0; 573 } 574 575 amdgpu_device_vram_access(adev, ctx->p2c_train_data_offset, p2c_header, sizeof(p2c_header), false); 576 dev_dbg(adev->dev, "sys_cache[%08x,%08x,%08x,%08x] p2c_header[%08x,%08x,%08x,%08x]\n", 577 pcache[0], pcache[1], pcache[2], pcache[3], 578 p2c_header[0], p2c_header[1], p2c_header[2], p2c_header[3]); 579 580 if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) { 581 dev_dbg(adev->dev, "Short training depends on restore.\n"); 582 ops |= PSP_MEM_TRAIN_RESTORE; 583 } 584 585 if ((ops & PSP_MEM_TRAIN_RESTORE) && 586 pcache[0] != MEM_TRAIN_SYSTEM_SIGNATURE) { 587 dev_dbg(adev->dev, "sys_cache[0] is invalid, restore depends on save.\n"); 588 ops |= PSP_MEM_TRAIN_SAVE; 589 } 590 591 if (p2c_header[0] == MEM_TRAIN_SYSTEM_SIGNATURE && 592 !(pcache[0] == MEM_TRAIN_SYSTEM_SIGNATURE && 593 pcache[3] == p2c_header[3])) { 594 dev_dbg(adev->dev, "sys_cache is invalid or out-of-date, need save training data to sys_cache.\n"); 595 ops |= PSP_MEM_TRAIN_SAVE; 596 } 597 598 if ((ops & PSP_MEM_TRAIN_SAVE) && 599 p2c_header[0] != MEM_TRAIN_SYSTEM_SIGNATURE) { 600 dev_dbg(adev->dev, "p2c_header[0] is invalid, save depends on long training.\n"); 601 ops |= PSP_MEM_TRAIN_SEND_LONG_MSG; 602 } 603 604 if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) { 605 ops &= ~PSP_MEM_TRAIN_SEND_SHORT_MSG; 606 ops |= PSP_MEM_TRAIN_SAVE; 607 } 608 609 dev_dbg(adev->dev, "Memory training ops:%x.\n", ops); 610 611 if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) { 612 /* 613 * Long training will encroach a certain amount on the bottom of VRAM; 614 * save the content from the bottom of VRAM to system memory 615 * before training, and restore it after training to avoid 616 * VRAM corruption. 617 */ 618 sz = BIST_MEM_TRAINING_ENCROACHED_SIZE; 619 620 if (adev->gmc.visible_vram_size < sz || !adev->mman.aper_base_kaddr) { 621 dev_err(adev->dev, "visible_vram_size %llx or aper_base_kaddr %p is not initialized.\n", 622 adev->gmc.visible_vram_size, 623 adev->mman.aper_base_kaddr); 624 return -EINVAL; 625 } 626 627 buf = vmalloc(sz); 628 if (!buf) { 629 dev_err(adev->dev, "failed to allocate system memory.\n"); 630 return -ENOMEM; 631 } 632 633 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 634 memcpy_fromio(buf, adev->mman.aper_base_kaddr, sz); 635 ret = psp_v13_0_memory_training_send_msg(psp, PSP_BL__DRAM_LONG_TRAIN); 636 if (ret) { 637 DRM_ERROR("Send long training msg failed.\n"); 638 vfree(buf); 639 drm_dev_exit(idx); 640 return ret; 641 } 642 643 memcpy_toio(adev->mman.aper_base_kaddr, buf, sz); 644 amdgpu_device_flush_hdp(adev, NULL); 645 vfree(buf); 646 drm_dev_exit(idx); 647 } else { 648 vfree(buf); 649 return -ENODEV; 650 } 651 } 652 653 if (ops & PSP_MEM_TRAIN_SAVE) { 654 amdgpu_device_vram_access(psp->adev, ctx->p2c_train_data_offset, ctx->sys_cache, ctx->train_data_size, false); 655 } 656 657 if (ops & PSP_MEM_TRAIN_RESTORE) { 658 amdgpu_device_vram_access(psp->adev, ctx->c2p_train_data_offset, ctx->sys_cache, ctx->train_data_size, true); 659 } 660 661 if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) { 662 ret = psp_v13_0_memory_training_send_msg(psp, (amdgpu_force_long_training > 0) ? 663 PSP_BL__DRAM_LONG_TRAIN : PSP_BL__DRAM_SHORT_TRAIN); 664 if (ret) { 665 dev_err(adev->dev, "send training msg failed.\n"); 666 return ret; 667 } 668 } 669 ctx->training_cnt++; 670 return 0; 671 } 672 673 static int psp_v13_0_load_usbc_pd_fw(struct psp_context *psp, uint64_t fw_pri_mc_addr) 674 { 675 struct amdgpu_device *adev = psp->adev; 676 uint32_t reg_status; 677 int ret, i = 0; 678 679 /* 680 * LFB address which is aligned to 1MB address and has to be 681 * right-shifted by 20 so that LFB address can be passed on a 32-bit C2P 682 * register 683 */ 684 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, (fw_pri_mc_addr >> 20)); 685 686 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 687 0x80000000, 0x80000000, false); 688 if (ret) 689 return ret; 690 691 /* Fireup interrupt so PSP can pick up the address */ 692 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, (GFX_CMD_USB_PD_USE_LFB << 16)); 693 694 /* FW load takes very long time */ 695 do { 696 msleep(1000); 697 reg_status = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35); 698 699 if (reg_status & 0x80000000) 700 goto done; 701 702 } while (++i < USBC_PD_POLLING_LIMIT_S); 703 704 return -ETIME; 705 done: 706 707 if ((reg_status & 0xFFFF) != 0) { 708 DRM_ERROR("Address load failed - MP0_SMN_C2PMSG_35.Bits [15:0] = %04x\n", 709 reg_status & 0xFFFF); 710 return -EIO; 711 } 712 713 return 0; 714 } 715 716 static int psp_v13_0_read_usbc_pd_fw(struct psp_context *psp, uint32_t *fw_ver) 717 { 718 struct amdgpu_device *adev = psp->adev; 719 int ret; 720 721 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, C2PMSG_CMD_GFX_USB_PD_FW_VER); 722 723 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 724 0x80000000, 0x80000000, false); 725 if (!ret) 726 *fw_ver = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36); 727 728 return ret; 729 } 730 731 static int psp_v13_0_exec_spi_cmd(struct psp_context *psp, int cmd) 732 { 733 uint32_t reg_status = 0, reg_val = 0; 734 struct amdgpu_device *adev = psp->adev; 735 int ret; 736 737 /* clear MBX ready (MBOX_READY_MASK bit is 0) and set update command */ 738 reg_val |= (cmd << 16); 739 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115, reg_val); 740 741 /* Ring the doorbell */ 742 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_73, 1); 743 744 if (cmd == C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE) 745 ret = psp_wait_for_spirom_update(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115), 746 MBOX_READY_FLAG, MBOX_READY_MASK, PSP_SPIROM_UPDATE_TIMEOUT); 747 else 748 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115), 749 MBOX_READY_FLAG, MBOX_READY_MASK, false); 750 if (ret) { 751 dev_err(adev->dev, "SPI cmd %x timed out, ret = %d", cmd, ret); 752 return ret; 753 } 754 755 reg_status = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115); 756 if ((reg_status & 0xFFFF) != 0) { 757 dev_err(adev->dev, "SPI cmd %x failed, fail status = %04x\n", 758 cmd, reg_status & 0xFFFF); 759 return -EIO; 760 } 761 762 return 0; 763 } 764 765 static int psp_v13_0_update_spirom(struct psp_context *psp, 766 uint64_t fw_pri_mc_addr) 767 { 768 struct amdgpu_device *adev = psp->adev; 769 int ret; 770 771 /* Confirm PSP is ready to start */ 772 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115), 773 MBOX_READY_FLAG, MBOX_READY_MASK, false); 774 if (ret) { 775 dev_err(adev->dev, "PSP Not ready to start processing, ret = %d", ret); 776 return ret; 777 } 778 779 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, lower_32_bits(fw_pri_mc_addr)); 780 781 ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_LO); 782 if (ret) 783 return ret; 784 785 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, upper_32_bits(fw_pri_mc_addr)); 786 787 ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI); 788 if (ret) 789 return ret; 790 791 psp->vbflash_done = true; 792 793 ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE); 794 if (ret) 795 return ret; 796 797 return 0; 798 } 799 800 static int psp_v13_0_vbflash_status(struct psp_context *psp) 801 { 802 struct amdgpu_device *adev = psp->adev; 803 804 return RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115); 805 } 806 807 static int psp_v13_0_fatal_error_recovery_quirk(struct psp_context *psp) 808 { 809 struct amdgpu_device *adev = psp->adev; 810 811 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 10)) { 812 uint32_t reg_data; 813 /* MP1 fatal error: trigger PSP dram read to unhalt PSP 814 * during MP1 triggered sync flood. 815 */ 816 reg_data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67); 817 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67, reg_data + 0x10); 818 819 /* delay 1000ms for the mode1 reset for fatal error 820 * to be recovered back. 821 */ 822 msleep(1000); 823 } 824 825 return 0; 826 } 827 828 static bool psp_v13_0_get_ras_capability(struct psp_context *psp) 829 { 830 struct amdgpu_device *adev = psp->adev; 831 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 832 u32 reg_data; 833 834 /* query ras cap should be done from host side */ 835 if (amdgpu_sriov_vf(adev)) 836 return false; 837 838 if (!con) 839 return false; 840 841 if ((amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) || 842 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 12) || 843 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14)) && 844 (!(adev->flags & AMD_IS_APU))) { 845 reg_data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_127); 846 adev->ras_hw_enabled = (reg_data & GENMASK_ULL(23, 0)); 847 con->poison_supported = ((reg_data & GENMASK_ULL(24, 24)) >> 24) ? true : false; 848 return true; 849 } else { 850 return false; 851 } 852 } 853 854 static bool psp_v13_0_is_aux_sos_load_required(struct psp_context *psp) 855 { 856 struct amdgpu_device *adev = psp->adev; 857 u32 pmfw_ver; 858 859 if (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 6)) 860 return false; 861 862 /* load 4e version of sos if pmfw version less than 85.115.0 */ 863 pmfw_ver = RREG32(regMP1_PUB_SCRATCH0 / 4); 864 865 return (pmfw_ver < 0x557300); 866 } 867 868 static bool psp_v13_0_is_reload_needed(struct psp_context *psp) 869 { 870 uint32_t ucode_ver; 871 872 if (!psp_v13_0_is_sos_alive(psp)) 873 return false; 874 875 /* Restrict reload support only to specific IP versions */ 876 switch (amdgpu_ip_version(psp->adev, MP0_HWIP, 0)) { 877 case IP_VERSION(13, 0, 2): 878 case IP_VERSION(13, 0, 6): 879 case IP_VERSION(13, 0, 14): 880 /* TOS version read from microcode header */ 881 ucode_ver = psp->sos.fw_version; 882 /* Read TOS version from hardware */ 883 psp_v13_0_init_sos_version(psp); 884 return (ucode_ver != psp->sos.fw_version); 885 default: 886 return false; 887 } 888 889 return false; 890 } 891 892 static int psp_v13_0_reg_program_no_ring(struct psp_context *psp, uint32_t val, 893 enum psp_reg_prog_id id) 894 { 895 struct amdgpu_device *adev = psp->adev; 896 int ret = -EOPNOTSUPP; 897 898 /* PSP will broadcast the value to all instances */ 899 if (amdgpu_sriov_vf(adev)) { 900 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_GBR_IH_SET); 901 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, id); 902 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_103, val); 903 904 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101), 905 0x80000000, 0x80000000, false); 906 } 907 908 return ret; 909 } 910 911 static const struct psp_funcs psp_v13_0_funcs = { 912 .init_microcode = psp_v13_0_init_microcode, 913 .wait_for_bootloader = psp_v13_0_wait_for_bootloader_steady_state, 914 .bootloader_load_kdb = psp_v13_0_bootloader_load_kdb, 915 .bootloader_load_spl = psp_v13_0_bootloader_load_spl, 916 .bootloader_load_sysdrv = psp_v13_0_bootloader_load_sysdrv, 917 .bootloader_load_soc_drv = psp_v13_0_bootloader_load_soc_drv, 918 .bootloader_load_intf_drv = psp_v13_0_bootloader_load_intf_drv, 919 .bootloader_load_dbg_drv = psp_v13_0_bootloader_load_dbg_drv, 920 .bootloader_load_ras_drv = psp_v13_0_bootloader_load_ras_drv, 921 .bootloader_load_spdm_drv = psp_v13_0_bootloader_load_spdm_drv, 922 .bootloader_load_sos = psp_v13_0_bootloader_load_sos, 923 .ring_create = psp_v13_0_ring_create, 924 .ring_stop = psp_v13_0_ring_stop, 925 .ring_destroy = psp_v13_0_ring_destroy, 926 .ring_get_wptr = psp_v13_0_ring_get_wptr, 927 .ring_set_wptr = psp_v13_0_ring_set_wptr, 928 .mem_training = psp_v13_0_memory_training, 929 .load_usbc_pd_fw = psp_v13_0_load_usbc_pd_fw, 930 .read_usbc_pd_fw = psp_v13_0_read_usbc_pd_fw, 931 .update_spirom = psp_v13_0_update_spirom, 932 .vbflash_stat = psp_v13_0_vbflash_status, 933 .fatal_error_recovery_quirk = psp_v13_0_fatal_error_recovery_quirk, 934 .get_ras_capability = psp_v13_0_get_ras_capability, 935 .is_aux_sos_load_required = psp_v13_0_is_aux_sos_load_required, 936 .is_reload_needed = psp_v13_0_is_reload_needed, 937 .reg_program_no_ring = psp_v13_0_reg_program_no_ring, 938 }; 939 940 void psp_v13_0_set_psp_funcs(struct psp_context *psp) 941 { 942 psp->funcs = &psp_v13_0_funcs; 943 } 944