1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "amdgpu.h" 24 #include "amdgpu_psp.h" 25 #include "amdgpu_ucode.h" 26 #include "soc15_common.h" 27 #include "psp_v13_0.h" 28 29 #include "mp/mp_13_0_2_offset.h" 30 #include "mp/mp_13_0_2_sh_mask.h" 31 32 MODULE_FIRMWARE("amdgpu/aldebaran_sos.bin"); 33 MODULE_FIRMWARE("amdgpu/aldebaran_ta.bin"); 34 MODULE_FIRMWARE("amdgpu/aldebaran_cap.bin"); 35 MODULE_FIRMWARE("amdgpu/yellow_carp_asd.bin"); 36 MODULE_FIRMWARE("amdgpu/yellow_carp_toc.bin"); 37 MODULE_FIRMWARE("amdgpu/yellow_carp_ta.bin"); 38 MODULE_FIRMWARE("amdgpu/psp_13_0_5_asd.bin"); 39 MODULE_FIRMWARE("amdgpu/psp_13_0_5_toc.bin"); 40 MODULE_FIRMWARE("amdgpu/psp_13_0_5_ta.bin"); 41 MODULE_FIRMWARE("amdgpu/psp_13_0_8_asd.bin"); 42 MODULE_FIRMWARE("amdgpu/psp_13_0_8_toc.bin"); 43 MODULE_FIRMWARE("amdgpu/psp_13_0_8_ta.bin"); 44 MODULE_FIRMWARE("amdgpu/psp_13_0_0_sos.bin"); 45 MODULE_FIRMWARE("amdgpu/psp_13_0_7_sos.bin"); 46 47 /* For large FW files the time to complete can be very long */ 48 #define USBC_PD_POLLING_LIMIT_S 240 49 50 /* Read USB-PD from LFB */ 51 #define GFX_CMD_USB_PD_USE_LFB 0x480 52 53 static int psp_v13_0_init_microcode(struct psp_context *psp) 54 { 55 struct amdgpu_device *adev = psp->adev; 56 const char *chip_name; 57 char ucode_prefix[30]; 58 int err = 0; 59 60 switch (adev->ip_versions[MP0_HWIP][0]) { 61 case IP_VERSION(13, 0, 2): 62 chip_name = "aldebaran"; 63 break; 64 case IP_VERSION(13, 0, 1): 65 case IP_VERSION(13, 0, 3): 66 chip_name = "yellow_carp"; 67 break; 68 default: 69 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); 70 chip_name = ucode_prefix; 71 break; 72 } 73 74 switch (adev->ip_versions[MP0_HWIP][0]) { 75 case IP_VERSION(13, 0, 2): 76 err = psp_init_sos_microcode(psp, chip_name); 77 if (err) 78 return err; 79 err = psp_init_ta_microcode(&adev->psp, chip_name); 80 if (err) 81 return err; 82 break; 83 case IP_VERSION(13, 0, 1): 84 case IP_VERSION(13, 0, 3): 85 case IP_VERSION(13, 0, 5): 86 case IP_VERSION(13, 0, 8): 87 err = psp_init_asd_microcode(psp, chip_name); 88 if (err) 89 return err; 90 err = psp_init_toc_microcode(psp, chip_name); 91 if (err) 92 return err; 93 err = psp_init_ta_microcode(psp, chip_name); 94 if (err) 95 return err; 96 break; 97 case IP_VERSION(13, 0, 0): 98 case IP_VERSION(13, 0, 7): 99 err = psp_init_sos_microcode(psp, chip_name); 100 if (err) 101 return err; 102 break; 103 default: 104 BUG(); 105 } 106 107 return 0; 108 } 109 110 static bool psp_v13_0_is_sos_alive(struct psp_context *psp) 111 { 112 struct amdgpu_device *adev = psp->adev; 113 uint32_t sol_reg; 114 115 sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81); 116 117 return sol_reg != 0x0; 118 } 119 120 static int psp_v13_0_wait_for_bootloader(struct psp_context *psp) 121 { 122 struct amdgpu_device *adev = psp->adev; 123 124 int ret; 125 int retry_loop; 126 127 for (retry_loop = 0; retry_loop < 10; retry_loop++) { 128 /* Wait for bootloader to signify that is 129 ready having bit 31 of C2PMSG_35 set to 1 */ 130 ret = psp_wait_for(psp, 131 SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 132 0x80000000, 133 0x80000000, 134 false); 135 136 if (ret == 0) 137 return 0; 138 } 139 140 return ret; 141 } 142 143 static int psp_v13_0_bootloader_load_component(struct psp_context *psp, 144 struct psp_bin_desc *bin_desc, 145 enum psp_bootloader_cmd bl_cmd) 146 { 147 int ret; 148 uint32_t psp_gfxdrv_command_reg = 0; 149 struct amdgpu_device *adev = psp->adev; 150 151 /* Check tOS sign of life register to confirm sys driver and sOS 152 * are already been loaded. 153 */ 154 if (psp_v13_0_is_sos_alive(psp)) 155 return 0; 156 157 ret = psp_v13_0_wait_for_bootloader(psp); 158 if (ret) 159 return ret; 160 161 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 162 163 /* Copy PSP KDB binary to memory */ 164 memcpy(psp->fw_pri_buf, bin_desc->start_addr, bin_desc->size_bytes); 165 166 /* Provide the PSP KDB to bootloader */ 167 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, 168 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 169 psp_gfxdrv_command_reg = bl_cmd; 170 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, 171 psp_gfxdrv_command_reg); 172 173 ret = psp_v13_0_wait_for_bootloader(psp); 174 175 return ret; 176 } 177 178 static int psp_v13_0_bootloader_load_kdb(struct psp_context *psp) 179 { 180 return psp_v13_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_KEY_DATABASE); 181 } 182 183 static int psp_v13_0_bootloader_load_spl(struct psp_context *psp) 184 { 185 return psp_v13_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_TOS_SPL_TABLE); 186 } 187 188 static int psp_v13_0_bootloader_load_sysdrv(struct psp_context *psp) 189 { 190 return psp_v13_0_bootloader_load_component(psp, &psp->sys, PSP_BL__LOAD_SYSDRV); 191 } 192 193 static int psp_v13_0_bootloader_load_soc_drv(struct psp_context *psp) 194 { 195 return psp_v13_0_bootloader_load_component(psp, &psp->soc_drv, PSP_BL__LOAD_SOCDRV); 196 } 197 198 static int psp_v13_0_bootloader_load_intf_drv(struct psp_context *psp) 199 { 200 return psp_v13_0_bootloader_load_component(psp, &psp->intf_drv, PSP_BL__LOAD_INTFDRV); 201 } 202 203 static int psp_v13_0_bootloader_load_dbg_drv(struct psp_context *psp) 204 { 205 return psp_v13_0_bootloader_load_component(psp, &psp->dbg_drv, PSP_BL__LOAD_DBGDRV); 206 } 207 208 static int psp_v13_0_bootloader_load_sos(struct psp_context *psp) 209 { 210 int ret; 211 unsigned int psp_gfxdrv_command_reg = 0; 212 struct amdgpu_device *adev = psp->adev; 213 214 /* Check sOS sign of life register to confirm sys driver and sOS 215 * are already been loaded. 216 */ 217 if (psp_v13_0_is_sos_alive(psp)) 218 return 0; 219 220 ret = psp_v13_0_wait_for_bootloader(psp); 221 if (ret) 222 return ret; 223 224 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 225 226 /* Copy Secure OS binary to PSP memory */ 227 memcpy(psp->fw_pri_buf, psp->sos.start_addr, psp->sos.size_bytes); 228 229 /* Provide the PSP secure OS to bootloader */ 230 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, 231 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 232 psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV; 233 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, 234 psp_gfxdrv_command_reg); 235 236 /* there might be handshake issue with hardware which needs delay */ 237 mdelay(20); 238 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_81), 239 RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81), 240 0, true); 241 242 return ret; 243 } 244 245 static int psp_v13_0_ring_init(struct psp_context *psp, 246 enum psp_ring_type ring_type) 247 { 248 int ret = 0; 249 struct psp_ring *ring; 250 struct amdgpu_device *adev = psp->adev; 251 252 ring = &psp->km_ring; 253 254 ring->ring_type = ring_type; 255 256 /* allocate 4k Page of Local Frame Buffer memory for ring */ 257 ring->ring_size = 0x1000; 258 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE, 259 AMDGPU_GEM_DOMAIN_VRAM, 260 &adev->firmware.rbuf, 261 &ring->ring_mem_mc_addr, 262 (void **)&ring->ring_mem); 263 if (ret) { 264 ring->ring_size = 0; 265 return ret; 266 } 267 268 return 0; 269 } 270 271 static int psp_v13_0_ring_stop(struct psp_context *psp, 272 enum psp_ring_type ring_type) 273 { 274 int ret = 0; 275 struct amdgpu_device *adev = psp->adev; 276 277 if (amdgpu_sriov_vf(adev)) { 278 /* Write the ring destroy command*/ 279 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, 280 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING); 281 /* there might be handshake issue with hardware which needs delay */ 282 mdelay(20); 283 /* Wait for response flag (bit 31) */ 284 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101), 285 0x80000000, 0x80000000, false); 286 } else { 287 /* Write the ring destroy command*/ 288 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, 289 GFX_CTRL_CMD_ID_DESTROY_RINGS); 290 /* there might be handshake issue with hardware which needs delay */ 291 mdelay(20); 292 /* Wait for response flag (bit 31) */ 293 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), 294 0x80000000, 0x80000000, false); 295 } 296 297 return ret; 298 } 299 300 static int psp_v13_0_ring_create(struct psp_context *psp, 301 enum psp_ring_type ring_type) 302 { 303 int ret = 0; 304 unsigned int psp_ring_reg = 0; 305 struct psp_ring *ring = &psp->km_ring; 306 struct amdgpu_device *adev = psp->adev; 307 308 if (amdgpu_sriov_vf(adev)) { 309 ret = psp_v13_0_ring_stop(psp, ring_type); 310 if (ret) { 311 DRM_ERROR("psp_v13_0_ring_stop_sriov failed!\n"); 312 return ret; 313 } 314 315 /* Write low address of the ring to C2PMSG_102 */ 316 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 317 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, psp_ring_reg); 318 /* Write high address of the ring to C2PMSG_103 */ 319 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 320 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_103, psp_ring_reg); 321 322 /* Write the ring initialization command to C2PMSG_101 */ 323 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, 324 GFX_CTRL_CMD_ID_INIT_GPCOM_RING); 325 326 /* there might be handshake issue with hardware which needs delay */ 327 mdelay(20); 328 329 /* Wait for response flag (bit 31) in C2PMSG_101 */ 330 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101), 331 0x80000000, 0x8000FFFF, false); 332 333 } else { 334 /* Wait for sOS ready for ring creation */ 335 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), 336 0x80000000, 0x80000000, false); 337 if (ret) { 338 DRM_ERROR("Failed to wait for trust OS ready for ring creation\n"); 339 return ret; 340 } 341 342 /* Write low address of the ring to C2PMSG_69 */ 343 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 344 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_69, psp_ring_reg); 345 /* Write high address of the ring to C2PMSG_70 */ 346 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 347 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_70, psp_ring_reg); 348 /* Write size of ring to C2PMSG_71 */ 349 psp_ring_reg = ring->ring_size; 350 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_71, psp_ring_reg); 351 /* Write the ring initialization command to C2PMSG_64 */ 352 psp_ring_reg = ring_type; 353 psp_ring_reg = psp_ring_reg << 16; 354 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, psp_ring_reg); 355 356 /* there might be handshake issue with hardware which needs delay */ 357 mdelay(20); 358 359 /* Wait for response flag (bit 31) in C2PMSG_64 */ 360 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), 361 0x80000000, 0x8000FFFF, false); 362 } 363 364 return ret; 365 } 366 367 static int psp_v13_0_ring_destroy(struct psp_context *psp, 368 enum psp_ring_type ring_type) 369 { 370 int ret = 0; 371 struct psp_ring *ring = &psp->km_ring; 372 struct amdgpu_device *adev = psp->adev; 373 374 ret = psp_v13_0_ring_stop(psp, ring_type); 375 if (ret) 376 DRM_ERROR("Fail to stop psp ring\n"); 377 378 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 379 &ring->ring_mem_mc_addr, 380 (void **)&ring->ring_mem); 381 382 return ret; 383 } 384 385 static uint32_t psp_v13_0_ring_get_wptr(struct psp_context *psp) 386 { 387 uint32_t data; 388 struct amdgpu_device *adev = psp->adev; 389 390 if (amdgpu_sriov_vf(adev)) 391 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102); 392 else 393 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67); 394 395 return data; 396 } 397 398 static void psp_v13_0_ring_set_wptr(struct psp_context *psp, uint32_t value) 399 { 400 struct amdgpu_device *adev = psp->adev; 401 402 if (amdgpu_sriov_vf(adev)) { 403 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, value); 404 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, 405 GFX_CTRL_CMD_ID_CONSUME_CMD); 406 } else 407 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67, value); 408 } 409 410 static int psp_v13_0_load_usbc_pd_fw(struct psp_context *psp, uint64_t fw_pri_mc_addr) 411 { 412 struct amdgpu_device *adev = psp->adev; 413 uint32_t reg_status; 414 int ret, i = 0; 415 416 /* 417 * LFB address which is aligned to 1MB address and has to be 418 * right-shifted by 20 so that LFB address can be passed on a 32-bit C2P 419 * register 420 */ 421 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, (fw_pri_mc_addr >> 20)); 422 423 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 424 0x80000000, 0x80000000, false); 425 if (ret) 426 return ret; 427 428 /* Fireup interrupt so PSP can pick up the address */ 429 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, (GFX_CMD_USB_PD_USE_LFB << 16)); 430 431 /* FW load takes very long time */ 432 do { 433 msleep(1000); 434 reg_status = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35); 435 436 if (reg_status & 0x80000000) 437 goto done; 438 439 } while (++i < USBC_PD_POLLING_LIMIT_S); 440 441 return -ETIME; 442 done: 443 444 if ((reg_status & 0xFFFF) != 0) { 445 DRM_ERROR("Address load failed - MP0_SMN_C2PMSG_35.Bits [15:0] = %04x\n", 446 reg_status & 0xFFFF); 447 return -EIO; 448 } 449 450 return 0; 451 } 452 453 static int psp_v13_0_read_usbc_pd_fw(struct psp_context *psp, uint32_t *fw_ver) 454 { 455 struct amdgpu_device *adev = psp->adev; 456 int ret; 457 458 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, C2PMSG_CMD_GFX_USB_PD_FW_VER); 459 460 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 461 0x80000000, 0x80000000, false); 462 if (!ret) 463 *fw_ver = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36); 464 465 return ret; 466 } 467 468 static const struct psp_funcs psp_v13_0_funcs = { 469 .init_microcode = psp_v13_0_init_microcode, 470 .bootloader_load_kdb = psp_v13_0_bootloader_load_kdb, 471 .bootloader_load_spl = psp_v13_0_bootloader_load_spl, 472 .bootloader_load_sysdrv = psp_v13_0_bootloader_load_sysdrv, 473 .bootloader_load_soc_drv = psp_v13_0_bootloader_load_soc_drv, 474 .bootloader_load_intf_drv = psp_v13_0_bootloader_load_intf_drv, 475 .bootloader_load_dbg_drv = psp_v13_0_bootloader_load_dbg_drv, 476 .bootloader_load_sos = psp_v13_0_bootloader_load_sos, 477 .ring_init = psp_v13_0_ring_init, 478 .ring_create = psp_v13_0_ring_create, 479 .ring_stop = psp_v13_0_ring_stop, 480 .ring_destroy = psp_v13_0_ring_destroy, 481 .ring_get_wptr = psp_v13_0_ring_get_wptr, 482 .ring_set_wptr = psp_v13_0_ring_set_wptr, 483 .load_usbc_pd_fw = psp_v13_0_load_usbc_pd_fw, 484 .read_usbc_pd_fw = psp_v13_0_read_usbc_pd_fw 485 }; 486 487 void psp_v13_0_set_psp_funcs(struct psp_context *psp) 488 { 489 psp->funcs = &psp_v13_0_funcs; 490 } 491