1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "amdgpu.h" 24 #include "amdgpu_psp.h" 25 #include "amdgpu_ucode.h" 26 #include "soc15_common.h" 27 #include "psp_v13_0.h" 28 29 #include "mp/mp_13_0_2_offset.h" 30 #include "mp/mp_13_0_2_sh_mask.h" 31 32 MODULE_FIRMWARE("amdgpu/aldebaran_sos.bin"); 33 MODULE_FIRMWARE("amdgpu/aldebaran_ta.bin"); 34 MODULE_FIRMWARE("amdgpu/yellow_carp_asd.bin"); 35 MODULE_FIRMWARE("amdgpu/yellow_carp_toc.bin"); 36 MODULE_FIRMWARE("amdgpu/yellow_carp_ta.bin"); 37 MODULE_FIRMWARE("amdgpu/psp_13_0_5_asd.bin"); 38 MODULE_FIRMWARE("amdgpu/psp_13_0_5_toc.bin"); 39 MODULE_FIRMWARE("amdgpu/psp_13_0_5_ta.bin"); 40 MODULE_FIRMWARE("amdgpu/psp_13_0_8_asd.bin"); 41 MODULE_FIRMWARE("amdgpu/psp_13_0_8_toc.bin"); 42 MODULE_FIRMWARE("amdgpu/psp_13_0_8_ta.bin"); 43 44 /* For large FW files the time to complete can be very long */ 45 #define USBC_PD_POLLING_LIMIT_S 240 46 47 /* Read USB-PD from LFB */ 48 #define GFX_CMD_USB_PD_USE_LFB 0x480 49 50 static int psp_v13_0_init_microcode(struct psp_context *psp) 51 { 52 struct amdgpu_device *adev = psp->adev; 53 const char *chip_name; 54 int err = 0; 55 56 switch (adev->ip_versions[MP0_HWIP][0]) { 57 case IP_VERSION(13, 0, 2): 58 chip_name = "aldebaran"; 59 break; 60 case IP_VERSION(13, 0, 1): 61 case IP_VERSION(13, 0, 3): 62 chip_name = "yellow_carp"; 63 break; 64 case IP_VERSION(13, 0, 5): 65 chip_name = "psp_13_0_5"; 66 break; 67 case IP_VERSION(13, 0, 8): 68 chip_name = "psp_13_0_8"; 69 break; 70 default: 71 BUG(); 72 } 73 switch (adev->ip_versions[MP0_HWIP][0]) { 74 case IP_VERSION(13, 0, 2): 75 err = psp_init_sos_microcode(psp, chip_name); 76 if (err) 77 return err; 78 err = psp_init_ta_microcode(&adev->psp, chip_name); 79 if (err) 80 return err; 81 break; 82 case IP_VERSION(13, 0, 1): 83 case IP_VERSION(13, 0, 3): 84 case IP_VERSION(13, 0, 5): 85 case IP_VERSION(13, 0, 8): 86 err = psp_init_asd_microcode(psp, chip_name); 87 if (err) 88 return err; 89 err = psp_init_toc_microcode(psp, chip_name); 90 if (err) 91 return err; 92 err = psp_init_ta_microcode(psp, chip_name); 93 if (err) 94 return err; 95 break; 96 default: 97 BUG(); 98 } 99 100 return 0; 101 } 102 103 static bool psp_v13_0_is_sos_alive(struct psp_context *psp) 104 { 105 struct amdgpu_device *adev = psp->adev; 106 uint32_t sol_reg; 107 108 sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81); 109 110 return sol_reg != 0x0; 111 } 112 113 static int psp_v13_0_wait_for_bootloader(struct psp_context *psp) 114 { 115 struct amdgpu_device *adev = psp->adev; 116 117 int ret; 118 int retry_loop; 119 120 for (retry_loop = 0; retry_loop < 10; retry_loop++) { 121 /* Wait for bootloader to signify that is 122 ready having bit 31 of C2PMSG_35 set to 1 */ 123 ret = psp_wait_for(psp, 124 SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 125 0x80000000, 126 0x80000000, 127 false); 128 129 if (ret == 0) 130 return 0; 131 } 132 133 return ret; 134 } 135 136 static int psp_v13_0_bootloader_load_component(struct psp_context *psp, 137 struct psp_bin_desc *bin_desc, 138 enum psp_bootloader_cmd bl_cmd) 139 { 140 int ret; 141 uint32_t psp_gfxdrv_command_reg = 0; 142 struct amdgpu_device *adev = psp->adev; 143 144 /* Check tOS sign of life register to confirm sys driver and sOS 145 * are already been loaded. 146 */ 147 if (psp_v13_0_is_sos_alive(psp)) 148 return 0; 149 150 ret = psp_v13_0_wait_for_bootloader(psp); 151 if (ret) 152 return ret; 153 154 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 155 156 /* Copy PSP KDB binary to memory */ 157 memcpy(psp->fw_pri_buf, bin_desc->start_addr, bin_desc->size_bytes); 158 159 /* Provide the PSP KDB to bootloader */ 160 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, 161 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 162 psp_gfxdrv_command_reg = bl_cmd; 163 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, 164 psp_gfxdrv_command_reg); 165 166 ret = psp_v13_0_wait_for_bootloader(psp); 167 168 return ret; 169 } 170 171 static int psp_v13_0_bootloader_load_kdb(struct psp_context *psp) 172 { 173 return psp_v13_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_KEY_DATABASE); 174 } 175 176 static int psp_v13_0_bootloader_load_sysdrv(struct psp_context *psp) 177 { 178 return psp_v13_0_bootloader_load_component(psp, &psp->sys, PSP_BL__LOAD_SYSDRV); 179 } 180 181 static int psp_v13_0_bootloader_load_soc_drv(struct psp_context *psp) 182 { 183 return psp_v13_0_bootloader_load_component(psp, &psp->soc_drv, PSP_BL__LOAD_SOCDRV); 184 } 185 186 static int psp_v13_0_bootloader_load_intf_drv(struct psp_context *psp) 187 { 188 return psp_v13_0_bootloader_load_component(psp, &psp->intf_drv, PSP_BL__LOAD_INTFDRV); 189 } 190 191 static int psp_v13_0_bootloader_load_dbg_drv(struct psp_context *psp) 192 { 193 return psp_v13_0_bootloader_load_component(psp, &psp->dbg_drv, PSP_BL__LOAD_DBGDRV); 194 } 195 196 static int psp_v13_0_bootloader_load_sos(struct psp_context *psp) 197 { 198 int ret; 199 unsigned int psp_gfxdrv_command_reg = 0; 200 struct amdgpu_device *adev = psp->adev; 201 202 /* Check sOS sign of life register to confirm sys driver and sOS 203 * are already been loaded. 204 */ 205 if (psp_v13_0_is_sos_alive(psp)) 206 return 0; 207 208 ret = psp_v13_0_wait_for_bootloader(psp); 209 if (ret) 210 return ret; 211 212 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 213 214 /* Copy Secure OS binary to PSP memory */ 215 memcpy(psp->fw_pri_buf, psp->sos.start_addr, psp->sos.size_bytes); 216 217 /* Provide the PSP secure OS to bootloader */ 218 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, 219 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 220 psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV; 221 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, 222 psp_gfxdrv_command_reg); 223 224 /* there might be handshake issue with hardware which needs delay */ 225 mdelay(20); 226 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_81), 227 RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81), 228 0, true); 229 230 return ret; 231 } 232 233 static int psp_v13_0_ring_init(struct psp_context *psp, 234 enum psp_ring_type ring_type) 235 { 236 int ret = 0; 237 struct psp_ring *ring; 238 struct amdgpu_device *adev = psp->adev; 239 240 ring = &psp->km_ring; 241 242 ring->ring_type = ring_type; 243 244 /* allocate 4k Page of Local Frame Buffer memory for ring */ 245 ring->ring_size = 0x1000; 246 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE, 247 AMDGPU_GEM_DOMAIN_VRAM, 248 &adev->firmware.rbuf, 249 &ring->ring_mem_mc_addr, 250 (void **)&ring->ring_mem); 251 if (ret) { 252 ring->ring_size = 0; 253 return ret; 254 } 255 256 return 0; 257 } 258 259 static int psp_v13_0_ring_stop(struct psp_context *psp, 260 enum psp_ring_type ring_type) 261 { 262 int ret = 0; 263 struct amdgpu_device *adev = psp->adev; 264 265 if (amdgpu_sriov_vf(adev)) { 266 /* Write the ring destroy command*/ 267 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, 268 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING); 269 /* there might be handshake issue with hardware which needs delay */ 270 mdelay(20); 271 /* Wait for response flag (bit 31) */ 272 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101), 273 0x80000000, 0x80000000, false); 274 } else { 275 /* Write the ring destroy command*/ 276 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, 277 GFX_CTRL_CMD_ID_DESTROY_RINGS); 278 /* there might be handshake issue with hardware which needs delay */ 279 mdelay(20); 280 /* Wait for response flag (bit 31) */ 281 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), 282 0x80000000, 0x80000000, false); 283 } 284 285 return ret; 286 } 287 288 static int psp_v13_0_ring_create(struct psp_context *psp, 289 enum psp_ring_type ring_type) 290 { 291 int ret = 0; 292 unsigned int psp_ring_reg = 0; 293 struct psp_ring *ring = &psp->km_ring; 294 struct amdgpu_device *adev = psp->adev; 295 296 if (amdgpu_sriov_vf(adev)) { 297 ret = psp_v13_0_ring_stop(psp, ring_type); 298 if (ret) { 299 DRM_ERROR("psp_v13_0_ring_stop_sriov failed!\n"); 300 return ret; 301 } 302 303 /* Write low address of the ring to C2PMSG_102 */ 304 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 305 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, psp_ring_reg); 306 /* Write high address of the ring to C2PMSG_103 */ 307 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 308 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_103, psp_ring_reg); 309 310 /* Write the ring initialization command to C2PMSG_101 */ 311 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, 312 GFX_CTRL_CMD_ID_INIT_GPCOM_RING); 313 314 /* there might be handshake issue with hardware which needs delay */ 315 mdelay(20); 316 317 /* Wait for response flag (bit 31) in C2PMSG_101 */ 318 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101), 319 0x80000000, 0x8000FFFF, false); 320 321 } else { 322 /* Wait for sOS ready for ring creation */ 323 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), 324 0x80000000, 0x80000000, false); 325 if (ret) { 326 DRM_ERROR("Failed to wait for trust OS ready for ring creation\n"); 327 return ret; 328 } 329 330 /* Write low address of the ring to C2PMSG_69 */ 331 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 332 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_69, psp_ring_reg); 333 /* Write high address of the ring to C2PMSG_70 */ 334 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 335 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_70, psp_ring_reg); 336 /* Write size of ring to C2PMSG_71 */ 337 psp_ring_reg = ring->ring_size; 338 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_71, psp_ring_reg); 339 /* Write the ring initialization command to C2PMSG_64 */ 340 psp_ring_reg = ring_type; 341 psp_ring_reg = psp_ring_reg << 16; 342 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, psp_ring_reg); 343 344 /* there might be handshake issue with hardware which needs delay */ 345 mdelay(20); 346 347 /* Wait for response flag (bit 31) in C2PMSG_64 */ 348 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), 349 0x80000000, 0x8000FFFF, false); 350 } 351 352 return ret; 353 } 354 355 static int psp_v13_0_ring_destroy(struct psp_context *psp, 356 enum psp_ring_type ring_type) 357 { 358 int ret = 0; 359 struct psp_ring *ring = &psp->km_ring; 360 struct amdgpu_device *adev = psp->adev; 361 362 ret = psp_v13_0_ring_stop(psp, ring_type); 363 if (ret) 364 DRM_ERROR("Fail to stop psp ring\n"); 365 366 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 367 &ring->ring_mem_mc_addr, 368 (void **)&ring->ring_mem); 369 370 return ret; 371 } 372 373 static uint32_t psp_v13_0_ring_get_wptr(struct psp_context *psp) 374 { 375 uint32_t data; 376 struct amdgpu_device *adev = psp->adev; 377 378 if (amdgpu_sriov_vf(adev)) 379 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102); 380 else 381 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67); 382 383 return data; 384 } 385 386 static void psp_v13_0_ring_set_wptr(struct psp_context *psp, uint32_t value) 387 { 388 struct amdgpu_device *adev = psp->adev; 389 390 if (amdgpu_sriov_vf(adev)) { 391 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, value); 392 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, 393 GFX_CTRL_CMD_ID_CONSUME_CMD); 394 } else 395 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67, value); 396 } 397 398 static int psp_v13_0_load_usbc_pd_fw(struct psp_context *psp, uint64_t fw_pri_mc_addr) 399 { 400 struct amdgpu_device *adev = psp->adev; 401 uint32_t reg_status; 402 int ret, i = 0; 403 404 /* 405 * LFB address which is aligned to 1MB address and has to be 406 * right-shifted by 20 so that LFB address can be passed on a 32-bit C2P 407 * register 408 */ 409 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, (fw_pri_mc_addr >> 20)); 410 411 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 412 0x80000000, 0x80000000, false); 413 if (ret) 414 return ret; 415 416 /* Fireup interrupt so PSP can pick up the address */ 417 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, (GFX_CMD_USB_PD_USE_LFB << 16)); 418 419 /* FW load takes very long time */ 420 do { 421 msleep(1000); 422 reg_status = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35); 423 424 if (reg_status & 0x80000000) 425 goto done; 426 427 } while (++i < USBC_PD_POLLING_LIMIT_S); 428 429 return -ETIME; 430 done: 431 432 if ((reg_status & 0xFFFF) != 0) { 433 DRM_ERROR("Address load failed - MP0_SMN_C2PMSG_35.Bits [15:0] = %04x\n", 434 reg_status & 0xFFFF); 435 return -EIO; 436 } 437 438 return 0; 439 } 440 441 static int psp_v13_0_read_usbc_pd_fw(struct psp_context *psp, uint32_t *fw_ver) 442 { 443 struct amdgpu_device *adev = psp->adev; 444 int ret; 445 446 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, C2PMSG_CMD_GFX_USB_PD_FW_VER); 447 448 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 449 0x80000000, 0x80000000, false); 450 if (!ret) 451 *fw_ver = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36); 452 453 return ret; 454 } 455 456 static const struct psp_funcs psp_v13_0_funcs = { 457 .init_microcode = psp_v13_0_init_microcode, 458 .bootloader_load_kdb = psp_v13_0_bootloader_load_kdb, 459 .bootloader_load_sysdrv = psp_v13_0_bootloader_load_sysdrv, 460 .bootloader_load_soc_drv = psp_v13_0_bootloader_load_soc_drv, 461 .bootloader_load_intf_drv = psp_v13_0_bootloader_load_intf_drv, 462 .bootloader_load_dbg_drv = psp_v13_0_bootloader_load_dbg_drv, 463 .bootloader_load_sos = psp_v13_0_bootloader_load_sos, 464 .ring_init = psp_v13_0_ring_init, 465 .ring_create = psp_v13_0_ring_create, 466 .ring_stop = psp_v13_0_ring_stop, 467 .ring_destroy = psp_v13_0_ring_destroy, 468 .ring_get_wptr = psp_v13_0_ring_get_wptr, 469 .ring_set_wptr = psp_v13_0_ring_set_wptr, 470 .load_usbc_pd_fw = psp_v13_0_load_usbc_pd_fw, 471 .read_usbc_pd_fw = psp_v13_0_read_usbc_pd_fw 472 }; 473 474 void psp_v13_0_set_psp_funcs(struct psp_context *psp) 475 { 476 psp->funcs = &psp_v13_0_funcs; 477 } 478