1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <drm/drm_drv.h> 24 #include <linux/vmalloc.h> 25 #include "amdgpu.h" 26 #include "amdgpu_psp.h" 27 #include "amdgpu_ucode.h" 28 #include "soc15_common.h" 29 #include "psp_v13_0.h" 30 #include "amdgpu_ras.h" 31 32 #include "mp/mp_13_0_2_offset.h" 33 #include "mp/mp_13_0_2_sh_mask.h" 34 35 MODULE_FIRMWARE("amdgpu/aldebaran_sos.bin"); 36 MODULE_FIRMWARE("amdgpu/aldebaran_ta.bin"); 37 MODULE_FIRMWARE("amdgpu/aldebaran_cap.bin"); 38 MODULE_FIRMWARE("amdgpu/yellow_carp_toc.bin"); 39 MODULE_FIRMWARE("amdgpu/yellow_carp_ta.bin"); 40 MODULE_FIRMWARE("amdgpu/psp_13_0_5_toc.bin"); 41 MODULE_FIRMWARE("amdgpu/psp_13_0_5_ta.bin"); 42 MODULE_FIRMWARE("amdgpu/psp_13_0_8_toc.bin"); 43 MODULE_FIRMWARE("amdgpu/psp_13_0_8_ta.bin"); 44 MODULE_FIRMWARE("amdgpu/psp_13_0_0_sos.bin"); 45 MODULE_FIRMWARE("amdgpu/psp_13_0_0_ta.bin"); 46 MODULE_FIRMWARE("amdgpu/psp_13_0_7_sos.bin"); 47 MODULE_FIRMWARE("amdgpu/psp_13_0_7_ta.bin"); 48 MODULE_FIRMWARE("amdgpu/psp_13_0_10_sos.bin"); 49 MODULE_FIRMWARE("amdgpu/psp_13_0_10_ta.bin"); 50 MODULE_FIRMWARE("amdgpu/psp_13_0_11_toc.bin"); 51 MODULE_FIRMWARE("amdgpu/psp_13_0_11_ta.bin"); 52 MODULE_FIRMWARE("amdgpu/psp_13_0_6_sos.bin"); 53 MODULE_FIRMWARE("amdgpu/psp_13_0_6_ta.bin"); 54 MODULE_FIRMWARE("amdgpu/psp_13_0_14_sos.bin"); 55 MODULE_FIRMWARE("amdgpu/psp_13_0_14_ta.bin"); 56 MODULE_FIRMWARE("amdgpu/psp_14_0_0_toc.bin"); 57 MODULE_FIRMWARE("amdgpu/psp_14_0_0_ta.bin"); 58 MODULE_FIRMWARE("amdgpu/psp_14_0_1_toc.bin"); 59 MODULE_FIRMWARE("amdgpu/psp_14_0_1_ta.bin"); 60 MODULE_FIRMWARE("amdgpu/psp_14_0_4_toc.bin"); 61 MODULE_FIRMWARE("amdgpu/psp_14_0_4_ta.bin"); 62 63 /* For large FW files the time to complete can be very long */ 64 #define USBC_PD_POLLING_LIMIT_S 240 65 66 /* Read USB-PD from LFB */ 67 #define GFX_CMD_USB_PD_USE_LFB 0x480 68 69 /* Retry times for vmbx ready wait */ 70 #define PSP_VMBX_POLLING_LIMIT 3000 71 72 /* VBIOS gfl defines */ 73 #define MBOX_READY_MASK 0x80000000 74 #define MBOX_STATUS_MASK 0x0000FFFF 75 #define MBOX_COMMAND_MASK 0x00FF0000 76 #define MBOX_READY_FLAG 0x80000000 77 #define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_LO 0x2 78 #define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI 0x3 79 #define C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE 0x4 80 81 /* memory training timeout define */ 82 #define MEM_TRAIN_SEND_MSG_TIMEOUT_US 3000000 83 84 static int psp_v13_0_init_microcode(struct psp_context *psp) 85 { 86 struct amdgpu_device *adev = psp->adev; 87 char ucode_prefix[30]; 88 int err = 0; 89 90 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); 91 92 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 93 case IP_VERSION(13, 0, 2): 94 err = psp_init_sos_microcode(psp, ucode_prefix); 95 if (err) 96 return err; 97 /* It's not necessary to load ras ta on Guest side */ 98 if (!amdgpu_sriov_vf(adev)) { 99 err = psp_init_ta_microcode(psp, ucode_prefix); 100 if (err) 101 return err; 102 } 103 break; 104 case IP_VERSION(13, 0, 1): 105 case IP_VERSION(13, 0, 3): 106 case IP_VERSION(13, 0, 5): 107 case IP_VERSION(13, 0, 8): 108 case IP_VERSION(13, 0, 11): 109 case IP_VERSION(14, 0, 0): 110 case IP_VERSION(14, 0, 1): 111 case IP_VERSION(14, 0, 4): 112 err = psp_init_toc_microcode(psp, ucode_prefix); 113 if (err) 114 return err; 115 err = psp_init_ta_microcode(psp, ucode_prefix); 116 if (err) 117 return err; 118 break; 119 case IP_VERSION(13, 0, 0): 120 case IP_VERSION(13, 0, 6): 121 case IP_VERSION(13, 0, 7): 122 case IP_VERSION(13, 0, 10): 123 case IP_VERSION(13, 0, 14): 124 err = psp_init_sos_microcode(psp, ucode_prefix); 125 if (err) 126 return err; 127 /* It's not necessary to load ras ta on Guest side */ 128 err = psp_init_ta_microcode(psp, ucode_prefix); 129 if (err) 130 return err; 131 break; 132 default: 133 BUG(); 134 } 135 136 return 0; 137 } 138 139 static bool psp_v13_0_is_sos_alive(struct psp_context *psp) 140 { 141 struct amdgpu_device *adev = psp->adev; 142 uint32_t sol_reg; 143 144 sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81); 145 146 return sol_reg != 0x0; 147 } 148 149 static int psp_v13_0_wait_for_vmbx_ready(struct psp_context *psp) 150 { 151 struct amdgpu_device *adev = psp->adev; 152 int retry_loop, ret; 153 154 for (retry_loop = 0; retry_loop < PSP_VMBX_POLLING_LIMIT; retry_loop++) { 155 /* Wait for bootloader to signify that is 156 ready having bit 31 of C2PMSG_33 set to 1 */ 157 ret = psp_wait_for( 158 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_33), 159 0x80000000, 0xffffffff, false); 160 161 if (ret == 0) 162 break; 163 } 164 165 if (ret) 166 dev_warn(adev->dev, "Bootloader wait timed out"); 167 168 return ret; 169 } 170 171 static int psp_v13_0_wait_for_bootloader(struct psp_context *psp) 172 { 173 struct amdgpu_device *adev = psp->adev; 174 int retry_loop, retry_cnt, ret; 175 176 retry_cnt = 177 ((amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) || 178 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14))) ? 179 PSP_VMBX_POLLING_LIMIT : 180 10; 181 /* Wait for bootloader to signify that it is ready having bit 31 of 182 * C2PMSG_35 set to 1. All other bits are expected to be cleared. 183 * If there is an error in processing command, bits[7:0] will be set. 184 * This is applicable for PSP v13.0.6 and newer. 185 */ 186 for (retry_loop = 0; retry_loop < retry_cnt; retry_loop++) { 187 ret = psp_wait_for( 188 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 189 0x80000000, 0xffffffff, false); 190 191 if (ret == 0) 192 return 0; 193 } 194 195 return ret; 196 } 197 198 static int psp_v13_0_wait_for_bootloader_steady_state(struct psp_context *psp) 199 { 200 struct amdgpu_device *adev = psp->adev; 201 int ret; 202 203 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) || 204 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14)) { 205 ret = psp_v13_0_wait_for_vmbx_ready(psp); 206 if (ret) 207 amdgpu_ras_query_boot_status(adev, 4); 208 209 ret = psp_v13_0_wait_for_bootloader(psp); 210 if (ret) 211 amdgpu_ras_query_boot_status(adev, 4); 212 213 return ret; 214 } 215 216 return 0; 217 } 218 219 static int psp_v13_0_bootloader_load_component(struct psp_context *psp, 220 struct psp_bin_desc *bin_desc, 221 enum psp_bootloader_cmd bl_cmd) 222 { 223 int ret; 224 uint32_t psp_gfxdrv_command_reg = 0; 225 struct amdgpu_device *adev = psp->adev; 226 227 /* Check tOS sign of life register to confirm sys driver and sOS 228 * are already been loaded. 229 */ 230 if (psp_v13_0_is_sos_alive(psp)) 231 return 0; 232 233 ret = psp_v13_0_wait_for_bootloader(psp); 234 if (ret) 235 return ret; 236 237 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 238 239 /* Copy PSP KDB binary to memory */ 240 memcpy(psp->fw_pri_buf, bin_desc->start_addr, bin_desc->size_bytes); 241 242 /* Provide the PSP KDB to bootloader */ 243 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, 244 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 245 psp_gfxdrv_command_reg = bl_cmd; 246 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, 247 psp_gfxdrv_command_reg); 248 249 ret = psp_v13_0_wait_for_bootloader(psp); 250 251 return ret; 252 } 253 254 static int psp_v13_0_bootloader_load_kdb(struct psp_context *psp) 255 { 256 return psp_v13_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_KEY_DATABASE); 257 } 258 259 static int psp_v13_0_bootloader_load_spl(struct psp_context *psp) 260 { 261 return psp_v13_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_TOS_SPL_TABLE); 262 } 263 264 static int psp_v13_0_bootloader_load_sysdrv(struct psp_context *psp) 265 { 266 return psp_v13_0_bootloader_load_component(psp, &psp->sys, PSP_BL__LOAD_SYSDRV); 267 } 268 269 static int psp_v13_0_bootloader_load_soc_drv(struct psp_context *psp) 270 { 271 return psp_v13_0_bootloader_load_component(psp, &psp->soc_drv, PSP_BL__LOAD_SOCDRV); 272 } 273 274 static int psp_v13_0_bootloader_load_intf_drv(struct psp_context *psp) 275 { 276 return psp_v13_0_bootloader_load_component(psp, &psp->intf_drv, PSP_BL__LOAD_INTFDRV); 277 } 278 279 static int psp_v13_0_bootloader_load_dbg_drv(struct psp_context *psp) 280 { 281 return psp_v13_0_bootloader_load_component(psp, &psp->dbg_drv, PSP_BL__LOAD_DBGDRV); 282 } 283 284 static int psp_v13_0_bootloader_load_ras_drv(struct psp_context *psp) 285 { 286 return psp_v13_0_bootloader_load_component(psp, &psp->ras_drv, PSP_BL__LOAD_RASDRV); 287 } 288 289 static inline void psp_v13_0_init_sos_version(struct psp_context *psp) 290 { 291 struct amdgpu_device *adev = psp->adev; 292 293 psp->sos.fw_version = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_58); 294 } 295 296 static int psp_v13_0_bootloader_load_sos(struct psp_context *psp) 297 { 298 int ret; 299 unsigned int psp_gfxdrv_command_reg = 0; 300 struct amdgpu_device *adev = psp->adev; 301 302 /* Check sOS sign of life register to confirm sys driver and sOS 303 * are already been loaded. 304 */ 305 if (psp_v13_0_is_sos_alive(psp)) { 306 psp_v13_0_init_sos_version(psp); 307 return 0; 308 } 309 310 ret = psp_v13_0_wait_for_bootloader(psp); 311 if (ret) 312 return ret; 313 314 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 315 316 /* Copy Secure OS binary to PSP memory */ 317 memcpy(psp->fw_pri_buf, psp->sos.start_addr, psp->sos.size_bytes); 318 319 /* Provide the PSP secure OS to bootloader */ 320 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, 321 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 322 psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV; 323 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, 324 psp_gfxdrv_command_reg); 325 326 /* there might be handshake issue with hardware which needs delay */ 327 mdelay(20); 328 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_81), 329 RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81), 330 0, true); 331 332 if (!ret) 333 psp_v13_0_init_sos_version(psp); 334 335 return ret; 336 } 337 338 static int psp_v13_0_ring_stop(struct psp_context *psp, 339 enum psp_ring_type ring_type) 340 { 341 int ret = 0; 342 struct amdgpu_device *adev = psp->adev; 343 344 if (amdgpu_sriov_vf(adev)) { 345 /* Write the ring destroy command*/ 346 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, 347 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING); 348 /* there might be handshake issue with hardware which needs delay */ 349 mdelay(20); 350 /* Wait for response flag (bit 31) */ 351 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101), 352 0x80000000, 0x80000000, false); 353 } else { 354 /* Write the ring destroy command*/ 355 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, 356 GFX_CTRL_CMD_ID_DESTROY_RINGS); 357 /* there might be handshake issue with hardware which needs delay */ 358 mdelay(20); 359 /* Wait for response flag (bit 31) */ 360 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), 361 0x80000000, 0x80000000, false); 362 } 363 364 return ret; 365 } 366 367 static int psp_v13_0_ring_create(struct psp_context *psp, 368 enum psp_ring_type ring_type) 369 { 370 int ret = 0; 371 unsigned int psp_ring_reg = 0; 372 struct psp_ring *ring = &psp->km_ring; 373 struct amdgpu_device *adev = psp->adev; 374 375 if (amdgpu_sriov_vf(adev)) { 376 ret = psp_v13_0_ring_stop(psp, ring_type); 377 if (ret) { 378 DRM_ERROR("psp_v13_0_ring_stop_sriov failed!\n"); 379 return ret; 380 } 381 382 /* Write low address of the ring to C2PMSG_102 */ 383 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 384 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, psp_ring_reg); 385 /* Write high address of the ring to C2PMSG_103 */ 386 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 387 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_103, psp_ring_reg); 388 389 /* Write the ring initialization command to C2PMSG_101 */ 390 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, 391 GFX_CTRL_CMD_ID_INIT_GPCOM_RING); 392 393 /* there might be handshake issue with hardware which needs delay */ 394 mdelay(20); 395 396 /* Wait for response flag (bit 31) in C2PMSG_101 */ 397 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101), 398 0x80000000, 0x8000FFFF, false); 399 400 } else { 401 /* Wait for sOS ready for ring creation */ 402 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), 403 0x80000000, 0x80000000, false); 404 if (ret) { 405 DRM_ERROR("Failed to wait for trust OS ready for ring creation\n"); 406 return ret; 407 } 408 409 /* Write low address of the ring to C2PMSG_69 */ 410 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 411 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_69, psp_ring_reg); 412 /* Write high address of the ring to C2PMSG_70 */ 413 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 414 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_70, psp_ring_reg); 415 /* Write size of ring to C2PMSG_71 */ 416 psp_ring_reg = ring->ring_size; 417 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_71, psp_ring_reg); 418 /* Write the ring initialization command to C2PMSG_64 */ 419 psp_ring_reg = ring_type; 420 psp_ring_reg = psp_ring_reg << 16; 421 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, psp_ring_reg); 422 423 /* there might be handshake issue with hardware which needs delay */ 424 mdelay(20); 425 426 /* Wait for response flag (bit 31) in C2PMSG_64 */ 427 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), 428 0x80000000, 0x8000FFFF, false); 429 } 430 431 return ret; 432 } 433 434 static int psp_v13_0_ring_destroy(struct psp_context *psp, 435 enum psp_ring_type ring_type) 436 { 437 int ret = 0; 438 struct psp_ring *ring = &psp->km_ring; 439 struct amdgpu_device *adev = psp->adev; 440 441 ret = psp_v13_0_ring_stop(psp, ring_type); 442 if (ret) 443 DRM_ERROR("Fail to stop psp ring\n"); 444 445 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 446 &ring->ring_mem_mc_addr, 447 (void **)&ring->ring_mem); 448 449 return ret; 450 } 451 452 static uint32_t psp_v13_0_ring_get_wptr(struct psp_context *psp) 453 { 454 uint32_t data; 455 struct amdgpu_device *adev = psp->adev; 456 457 if (amdgpu_sriov_vf(adev)) 458 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102); 459 else 460 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67); 461 462 return data; 463 } 464 465 static void psp_v13_0_ring_set_wptr(struct psp_context *psp, uint32_t value) 466 { 467 struct amdgpu_device *adev = psp->adev; 468 469 if (amdgpu_sriov_vf(adev)) { 470 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, value); 471 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, 472 GFX_CTRL_CMD_ID_CONSUME_CMD); 473 } else 474 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67, value); 475 } 476 477 static int psp_v13_0_memory_training_send_msg(struct psp_context *psp, int msg) 478 { 479 int ret; 480 int i; 481 uint32_t data_32; 482 int max_wait; 483 struct amdgpu_device *adev = psp->adev; 484 485 data_32 = (psp->mem_train_ctx.c2p_train_data_offset >> 20); 486 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, data_32); 487 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, msg); 488 489 max_wait = MEM_TRAIN_SEND_MSG_TIMEOUT_US / adev->usec_timeout; 490 for (i = 0; i < max_wait; i++) { 491 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 492 0x80000000, 0x80000000, false); 493 if (ret == 0) 494 break; 495 } 496 if (i < max_wait) 497 ret = 0; 498 else 499 ret = -ETIME; 500 501 dev_dbg(adev->dev, "training %s %s, cost %d @ %d ms\n", 502 (msg == PSP_BL__DRAM_SHORT_TRAIN) ? "short" : "long", 503 (ret == 0) ? "succeed" : "failed", 504 i, adev->usec_timeout/1000); 505 return ret; 506 } 507 508 509 static int psp_v13_0_memory_training(struct psp_context *psp, uint32_t ops) 510 { 511 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 512 uint32_t *pcache = (uint32_t *)ctx->sys_cache; 513 struct amdgpu_device *adev = psp->adev; 514 uint32_t p2c_header[4]; 515 uint32_t sz; 516 void *buf; 517 int ret, idx; 518 519 if (ctx->init == PSP_MEM_TRAIN_NOT_SUPPORT) { 520 dev_dbg(adev->dev, "Memory training is not supported.\n"); 521 return 0; 522 } else if (ctx->init != PSP_MEM_TRAIN_INIT_SUCCESS) { 523 dev_err(adev->dev, "Memory training initialization failure.\n"); 524 return -EINVAL; 525 } 526 527 if (psp_v13_0_is_sos_alive(psp)) { 528 dev_dbg(adev->dev, "SOS is alive, skip memory training.\n"); 529 return 0; 530 } 531 532 amdgpu_device_vram_access(adev, ctx->p2c_train_data_offset, p2c_header, sizeof(p2c_header), false); 533 dev_dbg(adev->dev, "sys_cache[%08x,%08x,%08x,%08x] p2c_header[%08x,%08x,%08x,%08x]\n", 534 pcache[0], pcache[1], pcache[2], pcache[3], 535 p2c_header[0], p2c_header[1], p2c_header[2], p2c_header[3]); 536 537 if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) { 538 dev_dbg(adev->dev, "Short training depends on restore.\n"); 539 ops |= PSP_MEM_TRAIN_RESTORE; 540 } 541 542 if ((ops & PSP_MEM_TRAIN_RESTORE) && 543 pcache[0] != MEM_TRAIN_SYSTEM_SIGNATURE) { 544 dev_dbg(adev->dev, "sys_cache[0] is invalid, restore depends on save.\n"); 545 ops |= PSP_MEM_TRAIN_SAVE; 546 } 547 548 if (p2c_header[0] == MEM_TRAIN_SYSTEM_SIGNATURE && 549 !(pcache[0] == MEM_TRAIN_SYSTEM_SIGNATURE && 550 pcache[3] == p2c_header[3])) { 551 dev_dbg(adev->dev, "sys_cache is invalid or out-of-date, need save training data to sys_cache.\n"); 552 ops |= PSP_MEM_TRAIN_SAVE; 553 } 554 555 if ((ops & PSP_MEM_TRAIN_SAVE) && 556 p2c_header[0] != MEM_TRAIN_SYSTEM_SIGNATURE) { 557 dev_dbg(adev->dev, "p2c_header[0] is invalid, save depends on long training.\n"); 558 ops |= PSP_MEM_TRAIN_SEND_LONG_MSG; 559 } 560 561 if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) { 562 ops &= ~PSP_MEM_TRAIN_SEND_SHORT_MSG; 563 ops |= PSP_MEM_TRAIN_SAVE; 564 } 565 566 dev_dbg(adev->dev, "Memory training ops:%x.\n", ops); 567 568 if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) { 569 /* 570 * Long training will encroach a certain amount on the bottom of VRAM; 571 * save the content from the bottom of VRAM to system memory 572 * before training, and restore it after training to avoid 573 * VRAM corruption. 574 */ 575 sz = BIST_MEM_TRAINING_ENCROACHED_SIZE; 576 577 if (adev->gmc.visible_vram_size < sz || !adev->mman.aper_base_kaddr) { 578 dev_err(adev->dev, "visible_vram_size %llx or aper_base_kaddr %p is not initialized.\n", 579 adev->gmc.visible_vram_size, 580 adev->mman.aper_base_kaddr); 581 return -EINVAL; 582 } 583 584 buf = vmalloc(sz); 585 if (!buf) { 586 dev_err(adev->dev, "failed to allocate system memory.\n"); 587 return -ENOMEM; 588 } 589 590 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 591 memcpy_fromio(buf, adev->mman.aper_base_kaddr, sz); 592 ret = psp_v13_0_memory_training_send_msg(psp, PSP_BL__DRAM_LONG_TRAIN); 593 if (ret) { 594 DRM_ERROR("Send long training msg failed.\n"); 595 vfree(buf); 596 drm_dev_exit(idx); 597 return ret; 598 } 599 600 memcpy_toio(adev->mman.aper_base_kaddr, buf, sz); 601 adev->hdp.funcs->flush_hdp(adev, NULL); 602 vfree(buf); 603 drm_dev_exit(idx); 604 } else { 605 vfree(buf); 606 return -ENODEV; 607 } 608 } 609 610 if (ops & PSP_MEM_TRAIN_SAVE) { 611 amdgpu_device_vram_access(psp->adev, ctx->p2c_train_data_offset, ctx->sys_cache, ctx->train_data_size, false); 612 } 613 614 if (ops & PSP_MEM_TRAIN_RESTORE) { 615 amdgpu_device_vram_access(psp->adev, ctx->c2p_train_data_offset, ctx->sys_cache, ctx->train_data_size, true); 616 } 617 618 if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) { 619 ret = psp_v13_0_memory_training_send_msg(psp, (amdgpu_force_long_training > 0) ? 620 PSP_BL__DRAM_LONG_TRAIN : PSP_BL__DRAM_SHORT_TRAIN); 621 if (ret) { 622 dev_err(adev->dev, "send training msg failed.\n"); 623 return ret; 624 } 625 } 626 ctx->training_cnt++; 627 return 0; 628 } 629 630 static int psp_v13_0_load_usbc_pd_fw(struct psp_context *psp, uint64_t fw_pri_mc_addr) 631 { 632 struct amdgpu_device *adev = psp->adev; 633 uint32_t reg_status; 634 int ret, i = 0; 635 636 /* 637 * LFB address which is aligned to 1MB address and has to be 638 * right-shifted by 20 so that LFB address can be passed on a 32-bit C2P 639 * register 640 */ 641 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, (fw_pri_mc_addr >> 20)); 642 643 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 644 0x80000000, 0x80000000, false); 645 if (ret) 646 return ret; 647 648 /* Fireup interrupt so PSP can pick up the address */ 649 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, (GFX_CMD_USB_PD_USE_LFB << 16)); 650 651 /* FW load takes very long time */ 652 do { 653 msleep(1000); 654 reg_status = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35); 655 656 if (reg_status & 0x80000000) 657 goto done; 658 659 } while (++i < USBC_PD_POLLING_LIMIT_S); 660 661 return -ETIME; 662 done: 663 664 if ((reg_status & 0xFFFF) != 0) { 665 DRM_ERROR("Address load failed - MP0_SMN_C2PMSG_35.Bits [15:0] = %04x\n", 666 reg_status & 0xFFFF); 667 return -EIO; 668 } 669 670 return 0; 671 } 672 673 static int psp_v13_0_read_usbc_pd_fw(struct psp_context *psp, uint32_t *fw_ver) 674 { 675 struct amdgpu_device *adev = psp->adev; 676 int ret; 677 678 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, C2PMSG_CMD_GFX_USB_PD_FW_VER); 679 680 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 681 0x80000000, 0x80000000, false); 682 if (!ret) 683 *fw_ver = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36); 684 685 return ret; 686 } 687 688 static int psp_v13_0_exec_spi_cmd(struct psp_context *psp, int cmd) 689 { 690 uint32_t reg_status = 0, reg_val = 0; 691 struct amdgpu_device *adev = psp->adev; 692 int ret; 693 694 /* clear MBX ready (MBOX_READY_MASK bit is 0) and set update command */ 695 reg_val |= (cmd << 16); 696 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115, reg_val); 697 698 /* Ring the doorbell */ 699 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_73, 1); 700 701 if (cmd == C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE) 702 ret = psp_wait_for_spirom_update(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115), 703 MBOX_READY_FLAG, MBOX_READY_MASK, PSP_SPIROM_UPDATE_TIMEOUT); 704 else 705 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115), 706 MBOX_READY_FLAG, MBOX_READY_MASK, false); 707 if (ret) { 708 dev_err(adev->dev, "SPI cmd %x timed out, ret = %d", cmd, ret); 709 return ret; 710 } 711 712 reg_status = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115); 713 if ((reg_status & 0xFFFF) != 0) { 714 dev_err(adev->dev, "SPI cmd %x failed, fail status = %04x\n", 715 cmd, reg_status & 0xFFFF); 716 return -EIO; 717 } 718 719 return 0; 720 } 721 722 static int psp_v13_0_update_spirom(struct psp_context *psp, 723 uint64_t fw_pri_mc_addr) 724 { 725 struct amdgpu_device *adev = psp->adev; 726 int ret; 727 728 /* Confirm PSP is ready to start */ 729 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115), 730 MBOX_READY_FLAG, MBOX_READY_MASK, false); 731 if (ret) { 732 dev_err(adev->dev, "PSP Not ready to start processing, ret = %d", ret); 733 return ret; 734 } 735 736 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, lower_32_bits(fw_pri_mc_addr)); 737 738 ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_LO); 739 if (ret) 740 return ret; 741 742 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, upper_32_bits(fw_pri_mc_addr)); 743 744 ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI); 745 if (ret) 746 return ret; 747 748 psp->vbflash_done = true; 749 750 ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE); 751 if (ret) 752 return ret; 753 754 return 0; 755 } 756 757 static int psp_v13_0_vbflash_status(struct psp_context *psp) 758 { 759 struct amdgpu_device *adev = psp->adev; 760 761 return RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115); 762 } 763 764 static int psp_v13_0_fatal_error_recovery_quirk(struct psp_context *psp) 765 { 766 struct amdgpu_device *adev = psp->adev; 767 768 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 10)) { 769 uint32_t reg_data; 770 /* MP1 fatal error: trigger PSP dram read to unhalt PSP 771 * during MP1 triggered sync flood. 772 */ 773 reg_data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67); 774 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67, reg_data + 0x10); 775 776 /* delay 1000ms for the mode1 reset for fatal error 777 * to be recovered back. 778 */ 779 msleep(1000); 780 } 781 782 return 0; 783 } 784 785 static bool psp_v13_0_get_ras_capability(struct psp_context *psp) 786 { 787 struct amdgpu_device *adev = psp->adev; 788 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 789 u32 reg_data; 790 791 /* query ras cap should be done from host side */ 792 if (amdgpu_sriov_vf(adev)) 793 return false; 794 795 if (!con) 796 return false; 797 798 if ((amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) || 799 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14)) && 800 (!(adev->flags & AMD_IS_APU))) { 801 reg_data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_127); 802 adev->ras_hw_enabled = (reg_data & GENMASK_ULL(23, 0)); 803 con->poison_supported = ((reg_data & GENMASK_ULL(24, 24)) >> 24) ? true : false; 804 return true; 805 } else { 806 return false; 807 } 808 } 809 810 static const struct psp_funcs psp_v13_0_funcs = { 811 .init_microcode = psp_v13_0_init_microcode, 812 .wait_for_bootloader = psp_v13_0_wait_for_bootloader_steady_state, 813 .bootloader_load_kdb = psp_v13_0_bootloader_load_kdb, 814 .bootloader_load_spl = psp_v13_0_bootloader_load_spl, 815 .bootloader_load_sysdrv = psp_v13_0_bootloader_load_sysdrv, 816 .bootloader_load_soc_drv = psp_v13_0_bootloader_load_soc_drv, 817 .bootloader_load_intf_drv = psp_v13_0_bootloader_load_intf_drv, 818 .bootloader_load_dbg_drv = psp_v13_0_bootloader_load_dbg_drv, 819 .bootloader_load_ras_drv = psp_v13_0_bootloader_load_ras_drv, 820 .bootloader_load_sos = psp_v13_0_bootloader_load_sos, 821 .ring_create = psp_v13_0_ring_create, 822 .ring_stop = psp_v13_0_ring_stop, 823 .ring_destroy = psp_v13_0_ring_destroy, 824 .ring_get_wptr = psp_v13_0_ring_get_wptr, 825 .ring_set_wptr = psp_v13_0_ring_set_wptr, 826 .mem_training = psp_v13_0_memory_training, 827 .load_usbc_pd_fw = psp_v13_0_load_usbc_pd_fw, 828 .read_usbc_pd_fw = psp_v13_0_read_usbc_pd_fw, 829 .update_spirom = psp_v13_0_update_spirom, 830 .vbflash_stat = psp_v13_0_vbflash_status, 831 .fatal_error_recovery_quirk = psp_v13_0_fatal_error_recovery_quirk, 832 .get_ras_capability = psp_v13_0_get_ras_capability, 833 }; 834 835 void psp_v13_0_set_psp_funcs(struct psp_context *psp) 836 { 837 psp->funcs = &psp_v13_0_funcs; 838 } 839