1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <drm/drm_drv.h> 24 #include <linux/vmalloc.h> 25 #include "amdgpu.h" 26 #include "amdgpu_psp.h" 27 #include "amdgpu_ucode.h" 28 #include "soc15_common.h" 29 #include "psp_v13_0.h" 30 #include "amdgpu_ras.h" 31 32 #include "mp/mp_13_0_2_offset.h" 33 #include "mp/mp_13_0_2_sh_mask.h" 34 35 MODULE_FIRMWARE("amdgpu/aldebaran_sos.bin"); 36 MODULE_FIRMWARE("amdgpu/aldebaran_ta.bin"); 37 MODULE_FIRMWARE("amdgpu/aldebaran_cap.bin"); 38 MODULE_FIRMWARE("amdgpu/yellow_carp_toc.bin"); 39 MODULE_FIRMWARE("amdgpu/yellow_carp_ta.bin"); 40 MODULE_FIRMWARE("amdgpu/psp_13_0_5_toc.bin"); 41 MODULE_FIRMWARE("amdgpu/psp_13_0_5_ta.bin"); 42 MODULE_FIRMWARE("amdgpu/psp_13_0_8_toc.bin"); 43 MODULE_FIRMWARE("amdgpu/psp_13_0_8_ta.bin"); 44 MODULE_FIRMWARE("amdgpu/psp_13_0_0_sos.bin"); 45 MODULE_FIRMWARE("amdgpu/psp_13_0_0_ta.bin"); 46 MODULE_FIRMWARE("amdgpu/psp_13_0_7_sos.bin"); 47 MODULE_FIRMWARE("amdgpu/psp_13_0_7_ta.bin"); 48 MODULE_FIRMWARE("amdgpu/psp_13_0_10_sos.bin"); 49 MODULE_FIRMWARE("amdgpu/psp_13_0_10_ta.bin"); 50 MODULE_FIRMWARE("amdgpu/psp_13_0_11_toc.bin"); 51 MODULE_FIRMWARE("amdgpu/psp_13_0_11_ta.bin"); 52 MODULE_FIRMWARE("amdgpu/psp_13_0_6_sos.bin"); 53 MODULE_FIRMWARE("amdgpu/psp_13_0_6_ta.bin"); 54 MODULE_FIRMWARE("amdgpu/psp_14_0_0_toc.bin"); 55 MODULE_FIRMWARE("amdgpu/psp_14_0_0_ta.bin"); 56 57 /* For large FW files the time to complete can be very long */ 58 #define USBC_PD_POLLING_LIMIT_S 240 59 60 /* Read USB-PD from LFB */ 61 #define GFX_CMD_USB_PD_USE_LFB 0x480 62 63 /* Retry times for vmbx ready wait */ 64 #define PSP_VMBX_POLLING_LIMIT 3000 65 66 /* VBIOS gfl defines */ 67 #define MBOX_READY_MASK 0x80000000 68 #define MBOX_STATUS_MASK 0x0000FFFF 69 #define MBOX_COMMAND_MASK 0x00FF0000 70 #define MBOX_READY_FLAG 0x80000000 71 #define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_LO 0x2 72 #define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI 0x3 73 #define C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE 0x4 74 75 /* memory training timeout define */ 76 #define MEM_TRAIN_SEND_MSG_TIMEOUT_US 3000000 77 78 static int psp_v13_0_init_microcode(struct psp_context *psp) 79 { 80 struct amdgpu_device *adev = psp->adev; 81 char ucode_prefix[30]; 82 int err = 0; 83 84 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); 85 86 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 87 case IP_VERSION(13, 0, 2): 88 err = psp_init_sos_microcode(psp, ucode_prefix); 89 if (err) 90 return err; 91 /* It's not necessary to load ras ta on Guest side */ 92 if (!amdgpu_sriov_vf(adev)) { 93 err = psp_init_ta_microcode(psp, ucode_prefix); 94 if (err) 95 return err; 96 } 97 break; 98 case IP_VERSION(13, 0, 1): 99 case IP_VERSION(13, 0, 3): 100 case IP_VERSION(13, 0, 5): 101 case IP_VERSION(13, 0, 8): 102 case IP_VERSION(13, 0, 11): 103 case IP_VERSION(14, 0, 0): 104 err = psp_init_toc_microcode(psp, ucode_prefix); 105 if (err) 106 return err; 107 err = psp_init_ta_microcode(psp, ucode_prefix); 108 if (err) 109 return err; 110 break; 111 case IP_VERSION(13, 0, 0): 112 case IP_VERSION(13, 0, 6): 113 case IP_VERSION(13, 0, 7): 114 case IP_VERSION(13, 0, 10): 115 err = psp_init_sos_microcode(psp, ucode_prefix); 116 if (err) 117 return err; 118 /* It's not necessary to load ras ta on Guest side */ 119 err = psp_init_ta_microcode(psp, ucode_prefix); 120 if (err) 121 return err; 122 break; 123 default: 124 BUG(); 125 } 126 127 return 0; 128 } 129 130 static bool psp_v13_0_is_sos_alive(struct psp_context *psp) 131 { 132 struct amdgpu_device *adev = psp->adev; 133 uint32_t sol_reg; 134 135 sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81); 136 137 return sol_reg != 0x0; 138 } 139 140 static int psp_v13_0_wait_for_vmbx_ready(struct psp_context *psp) 141 { 142 struct amdgpu_device *adev = psp->adev; 143 int retry_loop, ret; 144 145 for (retry_loop = 0; retry_loop < PSP_VMBX_POLLING_LIMIT; retry_loop++) { 146 /* Wait for bootloader to signify that is 147 ready having bit 31 of C2PMSG_33 set to 1 */ 148 ret = psp_wait_for( 149 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_33), 150 0x80000000, 0xffffffff, false); 151 152 if (ret == 0) 153 break; 154 } 155 156 if (ret) 157 dev_warn(adev->dev, "Bootloader wait timed out"); 158 159 return ret; 160 } 161 162 static int psp_v13_0_wait_for_bootloader(struct psp_context *psp) 163 { 164 struct amdgpu_device *adev = psp->adev; 165 int retry_loop, retry_cnt, ret; 166 167 retry_cnt = 168 (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6)) ? 169 PSP_VMBX_POLLING_LIMIT : 170 10; 171 /* Wait for bootloader to signify that it is ready having bit 31 of 172 * C2PMSG_35 set to 1. All other bits are expected to be cleared. 173 * If there is an error in processing command, bits[7:0] will be set. 174 * This is applicable for PSP v13.0.6 and newer. 175 */ 176 for (retry_loop = 0; retry_loop < retry_cnt; retry_loop++) { 177 ret = psp_wait_for( 178 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 179 0x80000000, 0xffffffff, false); 180 181 if (ret == 0) 182 return 0; 183 } 184 185 return ret; 186 } 187 188 static int psp_v13_0_wait_for_bootloader_steady_state(struct psp_context *psp) 189 { 190 struct amdgpu_device *adev = psp->adev; 191 int ret; 192 193 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6)) { 194 ret = psp_v13_0_wait_for_vmbx_ready(psp); 195 if (ret) 196 amdgpu_ras_query_boot_status(adev, 4); 197 198 ret = psp_v13_0_wait_for_bootloader(psp); 199 if (ret) 200 amdgpu_ras_query_boot_status(adev, 4); 201 202 return ret; 203 } 204 205 return 0; 206 } 207 208 static int psp_v13_0_bootloader_load_component(struct psp_context *psp, 209 struct psp_bin_desc *bin_desc, 210 enum psp_bootloader_cmd bl_cmd) 211 { 212 int ret; 213 uint32_t psp_gfxdrv_command_reg = 0; 214 struct amdgpu_device *adev = psp->adev; 215 216 /* Check tOS sign of life register to confirm sys driver and sOS 217 * are already been loaded. 218 */ 219 if (psp_v13_0_is_sos_alive(psp)) 220 return 0; 221 222 ret = psp_v13_0_wait_for_bootloader(psp); 223 if (ret) 224 return ret; 225 226 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 227 228 /* Copy PSP KDB binary to memory */ 229 memcpy(psp->fw_pri_buf, bin_desc->start_addr, bin_desc->size_bytes); 230 231 /* Provide the PSP KDB to bootloader */ 232 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, 233 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 234 psp_gfxdrv_command_reg = bl_cmd; 235 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, 236 psp_gfxdrv_command_reg); 237 238 ret = psp_v13_0_wait_for_bootloader(psp); 239 240 return ret; 241 } 242 243 static int psp_v13_0_bootloader_load_kdb(struct psp_context *psp) 244 { 245 return psp_v13_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_KEY_DATABASE); 246 } 247 248 static int psp_v13_0_bootloader_load_spl(struct psp_context *psp) 249 { 250 return psp_v13_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_TOS_SPL_TABLE); 251 } 252 253 static int psp_v13_0_bootloader_load_sysdrv(struct psp_context *psp) 254 { 255 return psp_v13_0_bootloader_load_component(psp, &psp->sys, PSP_BL__LOAD_SYSDRV); 256 } 257 258 static int psp_v13_0_bootloader_load_soc_drv(struct psp_context *psp) 259 { 260 return psp_v13_0_bootloader_load_component(psp, &psp->soc_drv, PSP_BL__LOAD_SOCDRV); 261 } 262 263 static int psp_v13_0_bootloader_load_intf_drv(struct psp_context *psp) 264 { 265 return psp_v13_0_bootloader_load_component(psp, &psp->intf_drv, PSP_BL__LOAD_INTFDRV); 266 } 267 268 static int psp_v13_0_bootloader_load_dbg_drv(struct psp_context *psp) 269 { 270 return psp_v13_0_bootloader_load_component(psp, &psp->dbg_drv, PSP_BL__LOAD_DBGDRV); 271 } 272 273 static int psp_v13_0_bootloader_load_ras_drv(struct psp_context *psp) 274 { 275 return psp_v13_0_bootloader_load_component(psp, &psp->ras_drv, PSP_BL__LOAD_RASDRV); 276 } 277 278 static inline void psp_v13_0_init_sos_version(struct psp_context *psp) 279 { 280 struct amdgpu_device *adev = psp->adev; 281 282 psp->sos.fw_version = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_58); 283 } 284 285 static int psp_v13_0_bootloader_load_sos(struct psp_context *psp) 286 { 287 int ret; 288 unsigned int psp_gfxdrv_command_reg = 0; 289 struct amdgpu_device *adev = psp->adev; 290 291 /* Check sOS sign of life register to confirm sys driver and sOS 292 * are already been loaded. 293 */ 294 if (psp_v13_0_is_sos_alive(psp)) { 295 psp_v13_0_init_sos_version(psp); 296 return 0; 297 } 298 299 ret = psp_v13_0_wait_for_bootloader(psp); 300 if (ret) 301 return ret; 302 303 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 304 305 /* Copy Secure OS binary to PSP memory */ 306 memcpy(psp->fw_pri_buf, psp->sos.start_addr, psp->sos.size_bytes); 307 308 /* Provide the PSP secure OS to bootloader */ 309 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, 310 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 311 psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV; 312 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, 313 psp_gfxdrv_command_reg); 314 315 /* there might be handshake issue with hardware which needs delay */ 316 mdelay(20); 317 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_81), 318 RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81), 319 0, true); 320 321 if (!ret) 322 psp_v13_0_init_sos_version(psp); 323 324 return ret; 325 } 326 327 static int psp_v13_0_ring_stop(struct psp_context *psp, 328 enum psp_ring_type ring_type) 329 { 330 int ret = 0; 331 struct amdgpu_device *adev = psp->adev; 332 333 if (amdgpu_sriov_vf(adev)) { 334 /* Write the ring destroy command*/ 335 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, 336 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING); 337 /* there might be handshake issue with hardware which needs delay */ 338 mdelay(20); 339 /* Wait for response flag (bit 31) */ 340 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101), 341 0x80000000, 0x80000000, false); 342 } else { 343 /* Write the ring destroy command*/ 344 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, 345 GFX_CTRL_CMD_ID_DESTROY_RINGS); 346 /* there might be handshake issue with hardware which needs delay */ 347 mdelay(20); 348 /* Wait for response flag (bit 31) */ 349 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), 350 0x80000000, 0x80000000, false); 351 } 352 353 return ret; 354 } 355 356 static int psp_v13_0_ring_create(struct psp_context *psp, 357 enum psp_ring_type ring_type) 358 { 359 int ret = 0; 360 unsigned int psp_ring_reg = 0; 361 struct psp_ring *ring = &psp->km_ring; 362 struct amdgpu_device *adev = psp->adev; 363 364 if (amdgpu_sriov_vf(adev)) { 365 ret = psp_v13_0_ring_stop(psp, ring_type); 366 if (ret) { 367 DRM_ERROR("psp_v13_0_ring_stop_sriov failed!\n"); 368 return ret; 369 } 370 371 /* Write low address of the ring to C2PMSG_102 */ 372 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 373 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, psp_ring_reg); 374 /* Write high address of the ring to C2PMSG_103 */ 375 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 376 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_103, psp_ring_reg); 377 378 /* Write the ring initialization command to C2PMSG_101 */ 379 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, 380 GFX_CTRL_CMD_ID_INIT_GPCOM_RING); 381 382 /* there might be handshake issue with hardware which needs delay */ 383 mdelay(20); 384 385 /* Wait for response flag (bit 31) in C2PMSG_101 */ 386 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101), 387 0x80000000, 0x8000FFFF, false); 388 389 } else { 390 /* Wait for sOS ready for ring creation */ 391 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), 392 0x80000000, 0x80000000, false); 393 if (ret) { 394 DRM_ERROR("Failed to wait for trust OS ready for ring creation\n"); 395 return ret; 396 } 397 398 /* Write low address of the ring to C2PMSG_69 */ 399 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 400 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_69, psp_ring_reg); 401 /* Write high address of the ring to C2PMSG_70 */ 402 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 403 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_70, psp_ring_reg); 404 /* Write size of ring to C2PMSG_71 */ 405 psp_ring_reg = ring->ring_size; 406 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_71, psp_ring_reg); 407 /* Write the ring initialization command to C2PMSG_64 */ 408 psp_ring_reg = ring_type; 409 psp_ring_reg = psp_ring_reg << 16; 410 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, psp_ring_reg); 411 412 /* there might be handshake issue with hardware which needs delay */ 413 mdelay(20); 414 415 /* Wait for response flag (bit 31) in C2PMSG_64 */ 416 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), 417 0x80000000, 0x8000FFFF, false); 418 } 419 420 return ret; 421 } 422 423 static int psp_v13_0_ring_destroy(struct psp_context *psp, 424 enum psp_ring_type ring_type) 425 { 426 int ret = 0; 427 struct psp_ring *ring = &psp->km_ring; 428 struct amdgpu_device *adev = psp->adev; 429 430 ret = psp_v13_0_ring_stop(psp, ring_type); 431 if (ret) 432 DRM_ERROR("Fail to stop psp ring\n"); 433 434 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 435 &ring->ring_mem_mc_addr, 436 (void **)&ring->ring_mem); 437 438 return ret; 439 } 440 441 static uint32_t psp_v13_0_ring_get_wptr(struct psp_context *psp) 442 { 443 uint32_t data; 444 struct amdgpu_device *adev = psp->adev; 445 446 if (amdgpu_sriov_vf(adev)) 447 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102); 448 else 449 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67); 450 451 return data; 452 } 453 454 static void psp_v13_0_ring_set_wptr(struct psp_context *psp, uint32_t value) 455 { 456 struct amdgpu_device *adev = psp->adev; 457 458 if (amdgpu_sriov_vf(adev)) { 459 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, value); 460 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, 461 GFX_CTRL_CMD_ID_CONSUME_CMD); 462 } else 463 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67, value); 464 } 465 466 static int psp_v13_0_memory_training_send_msg(struct psp_context *psp, int msg) 467 { 468 int ret; 469 int i; 470 uint32_t data_32; 471 int max_wait; 472 struct amdgpu_device *adev = psp->adev; 473 474 data_32 = (psp->mem_train_ctx.c2p_train_data_offset >> 20); 475 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, data_32); 476 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, msg); 477 478 max_wait = MEM_TRAIN_SEND_MSG_TIMEOUT_US / adev->usec_timeout; 479 for (i = 0; i < max_wait; i++) { 480 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 481 0x80000000, 0x80000000, false); 482 if (ret == 0) 483 break; 484 } 485 if (i < max_wait) 486 ret = 0; 487 else 488 ret = -ETIME; 489 490 dev_dbg(adev->dev, "training %s %s, cost %d @ %d ms\n", 491 (msg == PSP_BL__DRAM_SHORT_TRAIN) ? "short" : "long", 492 (ret == 0) ? "succeed" : "failed", 493 i, adev->usec_timeout/1000); 494 return ret; 495 } 496 497 498 static int psp_v13_0_memory_training(struct psp_context *psp, uint32_t ops) 499 { 500 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 501 uint32_t *pcache = (uint32_t *)ctx->sys_cache; 502 struct amdgpu_device *adev = psp->adev; 503 uint32_t p2c_header[4]; 504 uint32_t sz; 505 void *buf; 506 int ret, idx; 507 508 if (ctx->init == PSP_MEM_TRAIN_NOT_SUPPORT) { 509 dev_dbg(adev->dev, "Memory training is not supported.\n"); 510 return 0; 511 } else if (ctx->init != PSP_MEM_TRAIN_INIT_SUCCESS) { 512 dev_err(adev->dev, "Memory training initialization failure.\n"); 513 return -EINVAL; 514 } 515 516 if (psp_v13_0_is_sos_alive(psp)) { 517 dev_dbg(adev->dev, "SOS is alive, skip memory training.\n"); 518 return 0; 519 } 520 521 amdgpu_device_vram_access(adev, ctx->p2c_train_data_offset, p2c_header, sizeof(p2c_header), false); 522 dev_dbg(adev->dev, "sys_cache[%08x,%08x,%08x,%08x] p2c_header[%08x,%08x,%08x,%08x]\n", 523 pcache[0], pcache[1], pcache[2], pcache[3], 524 p2c_header[0], p2c_header[1], p2c_header[2], p2c_header[3]); 525 526 if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) { 527 dev_dbg(adev->dev, "Short training depends on restore.\n"); 528 ops |= PSP_MEM_TRAIN_RESTORE; 529 } 530 531 if ((ops & PSP_MEM_TRAIN_RESTORE) && 532 pcache[0] != MEM_TRAIN_SYSTEM_SIGNATURE) { 533 dev_dbg(adev->dev, "sys_cache[0] is invalid, restore depends on save.\n"); 534 ops |= PSP_MEM_TRAIN_SAVE; 535 } 536 537 if (p2c_header[0] == MEM_TRAIN_SYSTEM_SIGNATURE && 538 !(pcache[0] == MEM_TRAIN_SYSTEM_SIGNATURE && 539 pcache[3] == p2c_header[3])) { 540 dev_dbg(adev->dev, "sys_cache is invalid or out-of-date, need save training data to sys_cache.\n"); 541 ops |= PSP_MEM_TRAIN_SAVE; 542 } 543 544 if ((ops & PSP_MEM_TRAIN_SAVE) && 545 p2c_header[0] != MEM_TRAIN_SYSTEM_SIGNATURE) { 546 dev_dbg(adev->dev, "p2c_header[0] is invalid, save depends on long training.\n"); 547 ops |= PSP_MEM_TRAIN_SEND_LONG_MSG; 548 } 549 550 if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) { 551 ops &= ~PSP_MEM_TRAIN_SEND_SHORT_MSG; 552 ops |= PSP_MEM_TRAIN_SAVE; 553 } 554 555 dev_dbg(adev->dev, "Memory training ops:%x.\n", ops); 556 557 if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) { 558 /* 559 * Long training will encroach a certain amount on the bottom of VRAM; 560 * save the content from the bottom of VRAM to system memory 561 * before training, and restore it after training to avoid 562 * VRAM corruption. 563 */ 564 sz = GDDR6_MEM_TRAINING_ENCROACHED_SIZE; 565 566 if (adev->gmc.visible_vram_size < sz || !adev->mman.aper_base_kaddr) { 567 dev_err(adev->dev, "visible_vram_size %llx or aper_base_kaddr %p is not initialized.\n", 568 adev->gmc.visible_vram_size, 569 adev->mman.aper_base_kaddr); 570 return -EINVAL; 571 } 572 573 buf = vmalloc(sz); 574 if (!buf) { 575 dev_err(adev->dev, "failed to allocate system memory.\n"); 576 return -ENOMEM; 577 } 578 579 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 580 memcpy_fromio(buf, adev->mman.aper_base_kaddr, sz); 581 ret = psp_v13_0_memory_training_send_msg(psp, PSP_BL__DRAM_LONG_TRAIN); 582 if (ret) { 583 DRM_ERROR("Send long training msg failed.\n"); 584 vfree(buf); 585 drm_dev_exit(idx); 586 return ret; 587 } 588 589 memcpy_toio(adev->mman.aper_base_kaddr, buf, sz); 590 adev->hdp.funcs->flush_hdp(adev, NULL); 591 vfree(buf); 592 drm_dev_exit(idx); 593 } else { 594 vfree(buf); 595 return -ENODEV; 596 } 597 } 598 599 if (ops & PSP_MEM_TRAIN_SAVE) { 600 amdgpu_device_vram_access(psp->adev, ctx->p2c_train_data_offset, ctx->sys_cache, ctx->train_data_size, false); 601 } 602 603 if (ops & PSP_MEM_TRAIN_RESTORE) { 604 amdgpu_device_vram_access(psp->adev, ctx->c2p_train_data_offset, ctx->sys_cache, ctx->train_data_size, true); 605 } 606 607 if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) { 608 ret = psp_v13_0_memory_training_send_msg(psp, (amdgpu_force_long_training > 0) ? 609 PSP_BL__DRAM_LONG_TRAIN : PSP_BL__DRAM_SHORT_TRAIN); 610 if (ret) { 611 dev_err(adev->dev, "send training msg failed.\n"); 612 return ret; 613 } 614 } 615 ctx->training_cnt++; 616 return 0; 617 } 618 619 static int psp_v13_0_load_usbc_pd_fw(struct psp_context *psp, uint64_t fw_pri_mc_addr) 620 { 621 struct amdgpu_device *adev = psp->adev; 622 uint32_t reg_status; 623 int ret, i = 0; 624 625 /* 626 * LFB address which is aligned to 1MB address and has to be 627 * right-shifted by 20 so that LFB address can be passed on a 32-bit C2P 628 * register 629 */ 630 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, (fw_pri_mc_addr >> 20)); 631 632 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 633 0x80000000, 0x80000000, false); 634 if (ret) 635 return ret; 636 637 /* Fireup interrupt so PSP can pick up the address */ 638 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, (GFX_CMD_USB_PD_USE_LFB << 16)); 639 640 /* FW load takes very long time */ 641 do { 642 msleep(1000); 643 reg_status = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35); 644 645 if (reg_status & 0x80000000) 646 goto done; 647 648 } while (++i < USBC_PD_POLLING_LIMIT_S); 649 650 return -ETIME; 651 done: 652 653 if ((reg_status & 0xFFFF) != 0) { 654 DRM_ERROR("Address load failed - MP0_SMN_C2PMSG_35.Bits [15:0] = %04x\n", 655 reg_status & 0xFFFF); 656 return -EIO; 657 } 658 659 return 0; 660 } 661 662 static int psp_v13_0_read_usbc_pd_fw(struct psp_context *psp, uint32_t *fw_ver) 663 { 664 struct amdgpu_device *adev = psp->adev; 665 int ret; 666 667 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, C2PMSG_CMD_GFX_USB_PD_FW_VER); 668 669 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 670 0x80000000, 0x80000000, false); 671 if (!ret) 672 *fw_ver = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36); 673 674 return ret; 675 } 676 677 static int psp_v13_0_exec_spi_cmd(struct psp_context *psp, int cmd) 678 { 679 uint32_t reg_status = 0, reg_val = 0; 680 struct amdgpu_device *adev = psp->adev; 681 int ret; 682 683 /* clear MBX ready (MBOX_READY_MASK bit is 0) and set update command */ 684 reg_val |= (cmd << 16); 685 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115, reg_val); 686 687 /* Ring the doorbell */ 688 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_73, 1); 689 690 if (cmd == C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE) 691 ret = psp_wait_for_spirom_update(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115), 692 MBOX_READY_FLAG, MBOX_READY_MASK, PSP_SPIROM_UPDATE_TIMEOUT); 693 else 694 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115), 695 MBOX_READY_FLAG, MBOX_READY_MASK, false); 696 if (ret) { 697 dev_err(adev->dev, "SPI cmd %x timed out, ret = %d", cmd, ret); 698 return ret; 699 } 700 701 reg_status = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115); 702 if ((reg_status & 0xFFFF) != 0) { 703 dev_err(adev->dev, "SPI cmd %x failed, fail status = %04x\n", 704 cmd, reg_status & 0xFFFF); 705 return -EIO; 706 } 707 708 return 0; 709 } 710 711 static int psp_v13_0_update_spirom(struct psp_context *psp, 712 uint64_t fw_pri_mc_addr) 713 { 714 struct amdgpu_device *adev = psp->adev; 715 int ret; 716 717 /* Confirm PSP is ready to start */ 718 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115), 719 MBOX_READY_FLAG, MBOX_READY_MASK, false); 720 if (ret) { 721 dev_err(adev->dev, "PSP Not ready to start processing, ret = %d", ret); 722 return ret; 723 } 724 725 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, lower_32_bits(fw_pri_mc_addr)); 726 727 ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_LO); 728 if (ret) 729 return ret; 730 731 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, upper_32_bits(fw_pri_mc_addr)); 732 733 ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI); 734 if (ret) 735 return ret; 736 737 psp->vbflash_done = true; 738 739 ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE); 740 if (ret) 741 return ret; 742 743 return 0; 744 } 745 746 static int psp_v13_0_vbflash_status(struct psp_context *psp) 747 { 748 struct amdgpu_device *adev = psp->adev; 749 750 return RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115); 751 } 752 753 static int psp_v13_0_fatal_error_recovery_quirk(struct psp_context *psp) 754 { 755 struct amdgpu_device *adev = psp->adev; 756 757 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 10)) { 758 uint32_t reg_data; 759 /* MP1 fatal error: trigger PSP dram read to unhalt PSP 760 * during MP1 triggered sync flood. 761 */ 762 reg_data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67); 763 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67, reg_data + 0x10); 764 765 /* delay 1000ms for the mode1 reset for fatal error 766 * to be recovered back. 767 */ 768 msleep(1000); 769 } 770 771 return 0; 772 } 773 774 static bool psp_v13_0_get_ras_capability(struct psp_context *psp) 775 { 776 struct amdgpu_device *adev = psp->adev; 777 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 778 u32 reg_data; 779 780 /* query ras cap should be done from host side */ 781 if (amdgpu_sriov_vf(adev)) 782 return false; 783 784 if (!con) 785 return false; 786 787 if ((amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6)) && 788 (!(adev->flags & AMD_IS_APU))) { 789 reg_data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_127); 790 adev->ras_hw_enabled = (reg_data & GENMASK_ULL(23, 0)); 791 con->poison_supported = ((reg_data & GENMASK_ULL(24, 24)) >> 24) ? true : false; 792 return true; 793 } else { 794 return false; 795 } 796 } 797 798 static const struct psp_funcs psp_v13_0_funcs = { 799 .init_microcode = psp_v13_0_init_microcode, 800 .wait_for_bootloader = psp_v13_0_wait_for_bootloader_steady_state, 801 .bootloader_load_kdb = psp_v13_0_bootloader_load_kdb, 802 .bootloader_load_spl = psp_v13_0_bootloader_load_spl, 803 .bootloader_load_sysdrv = psp_v13_0_bootloader_load_sysdrv, 804 .bootloader_load_soc_drv = psp_v13_0_bootloader_load_soc_drv, 805 .bootloader_load_intf_drv = psp_v13_0_bootloader_load_intf_drv, 806 .bootloader_load_dbg_drv = psp_v13_0_bootloader_load_dbg_drv, 807 .bootloader_load_ras_drv = psp_v13_0_bootloader_load_ras_drv, 808 .bootloader_load_sos = psp_v13_0_bootloader_load_sos, 809 .ring_create = psp_v13_0_ring_create, 810 .ring_stop = psp_v13_0_ring_stop, 811 .ring_destroy = psp_v13_0_ring_destroy, 812 .ring_get_wptr = psp_v13_0_ring_get_wptr, 813 .ring_set_wptr = psp_v13_0_ring_set_wptr, 814 .mem_training = psp_v13_0_memory_training, 815 .load_usbc_pd_fw = psp_v13_0_load_usbc_pd_fw, 816 .read_usbc_pd_fw = psp_v13_0_read_usbc_pd_fw, 817 .update_spirom = psp_v13_0_update_spirom, 818 .vbflash_stat = psp_v13_0_vbflash_status, 819 .fatal_error_recovery_quirk = psp_v13_0_fatal_error_recovery_quirk, 820 .get_ras_capability = psp_v13_0_get_ras_capability, 821 }; 822 823 void psp_v13_0_set_psp_funcs(struct psp_context *psp) 824 { 825 psp->funcs = &psp_v13_0_funcs; 826 } 827