1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <drm/drm_drv.h> 24 #include <linux/vmalloc.h> 25 #include "amdgpu.h" 26 #include "amdgpu_psp.h" 27 #include "amdgpu_ucode.h" 28 #include "soc15_common.h" 29 #include "psp_v13_0.h" 30 #include "amdgpu_ras.h" 31 32 #include "mp/mp_13_0_2_offset.h" 33 #include "mp/mp_13_0_2_sh_mask.h" 34 35 MODULE_FIRMWARE("amdgpu/aldebaran_sos.bin"); 36 MODULE_FIRMWARE("amdgpu/aldebaran_ta.bin"); 37 MODULE_FIRMWARE("amdgpu/aldebaran_cap.bin"); 38 MODULE_FIRMWARE("amdgpu/yellow_carp_toc.bin"); 39 MODULE_FIRMWARE("amdgpu/yellow_carp_ta.bin"); 40 MODULE_FIRMWARE("amdgpu/psp_13_0_5_toc.bin"); 41 MODULE_FIRMWARE("amdgpu/psp_13_0_5_ta.bin"); 42 MODULE_FIRMWARE("amdgpu/psp_13_0_8_toc.bin"); 43 MODULE_FIRMWARE("amdgpu/psp_13_0_8_ta.bin"); 44 MODULE_FIRMWARE("amdgpu/psp_13_0_0_sos.bin"); 45 MODULE_FIRMWARE("amdgpu/psp_13_0_0_ta.bin"); 46 MODULE_FIRMWARE("amdgpu/psp_13_0_7_sos.bin"); 47 MODULE_FIRMWARE("amdgpu/psp_13_0_7_ta.bin"); 48 MODULE_FIRMWARE("amdgpu/psp_13_0_10_sos.bin"); 49 MODULE_FIRMWARE("amdgpu/psp_13_0_10_ta.bin"); 50 MODULE_FIRMWARE("amdgpu/psp_13_0_11_toc.bin"); 51 MODULE_FIRMWARE("amdgpu/psp_13_0_11_ta.bin"); 52 MODULE_FIRMWARE("amdgpu/psp_13_0_6_sos.bin"); 53 MODULE_FIRMWARE("amdgpu/psp_13_0_6_ta.bin"); 54 MODULE_FIRMWARE("amdgpu/psp_13_0_14_sos.bin"); 55 MODULE_FIRMWARE("amdgpu/psp_13_0_14_ta.bin"); 56 MODULE_FIRMWARE("amdgpu/psp_14_0_0_toc.bin"); 57 MODULE_FIRMWARE("amdgpu/psp_14_0_0_ta.bin"); 58 MODULE_FIRMWARE("amdgpu/psp_14_0_1_toc.bin"); 59 MODULE_FIRMWARE("amdgpu/psp_14_0_1_ta.bin"); 60 MODULE_FIRMWARE("amdgpu/psp_14_0_4_toc.bin"); 61 MODULE_FIRMWARE("amdgpu/psp_14_0_4_ta.bin"); 62 63 /* For large FW files the time to complete can be very long */ 64 #define USBC_PD_POLLING_LIMIT_S 240 65 66 /* Read USB-PD from LFB */ 67 #define GFX_CMD_USB_PD_USE_LFB 0x480 68 69 /* Retry times for vmbx ready wait */ 70 #define PSP_VMBX_POLLING_LIMIT 3000 71 72 /* VBIOS gfl defines */ 73 #define MBOX_READY_MASK 0x80000000 74 #define MBOX_STATUS_MASK 0x0000FFFF 75 #define MBOX_COMMAND_MASK 0x00FF0000 76 #define MBOX_READY_FLAG 0x80000000 77 #define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_LO 0x2 78 #define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI 0x3 79 #define C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE 0x4 80 81 /* memory training timeout define */ 82 #define MEM_TRAIN_SEND_MSG_TIMEOUT_US 3000000 83 84 #define regMP1_PUB_SCRATCH0 0x3b10090 85 86 static int psp_v13_0_init_microcode(struct psp_context *psp) 87 { 88 struct amdgpu_device *adev = psp->adev; 89 char ucode_prefix[30]; 90 int err = 0; 91 92 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); 93 94 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 95 case IP_VERSION(13, 0, 2): 96 err = psp_init_sos_microcode(psp, ucode_prefix); 97 if (err) 98 return err; 99 /* It's not necessary to load ras ta on Guest side */ 100 if (!amdgpu_sriov_vf(adev)) { 101 err = psp_init_ta_microcode(psp, ucode_prefix); 102 if (err) 103 return err; 104 } 105 break; 106 case IP_VERSION(13, 0, 1): 107 case IP_VERSION(13, 0, 3): 108 case IP_VERSION(13, 0, 5): 109 case IP_VERSION(13, 0, 8): 110 case IP_VERSION(13, 0, 11): 111 case IP_VERSION(14, 0, 0): 112 case IP_VERSION(14, 0, 1): 113 case IP_VERSION(14, 0, 4): 114 err = psp_init_toc_microcode(psp, ucode_prefix); 115 if (err) 116 return err; 117 err = psp_init_ta_microcode(psp, ucode_prefix); 118 if (err) 119 return err; 120 break; 121 case IP_VERSION(13, 0, 0): 122 case IP_VERSION(13, 0, 6): 123 case IP_VERSION(13, 0, 7): 124 case IP_VERSION(13, 0, 10): 125 case IP_VERSION(13, 0, 14): 126 err = psp_init_sos_microcode(psp, ucode_prefix); 127 if (err) 128 return err; 129 /* It's not necessary to load ras ta on Guest side */ 130 err = psp_init_ta_microcode(psp, ucode_prefix); 131 if (err) 132 return err; 133 break; 134 default: 135 BUG(); 136 } 137 138 return 0; 139 } 140 141 static bool psp_v13_0_is_sos_alive(struct psp_context *psp) 142 { 143 struct amdgpu_device *adev = psp->adev; 144 uint32_t sol_reg; 145 146 sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81); 147 148 return sol_reg != 0x0; 149 } 150 151 static int psp_v13_0_wait_for_vmbx_ready(struct psp_context *psp) 152 { 153 struct amdgpu_device *adev = psp->adev; 154 int retry_loop, ret; 155 156 for (retry_loop = 0; retry_loop < PSP_VMBX_POLLING_LIMIT; retry_loop++) { 157 /* Wait for bootloader to signify that is 158 ready having bit 31 of C2PMSG_33 set to 1 */ 159 ret = psp_wait_for( 160 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_33), 161 0x80000000, 0xffffffff, false); 162 163 if (ret == 0) 164 break; 165 } 166 167 if (ret) 168 dev_warn(adev->dev, "Bootloader wait timed out"); 169 170 return ret; 171 } 172 173 static int psp_v13_0_wait_for_bootloader(struct psp_context *psp) 174 { 175 struct amdgpu_device *adev = psp->adev; 176 int retry_loop, retry_cnt, ret; 177 178 retry_cnt = 179 ((amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) || 180 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14))) ? 181 PSP_VMBX_POLLING_LIMIT : 182 10; 183 /* Wait for bootloader to signify that it is ready having bit 31 of 184 * C2PMSG_35 set to 1. All other bits are expected to be cleared. 185 * If there is an error in processing command, bits[7:0] will be set. 186 * This is applicable for PSP v13.0.6 and newer. 187 */ 188 for (retry_loop = 0; retry_loop < retry_cnt; retry_loop++) { 189 ret = psp_wait_for( 190 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 191 0x80000000, 0xffffffff, false); 192 193 if (ret == 0) 194 return 0; 195 } 196 197 return ret; 198 } 199 200 static int psp_v13_0_wait_for_bootloader_steady_state(struct psp_context *psp) 201 { 202 struct amdgpu_device *adev = psp->adev; 203 int ret; 204 205 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) || 206 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14)) { 207 ret = psp_v13_0_wait_for_vmbx_ready(psp); 208 if (ret) 209 amdgpu_ras_query_boot_status(adev, 4); 210 211 ret = psp_v13_0_wait_for_bootloader(psp); 212 if (ret) 213 amdgpu_ras_query_boot_status(adev, 4); 214 215 return ret; 216 } 217 218 return 0; 219 } 220 221 static int psp_v13_0_bootloader_load_component(struct psp_context *psp, 222 struct psp_bin_desc *bin_desc, 223 enum psp_bootloader_cmd bl_cmd) 224 { 225 int ret; 226 uint32_t psp_gfxdrv_command_reg = 0; 227 struct amdgpu_device *adev = psp->adev; 228 229 /* Check tOS sign of life register to confirm sys driver and sOS 230 * are already been loaded. 231 */ 232 if (psp_v13_0_is_sos_alive(psp)) 233 return 0; 234 235 ret = psp_v13_0_wait_for_bootloader(psp); 236 if (ret) 237 return ret; 238 239 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 240 241 /* Copy PSP KDB binary to memory */ 242 memcpy(psp->fw_pri_buf, bin_desc->start_addr, bin_desc->size_bytes); 243 244 /* Provide the PSP KDB to bootloader */ 245 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, 246 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 247 psp_gfxdrv_command_reg = bl_cmd; 248 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, 249 psp_gfxdrv_command_reg); 250 251 ret = psp_v13_0_wait_for_bootloader(psp); 252 253 return ret; 254 } 255 256 static int psp_v13_0_bootloader_load_kdb(struct psp_context *psp) 257 { 258 return psp_v13_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_KEY_DATABASE); 259 } 260 261 static int psp_v13_0_bootloader_load_spl(struct psp_context *psp) 262 { 263 return psp_v13_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_TOS_SPL_TABLE); 264 } 265 266 static int psp_v13_0_bootloader_load_sysdrv(struct psp_context *psp) 267 { 268 return psp_v13_0_bootloader_load_component(psp, &psp->sys, PSP_BL__LOAD_SYSDRV); 269 } 270 271 static int psp_v13_0_bootloader_load_soc_drv(struct psp_context *psp) 272 { 273 return psp_v13_0_bootloader_load_component(psp, &psp->soc_drv, PSP_BL__LOAD_SOCDRV); 274 } 275 276 static int psp_v13_0_bootloader_load_intf_drv(struct psp_context *psp) 277 { 278 return psp_v13_0_bootloader_load_component(psp, &psp->intf_drv, PSP_BL__LOAD_INTFDRV); 279 } 280 281 static int psp_v13_0_bootloader_load_dbg_drv(struct psp_context *psp) 282 { 283 return psp_v13_0_bootloader_load_component(psp, &psp->dbg_drv, PSP_BL__LOAD_DBGDRV); 284 } 285 286 static int psp_v13_0_bootloader_load_ras_drv(struct psp_context *psp) 287 { 288 return psp_v13_0_bootloader_load_component(psp, &psp->ras_drv, PSP_BL__LOAD_RASDRV); 289 } 290 291 static inline void psp_v13_0_init_sos_version(struct psp_context *psp) 292 { 293 struct amdgpu_device *adev = psp->adev; 294 295 psp->sos.fw_version = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_58); 296 } 297 298 static int psp_v13_0_bootloader_load_sos(struct psp_context *psp) 299 { 300 int ret; 301 unsigned int psp_gfxdrv_command_reg = 0; 302 struct amdgpu_device *adev = psp->adev; 303 304 /* Check sOS sign of life register to confirm sys driver and sOS 305 * are already been loaded. 306 */ 307 if (psp_v13_0_is_sos_alive(psp)) { 308 psp_v13_0_init_sos_version(psp); 309 return 0; 310 } 311 312 ret = psp_v13_0_wait_for_bootloader(psp); 313 if (ret) 314 return ret; 315 316 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 317 318 /* Copy Secure OS binary to PSP memory */ 319 memcpy(psp->fw_pri_buf, psp->sos.start_addr, psp->sos.size_bytes); 320 321 /* Provide the PSP secure OS to bootloader */ 322 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, 323 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 324 psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV; 325 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, 326 psp_gfxdrv_command_reg); 327 328 /* there might be handshake issue with hardware which needs delay */ 329 mdelay(20); 330 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_81), 331 RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81), 332 0, true); 333 334 if (!ret) 335 psp_v13_0_init_sos_version(psp); 336 337 return ret; 338 } 339 340 static int psp_v13_0_ring_stop(struct psp_context *psp, 341 enum psp_ring_type ring_type) 342 { 343 int ret = 0; 344 struct amdgpu_device *adev = psp->adev; 345 346 if (amdgpu_sriov_vf(adev)) { 347 /* Write the ring destroy command*/ 348 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, 349 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING); 350 /* there might be handshake issue with hardware which needs delay */ 351 mdelay(20); 352 /* Wait for response flag (bit 31) */ 353 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101), 354 0x80000000, 0x80000000, false); 355 } else { 356 /* Write the ring destroy command*/ 357 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, 358 GFX_CTRL_CMD_ID_DESTROY_RINGS); 359 /* there might be handshake issue with hardware which needs delay */ 360 mdelay(20); 361 /* Wait for response flag (bit 31) */ 362 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), 363 0x80000000, 0x80000000, false); 364 } 365 366 return ret; 367 } 368 369 static int psp_v13_0_ring_create(struct psp_context *psp, 370 enum psp_ring_type ring_type) 371 { 372 int ret = 0; 373 unsigned int psp_ring_reg = 0; 374 struct psp_ring *ring = &psp->km_ring; 375 struct amdgpu_device *adev = psp->adev; 376 377 if (amdgpu_sriov_vf(adev)) { 378 ret = psp_v13_0_ring_stop(psp, ring_type); 379 if (ret) { 380 DRM_ERROR("psp_v13_0_ring_stop_sriov failed!\n"); 381 return ret; 382 } 383 384 /* Write low address of the ring to C2PMSG_102 */ 385 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 386 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, psp_ring_reg); 387 /* Write high address of the ring to C2PMSG_103 */ 388 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 389 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_103, psp_ring_reg); 390 391 /* Write the ring initialization command to C2PMSG_101 */ 392 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, 393 GFX_CTRL_CMD_ID_INIT_GPCOM_RING); 394 395 /* there might be handshake issue with hardware which needs delay */ 396 mdelay(20); 397 398 /* Wait for response flag (bit 31) in C2PMSG_101 */ 399 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101), 400 0x80000000, 0x8000FFFF, false); 401 402 } else { 403 /* Wait for sOS ready for ring creation */ 404 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), 405 0x80000000, 0x80000000, false); 406 if (ret) { 407 DRM_ERROR("Failed to wait for trust OS ready for ring creation\n"); 408 return ret; 409 } 410 411 /* Write low address of the ring to C2PMSG_69 */ 412 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 413 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_69, psp_ring_reg); 414 /* Write high address of the ring to C2PMSG_70 */ 415 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 416 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_70, psp_ring_reg); 417 /* Write size of ring to C2PMSG_71 */ 418 psp_ring_reg = ring->ring_size; 419 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_71, psp_ring_reg); 420 /* Write the ring initialization command to C2PMSG_64 */ 421 psp_ring_reg = ring_type; 422 psp_ring_reg = psp_ring_reg << 16; 423 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, psp_ring_reg); 424 425 /* there might be handshake issue with hardware which needs delay */ 426 mdelay(20); 427 428 /* Wait for response flag (bit 31) in C2PMSG_64 */ 429 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), 430 0x80000000, 0x8000FFFF, false); 431 } 432 433 return ret; 434 } 435 436 static int psp_v13_0_ring_destroy(struct psp_context *psp, 437 enum psp_ring_type ring_type) 438 { 439 int ret = 0; 440 struct psp_ring *ring = &psp->km_ring; 441 struct amdgpu_device *adev = psp->adev; 442 443 ret = psp_v13_0_ring_stop(psp, ring_type); 444 if (ret) 445 DRM_ERROR("Fail to stop psp ring\n"); 446 447 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 448 &ring->ring_mem_mc_addr, 449 (void **)&ring->ring_mem); 450 451 return ret; 452 } 453 454 static uint32_t psp_v13_0_ring_get_wptr(struct psp_context *psp) 455 { 456 uint32_t data; 457 struct amdgpu_device *adev = psp->adev; 458 459 if (amdgpu_sriov_vf(adev)) 460 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102); 461 else 462 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67); 463 464 return data; 465 } 466 467 static void psp_v13_0_ring_set_wptr(struct psp_context *psp, uint32_t value) 468 { 469 struct amdgpu_device *adev = psp->adev; 470 471 if (amdgpu_sriov_vf(adev)) { 472 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, value); 473 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, 474 GFX_CTRL_CMD_ID_CONSUME_CMD); 475 } else 476 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67, value); 477 } 478 479 static int psp_v13_0_memory_training_send_msg(struct psp_context *psp, int msg) 480 { 481 int ret; 482 int i; 483 uint32_t data_32; 484 int max_wait; 485 struct amdgpu_device *adev = psp->adev; 486 487 data_32 = (psp->mem_train_ctx.c2p_train_data_offset >> 20); 488 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, data_32); 489 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, msg); 490 491 max_wait = MEM_TRAIN_SEND_MSG_TIMEOUT_US / adev->usec_timeout; 492 for (i = 0; i < max_wait; i++) { 493 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 494 0x80000000, 0x80000000, false); 495 if (ret == 0) 496 break; 497 } 498 if (i < max_wait) 499 ret = 0; 500 else 501 ret = -ETIME; 502 503 dev_dbg(adev->dev, "training %s %s, cost %d @ %d ms\n", 504 (msg == PSP_BL__DRAM_SHORT_TRAIN) ? "short" : "long", 505 (ret == 0) ? "succeed" : "failed", 506 i, adev->usec_timeout/1000); 507 return ret; 508 } 509 510 511 static int psp_v13_0_memory_training(struct psp_context *psp, uint32_t ops) 512 { 513 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 514 uint32_t *pcache = (uint32_t *)ctx->sys_cache; 515 struct amdgpu_device *adev = psp->adev; 516 uint32_t p2c_header[4]; 517 uint32_t sz; 518 void *buf; 519 int ret, idx; 520 521 if (ctx->init == PSP_MEM_TRAIN_NOT_SUPPORT) { 522 dev_dbg(adev->dev, "Memory training is not supported.\n"); 523 return 0; 524 } else if (ctx->init != PSP_MEM_TRAIN_INIT_SUCCESS) { 525 dev_err(adev->dev, "Memory training initialization failure.\n"); 526 return -EINVAL; 527 } 528 529 if (psp_v13_0_is_sos_alive(psp)) { 530 dev_dbg(adev->dev, "SOS is alive, skip memory training.\n"); 531 return 0; 532 } 533 534 amdgpu_device_vram_access(adev, ctx->p2c_train_data_offset, p2c_header, sizeof(p2c_header), false); 535 dev_dbg(adev->dev, "sys_cache[%08x,%08x,%08x,%08x] p2c_header[%08x,%08x,%08x,%08x]\n", 536 pcache[0], pcache[1], pcache[2], pcache[3], 537 p2c_header[0], p2c_header[1], p2c_header[2], p2c_header[3]); 538 539 if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) { 540 dev_dbg(adev->dev, "Short training depends on restore.\n"); 541 ops |= PSP_MEM_TRAIN_RESTORE; 542 } 543 544 if ((ops & PSP_MEM_TRAIN_RESTORE) && 545 pcache[0] != MEM_TRAIN_SYSTEM_SIGNATURE) { 546 dev_dbg(adev->dev, "sys_cache[0] is invalid, restore depends on save.\n"); 547 ops |= PSP_MEM_TRAIN_SAVE; 548 } 549 550 if (p2c_header[0] == MEM_TRAIN_SYSTEM_SIGNATURE && 551 !(pcache[0] == MEM_TRAIN_SYSTEM_SIGNATURE && 552 pcache[3] == p2c_header[3])) { 553 dev_dbg(adev->dev, "sys_cache is invalid or out-of-date, need save training data to sys_cache.\n"); 554 ops |= PSP_MEM_TRAIN_SAVE; 555 } 556 557 if ((ops & PSP_MEM_TRAIN_SAVE) && 558 p2c_header[0] != MEM_TRAIN_SYSTEM_SIGNATURE) { 559 dev_dbg(adev->dev, "p2c_header[0] is invalid, save depends on long training.\n"); 560 ops |= PSP_MEM_TRAIN_SEND_LONG_MSG; 561 } 562 563 if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) { 564 ops &= ~PSP_MEM_TRAIN_SEND_SHORT_MSG; 565 ops |= PSP_MEM_TRAIN_SAVE; 566 } 567 568 dev_dbg(adev->dev, "Memory training ops:%x.\n", ops); 569 570 if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) { 571 /* 572 * Long training will encroach a certain amount on the bottom of VRAM; 573 * save the content from the bottom of VRAM to system memory 574 * before training, and restore it after training to avoid 575 * VRAM corruption. 576 */ 577 sz = BIST_MEM_TRAINING_ENCROACHED_SIZE; 578 579 if (adev->gmc.visible_vram_size < sz || !adev->mman.aper_base_kaddr) { 580 dev_err(adev->dev, "visible_vram_size %llx or aper_base_kaddr %p is not initialized.\n", 581 adev->gmc.visible_vram_size, 582 adev->mman.aper_base_kaddr); 583 return -EINVAL; 584 } 585 586 buf = vmalloc(sz); 587 if (!buf) { 588 dev_err(adev->dev, "failed to allocate system memory.\n"); 589 return -ENOMEM; 590 } 591 592 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 593 memcpy_fromio(buf, adev->mman.aper_base_kaddr, sz); 594 ret = psp_v13_0_memory_training_send_msg(psp, PSP_BL__DRAM_LONG_TRAIN); 595 if (ret) { 596 DRM_ERROR("Send long training msg failed.\n"); 597 vfree(buf); 598 drm_dev_exit(idx); 599 return ret; 600 } 601 602 memcpy_toio(adev->mman.aper_base_kaddr, buf, sz); 603 adev->hdp.funcs->flush_hdp(adev, NULL); 604 vfree(buf); 605 drm_dev_exit(idx); 606 } else { 607 vfree(buf); 608 return -ENODEV; 609 } 610 } 611 612 if (ops & PSP_MEM_TRAIN_SAVE) { 613 amdgpu_device_vram_access(psp->adev, ctx->p2c_train_data_offset, ctx->sys_cache, ctx->train_data_size, false); 614 } 615 616 if (ops & PSP_MEM_TRAIN_RESTORE) { 617 amdgpu_device_vram_access(psp->adev, ctx->c2p_train_data_offset, ctx->sys_cache, ctx->train_data_size, true); 618 } 619 620 if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) { 621 ret = psp_v13_0_memory_training_send_msg(psp, (amdgpu_force_long_training > 0) ? 622 PSP_BL__DRAM_LONG_TRAIN : PSP_BL__DRAM_SHORT_TRAIN); 623 if (ret) { 624 dev_err(adev->dev, "send training msg failed.\n"); 625 return ret; 626 } 627 } 628 ctx->training_cnt++; 629 return 0; 630 } 631 632 static int psp_v13_0_load_usbc_pd_fw(struct psp_context *psp, uint64_t fw_pri_mc_addr) 633 { 634 struct amdgpu_device *adev = psp->adev; 635 uint32_t reg_status; 636 int ret, i = 0; 637 638 /* 639 * LFB address which is aligned to 1MB address and has to be 640 * right-shifted by 20 so that LFB address can be passed on a 32-bit C2P 641 * register 642 */ 643 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, (fw_pri_mc_addr >> 20)); 644 645 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 646 0x80000000, 0x80000000, false); 647 if (ret) 648 return ret; 649 650 /* Fireup interrupt so PSP can pick up the address */ 651 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, (GFX_CMD_USB_PD_USE_LFB << 16)); 652 653 /* FW load takes very long time */ 654 do { 655 msleep(1000); 656 reg_status = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35); 657 658 if (reg_status & 0x80000000) 659 goto done; 660 661 } while (++i < USBC_PD_POLLING_LIMIT_S); 662 663 return -ETIME; 664 done: 665 666 if ((reg_status & 0xFFFF) != 0) { 667 DRM_ERROR("Address load failed - MP0_SMN_C2PMSG_35.Bits [15:0] = %04x\n", 668 reg_status & 0xFFFF); 669 return -EIO; 670 } 671 672 return 0; 673 } 674 675 static int psp_v13_0_read_usbc_pd_fw(struct psp_context *psp, uint32_t *fw_ver) 676 { 677 struct amdgpu_device *adev = psp->adev; 678 int ret; 679 680 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, C2PMSG_CMD_GFX_USB_PD_FW_VER); 681 682 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 683 0x80000000, 0x80000000, false); 684 if (!ret) 685 *fw_ver = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36); 686 687 return ret; 688 } 689 690 static int psp_v13_0_exec_spi_cmd(struct psp_context *psp, int cmd) 691 { 692 uint32_t reg_status = 0, reg_val = 0; 693 struct amdgpu_device *adev = psp->adev; 694 int ret; 695 696 /* clear MBX ready (MBOX_READY_MASK bit is 0) and set update command */ 697 reg_val |= (cmd << 16); 698 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115, reg_val); 699 700 /* Ring the doorbell */ 701 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_73, 1); 702 703 if (cmd == C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE) 704 ret = psp_wait_for_spirom_update(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115), 705 MBOX_READY_FLAG, MBOX_READY_MASK, PSP_SPIROM_UPDATE_TIMEOUT); 706 else 707 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115), 708 MBOX_READY_FLAG, MBOX_READY_MASK, false); 709 if (ret) { 710 dev_err(adev->dev, "SPI cmd %x timed out, ret = %d", cmd, ret); 711 return ret; 712 } 713 714 reg_status = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115); 715 if ((reg_status & 0xFFFF) != 0) { 716 dev_err(adev->dev, "SPI cmd %x failed, fail status = %04x\n", 717 cmd, reg_status & 0xFFFF); 718 return -EIO; 719 } 720 721 return 0; 722 } 723 724 static int psp_v13_0_update_spirom(struct psp_context *psp, 725 uint64_t fw_pri_mc_addr) 726 { 727 struct amdgpu_device *adev = psp->adev; 728 int ret; 729 730 /* Confirm PSP is ready to start */ 731 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115), 732 MBOX_READY_FLAG, MBOX_READY_MASK, false); 733 if (ret) { 734 dev_err(adev->dev, "PSP Not ready to start processing, ret = %d", ret); 735 return ret; 736 } 737 738 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, lower_32_bits(fw_pri_mc_addr)); 739 740 ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_LO); 741 if (ret) 742 return ret; 743 744 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, upper_32_bits(fw_pri_mc_addr)); 745 746 ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI); 747 if (ret) 748 return ret; 749 750 psp->vbflash_done = true; 751 752 ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE); 753 if (ret) 754 return ret; 755 756 return 0; 757 } 758 759 static int psp_v13_0_vbflash_status(struct psp_context *psp) 760 { 761 struct amdgpu_device *adev = psp->adev; 762 763 return RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115); 764 } 765 766 static int psp_v13_0_fatal_error_recovery_quirk(struct psp_context *psp) 767 { 768 struct amdgpu_device *adev = psp->adev; 769 770 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 10)) { 771 uint32_t reg_data; 772 /* MP1 fatal error: trigger PSP dram read to unhalt PSP 773 * during MP1 triggered sync flood. 774 */ 775 reg_data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67); 776 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67, reg_data + 0x10); 777 778 /* delay 1000ms for the mode1 reset for fatal error 779 * to be recovered back. 780 */ 781 msleep(1000); 782 } 783 784 return 0; 785 } 786 787 static bool psp_v13_0_get_ras_capability(struct psp_context *psp) 788 { 789 struct amdgpu_device *adev = psp->adev; 790 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 791 u32 reg_data; 792 793 /* query ras cap should be done from host side */ 794 if (amdgpu_sriov_vf(adev)) 795 return false; 796 797 if (!con) 798 return false; 799 800 if ((amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) || 801 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14)) && 802 (!(adev->flags & AMD_IS_APU))) { 803 reg_data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_127); 804 adev->ras_hw_enabled = (reg_data & GENMASK_ULL(23, 0)); 805 con->poison_supported = ((reg_data & GENMASK_ULL(24, 24)) >> 24) ? true : false; 806 return true; 807 } else { 808 return false; 809 } 810 } 811 812 static bool psp_v13_0_is_aux_sos_load_required(struct psp_context *psp) 813 { 814 struct amdgpu_device *adev = psp->adev; 815 u32 pmfw_ver; 816 817 if (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 6)) 818 return false; 819 820 /* load 4e version of sos if pmfw version less than 85.115.0 */ 821 pmfw_ver = RREG32(regMP1_PUB_SCRATCH0 / 4); 822 823 return (pmfw_ver < 0x557300); 824 } 825 826 static const struct psp_funcs psp_v13_0_funcs = { 827 .init_microcode = psp_v13_0_init_microcode, 828 .wait_for_bootloader = psp_v13_0_wait_for_bootloader_steady_state, 829 .bootloader_load_kdb = psp_v13_0_bootloader_load_kdb, 830 .bootloader_load_spl = psp_v13_0_bootloader_load_spl, 831 .bootloader_load_sysdrv = psp_v13_0_bootloader_load_sysdrv, 832 .bootloader_load_soc_drv = psp_v13_0_bootloader_load_soc_drv, 833 .bootloader_load_intf_drv = psp_v13_0_bootloader_load_intf_drv, 834 .bootloader_load_dbg_drv = psp_v13_0_bootloader_load_dbg_drv, 835 .bootloader_load_ras_drv = psp_v13_0_bootloader_load_ras_drv, 836 .bootloader_load_sos = psp_v13_0_bootloader_load_sos, 837 .ring_create = psp_v13_0_ring_create, 838 .ring_stop = psp_v13_0_ring_stop, 839 .ring_destroy = psp_v13_0_ring_destroy, 840 .ring_get_wptr = psp_v13_0_ring_get_wptr, 841 .ring_set_wptr = psp_v13_0_ring_set_wptr, 842 .mem_training = psp_v13_0_memory_training, 843 .load_usbc_pd_fw = psp_v13_0_load_usbc_pd_fw, 844 .read_usbc_pd_fw = psp_v13_0_read_usbc_pd_fw, 845 .update_spirom = psp_v13_0_update_spirom, 846 .vbflash_stat = psp_v13_0_vbflash_status, 847 .fatal_error_recovery_quirk = psp_v13_0_fatal_error_recovery_quirk, 848 .get_ras_capability = psp_v13_0_get_ras_capability, 849 .is_aux_sos_load_required = psp_v13_0_is_aux_sos_load_required, 850 }; 851 852 void psp_v13_0_set_psp_funcs(struct psp_context *psp) 853 { 854 psp->funcs = &psp_v13_0_funcs; 855 } 856