1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <drm/drm_drv.h> 24 #include <linux/vmalloc.h> 25 #include "amdgpu.h" 26 #include "amdgpu_psp.h" 27 #include "amdgpu_ucode.h" 28 #include "soc15_common.h" 29 #include "psp_v13_0.h" 30 #include "amdgpu_ras.h" 31 32 #include "mp/mp_13_0_2_offset.h" 33 #include "mp/mp_13_0_2_sh_mask.h" 34 35 MODULE_FIRMWARE("amdgpu/aldebaran_sos.bin"); 36 MODULE_FIRMWARE("amdgpu/aldebaran_ta.bin"); 37 MODULE_FIRMWARE("amdgpu/aldebaran_cap.bin"); 38 MODULE_FIRMWARE("amdgpu/yellow_carp_toc.bin"); 39 MODULE_FIRMWARE("amdgpu/yellow_carp_ta.bin"); 40 MODULE_FIRMWARE("amdgpu/psp_13_0_5_toc.bin"); 41 MODULE_FIRMWARE("amdgpu/psp_13_0_5_ta.bin"); 42 MODULE_FIRMWARE("amdgpu/psp_13_0_8_toc.bin"); 43 MODULE_FIRMWARE("amdgpu/psp_13_0_8_ta.bin"); 44 MODULE_FIRMWARE("amdgpu/psp_13_0_0_sos.bin"); 45 MODULE_FIRMWARE("amdgpu/psp_13_0_0_sos_kicker.bin"); 46 MODULE_FIRMWARE("amdgpu/psp_13_0_0_ta.bin"); 47 MODULE_FIRMWARE("amdgpu/psp_13_0_0_ta_kicker.bin"); 48 MODULE_FIRMWARE("amdgpu/psp_13_0_7_sos.bin"); 49 MODULE_FIRMWARE("amdgpu/psp_13_0_7_ta.bin"); 50 MODULE_FIRMWARE("amdgpu/psp_13_0_10_sos.bin"); 51 MODULE_FIRMWARE("amdgpu/psp_13_0_10_ta.bin"); 52 MODULE_FIRMWARE("amdgpu/psp_13_0_11_toc.bin"); 53 MODULE_FIRMWARE("amdgpu/psp_13_0_11_ta.bin"); 54 MODULE_FIRMWARE("amdgpu/psp_13_0_6_sos.bin"); 55 MODULE_FIRMWARE("amdgpu/psp_13_0_6_ta.bin"); 56 MODULE_FIRMWARE("amdgpu/psp_13_0_12_sos.bin"); 57 MODULE_FIRMWARE("amdgpu/psp_13_0_12_ta.bin"); 58 MODULE_FIRMWARE("amdgpu/psp_13_0_14_sos.bin"); 59 MODULE_FIRMWARE("amdgpu/psp_13_0_14_ta.bin"); 60 MODULE_FIRMWARE("amdgpu/psp_13_0_15_sos.bin"); 61 MODULE_FIRMWARE("amdgpu/psp_13_0_15_ta.bin"); 62 MODULE_FIRMWARE("amdgpu/psp_14_0_0_toc.bin"); 63 MODULE_FIRMWARE("amdgpu/psp_14_0_0_ta.bin"); 64 MODULE_FIRMWARE("amdgpu/psp_14_0_1_toc.bin"); 65 MODULE_FIRMWARE("amdgpu/psp_14_0_1_ta.bin"); 66 MODULE_FIRMWARE("amdgpu/psp_14_0_4_toc.bin"); 67 MODULE_FIRMWARE("amdgpu/psp_14_0_4_ta.bin"); 68 69 /* For large FW files the time to complete can be very long */ 70 #define USBC_PD_POLLING_LIMIT_S 240 71 72 /* Read USB-PD from LFB */ 73 #define GFX_CMD_USB_PD_USE_LFB 0x480 74 75 /* Retry times for vmbx ready wait */ 76 #define PSP_VMBX_POLLING_LIMIT 3000 77 78 /* memory training timeout define */ 79 #define MEM_TRAIN_SEND_MSG_TIMEOUT_US 3000000 80 81 #define regMP1_PUB_SCRATCH0 0x3b10090 82 83 #define PSP13_BL_STATUS_SIZE 100 84 85 static int psp_v13_0_init_microcode(struct psp_context *psp) 86 { 87 struct amdgpu_device *adev = psp->adev; 88 char ucode_prefix[30]; 89 int err = 0; 90 91 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); 92 93 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 94 case IP_VERSION(13, 0, 2): 95 err = psp_init_sos_microcode(psp, ucode_prefix); 96 if (err) 97 return err; 98 /* It's not necessary to load ras ta on Guest side */ 99 if (!amdgpu_sriov_vf(adev)) { 100 err = psp_init_ta_microcode(psp, ucode_prefix); 101 if (err) 102 return err; 103 } 104 break; 105 case IP_VERSION(13, 0, 1): 106 case IP_VERSION(13, 0, 3): 107 case IP_VERSION(13, 0, 5): 108 case IP_VERSION(13, 0, 8): 109 case IP_VERSION(13, 0, 11): 110 case IP_VERSION(14, 0, 0): 111 case IP_VERSION(14, 0, 1): 112 case IP_VERSION(14, 0, 4): 113 err = psp_init_toc_microcode(psp, ucode_prefix); 114 if (err) 115 return err; 116 err = psp_init_ta_microcode(psp, ucode_prefix); 117 if (err) 118 return err; 119 break; 120 case IP_VERSION(13, 0, 0): 121 case IP_VERSION(13, 0, 6): 122 case IP_VERSION(13, 0, 7): 123 case IP_VERSION(13, 0, 10): 124 case IP_VERSION(13, 0, 12): 125 case IP_VERSION(13, 0, 14): 126 case IP_VERSION(13, 0, 15): 127 err = psp_init_sos_microcode(psp, ucode_prefix); 128 if (err) 129 return err; 130 /* It's not necessary to load ras ta on Guest side */ 131 err = psp_init_ta_microcode(psp, ucode_prefix); 132 if (err) 133 return err; 134 break; 135 default: 136 BUG(); 137 } 138 139 return 0; 140 } 141 142 static bool psp_v13_0_is_sos_alive(struct psp_context *psp) 143 { 144 struct amdgpu_device *adev = psp->adev; 145 uint32_t sol_reg; 146 147 sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81); 148 149 return sol_reg != 0x0; 150 } 151 152 static void psp_v13_0_bootloader_print_status(struct psp_context *psp, 153 const char *msg) 154 { 155 struct amdgpu_device *adev = psp->adev; 156 u32 bl_status_reg; 157 char bl_status_msg[PSP13_BL_STATUS_SIZE]; 158 int i, at; 159 160 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) || 161 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 12) || 162 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14) || 163 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 15)) { 164 at = 0; 165 for_each_inst(i, adev->aid_mask) { 166 bl_status_reg = 167 (SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_92) 168 << 2) + 169 amdgpu_reg_get_smn_base64(adev, MP0_HWIP, i); 170 at += snprintf(bl_status_msg + at, 171 PSP13_BL_STATUS_SIZE - at, 172 " status(%02i): 0x%08x", i, 173 RREG32_PCIE_EXT(bl_status_reg)); 174 } 175 dev_info(adev->dev, "%s - %s", msg, bl_status_msg); 176 } 177 } 178 179 static int psp_v13_0_wait_for_vmbx_ready(struct psp_context *psp) 180 { 181 struct amdgpu_device *adev = psp->adev; 182 int retry_loop, ret; 183 184 for (retry_loop = 0; retry_loop < PSP_VMBX_POLLING_LIMIT; retry_loop++) { 185 /* Wait for bootloader to signify that is 186 ready having bit 31 of C2PMSG_33 set to 1 */ 187 ret = psp_wait_for( 188 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_33), 189 0x80000000, 0xffffffff, PSP_WAITREG_NOVERBOSE); 190 191 if (ret == 0) 192 break; 193 } 194 195 if (ret) 196 dev_warn(adev->dev, "Bootloader wait timed out"); 197 198 return ret; 199 } 200 201 static int psp_v13_0_wait_for_bootloader(struct psp_context *psp) 202 { 203 struct amdgpu_device *adev = psp->adev; 204 int retry_loop, retry_cnt, ret; 205 206 retry_cnt = 207 ((amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) || 208 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 12) || 209 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14) || 210 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 15))) ? 211 PSP_VMBX_POLLING_LIMIT : 212 10; 213 /* Wait for bootloader to signify that it is ready having bit 31 of 214 * C2PMSG_35 set to 1. All other bits are expected to be cleared. 215 * If there is an error in processing command, bits[7:0] will be set. 216 * This is applicable for PSP v13.0.6 and newer. 217 */ 218 for (retry_loop = 0; retry_loop < retry_cnt; retry_loop++) { 219 ret = psp_wait_for( 220 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 221 0x80000000, 0xffffffff, PSP_WAITREG_NOVERBOSE); 222 223 if (ret == 0) 224 return 0; 225 if (retry_loop && !(retry_loop % 10)) 226 psp_v13_0_bootloader_print_status( 227 psp, "Waiting for bootloader completion"); 228 } 229 230 return ret; 231 } 232 233 static int psp_v13_0_wait_for_bootloader_steady_state(struct psp_context *psp) 234 { 235 struct amdgpu_device *adev = psp->adev; 236 int ret; 237 238 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) || 239 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 12) || 240 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14) || 241 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 15)) { 242 ret = psp_v13_0_wait_for_vmbx_ready(psp); 243 if (ret) 244 amdgpu_ras_query_boot_status(adev, 4); 245 246 ret = psp_v13_0_wait_for_bootloader(psp); 247 if (ret) 248 amdgpu_ras_query_boot_status(adev, 4); 249 250 return ret; 251 } 252 253 return 0; 254 } 255 256 static int psp_v13_0_bootloader_load_component(struct psp_context *psp, 257 struct psp_bin_desc *bin_desc, 258 enum psp_bootloader_cmd bl_cmd) 259 { 260 int ret; 261 uint32_t psp_gfxdrv_command_reg = 0; 262 struct amdgpu_device *adev = psp->adev; 263 264 /* Check tOS sign of life register to confirm sys driver and sOS 265 * are already been loaded. 266 */ 267 if (psp_v13_0_is_sos_alive(psp)) 268 return 0; 269 270 ret = psp_v13_0_wait_for_bootloader(psp); 271 if (ret) 272 return ret; 273 274 ret = psp_copy_fw(psp, bin_desc->start_addr, bin_desc->size_bytes); 275 if (ret) 276 return ret; 277 278 /* Provide the PSP KDB to bootloader */ 279 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, 280 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 281 psp_gfxdrv_command_reg = bl_cmd; 282 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, 283 psp_gfxdrv_command_reg); 284 285 ret = psp_v13_0_wait_for_bootloader(psp); 286 287 return ret; 288 } 289 290 static int psp_v13_0_bootloader_load_kdb(struct psp_context *psp) 291 { 292 return psp_v13_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_KEY_DATABASE); 293 } 294 295 static int psp_v13_0_bootloader_load_spl(struct psp_context *psp) 296 { 297 return psp_v13_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_TOS_SPL_TABLE); 298 } 299 300 static int psp_v13_0_bootloader_load_sysdrv(struct psp_context *psp) 301 { 302 return psp_v13_0_bootloader_load_component(psp, &psp->sys, PSP_BL__LOAD_SYSDRV); 303 } 304 305 static int psp_v13_0_bootloader_load_soc_drv(struct psp_context *psp) 306 { 307 return psp_v13_0_bootloader_load_component(psp, &psp->soc_drv, PSP_BL__LOAD_SOCDRV); 308 } 309 310 static int psp_v13_0_bootloader_load_intf_drv(struct psp_context *psp) 311 { 312 return psp_v13_0_bootloader_load_component(psp, &psp->intf_drv, PSP_BL__LOAD_INTFDRV); 313 } 314 315 static int psp_v13_0_bootloader_load_dbg_drv(struct psp_context *psp) 316 { 317 return psp_v13_0_bootloader_load_component(psp, &psp->dbg_drv, PSP_BL__LOAD_DBGDRV); 318 } 319 320 static int psp_v13_0_bootloader_load_ras_drv(struct psp_context *psp) 321 { 322 return psp_v13_0_bootloader_load_component(psp, &psp->ras_drv, PSP_BL__LOAD_RASDRV); 323 } 324 325 static int psp_v13_0_bootloader_load_spdm_drv(struct psp_context *psp) 326 { 327 return psp_v13_0_bootloader_load_component(psp, &psp->spdm_drv, PSP_BL__LOAD_SPDMDRV); 328 } 329 330 static inline void psp_v13_0_init_sos_version(struct psp_context *psp) 331 { 332 struct amdgpu_device *adev = psp->adev; 333 334 psp->sos.fw_version = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_58); 335 } 336 337 static int psp_v13_0_bootloader_load_sos(struct psp_context *psp) 338 { 339 int ret; 340 unsigned int psp_gfxdrv_command_reg = 0; 341 struct amdgpu_device *adev = psp->adev; 342 343 /* Check sOS sign of life register to confirm sys driver and sOS 344 * are already been loaded. 345 */ 346 if (psp_v13_0_is_sos_alive(psp)) { 347 psp_v13_0_init_sos_version(psp); 348 return 0; 349 } 350 351 ret = psp_v13_0_wait_for_bootloader(psp); 352 if (ret) 353 return ret; 354 355 ret = psp_copy_fw(psp, psp->sos.start_addr, psp->sos.size_bytes); 356 if (ret) 357 return ret; 358 359 /* Provide the PSP secure OS to bootloader */ 360 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, 361 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 362 psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV; 363 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, 364 psp_gfxdrv_command_reg); 365 366 /* there might be handshake issue with hardware which needs delay */ 367 mdelay(20); 368 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_81), 369 RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81), 0, 370 PSP_WAITREG_CHANGED); 371 372 if (!ret) 373 psp_v13_0_init_sos_version(psp); 374 375 return ret; 376 } 377 378 static int psp_v13_0_ring_stop(struct psp_context *psp, 379 enum psp_ring_type ring_type) 380 { 381 int ret = 0; 382 struct amdgpu_device *adev = psp->adev; 383 384 if (amdgpu_sriov_vf(adev)) { 385 /* Write the ring destroy command*/ 386 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, 387 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING); 388 /* there might be handshake issue with hardware which needs delay */ 389 mdelay(20); 390 /* Wait for response flag (bit 31) */ 391 ret = psp_wait_for( 392 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101), 393 MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0); 394 } else { 395 /* Write the ring destroy command*/ 396 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, 397 GFX_CTRL_CMD_ID_DESTROY_RINGS); 398 /* there might be handshake issue with hardware which needs delay */ 399 mdelay(20); 400 /* Wait for response flag (bit 31) */ 401 ret = psp_wait_for( 402 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), 403 MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0); 404 } 405 406 return ret; 407 } 408 409 static int psp_v13_0_ring_create(struct psp_context *psp, 410 enum psp_ring_type ring_type) 411 { 412 int ret = 0; 413 unsigned int psp_ring_reg = 0; 414 struct psp_ring *ring = &psp->km_ring; 415 struct amdgpu_device *adev = psp->adev; 416 417 if (amdgpu_sriov_vf(adev)) { 418 ret = psp_v13_0_ring_stop(psp, ring_type); 419 if (ret) { 420 DRM_ERROR("psp_v13_0_ring_stop_sriov failed!\n"); 421 return ret; 422 } 423 424 /* Write low address of the ring to C2PMSG_102 */ 425 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 426 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, psp_ring_reg); 427 /* Write high address of the ring to C2PMSG_103 */ 428 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 429 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_103, psp_ring_reg); 430 431 /* Write the ring initialization command to C2PMSG_101 */ 432 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, 433 GFX_CTRL_CMD_ID_INIT_GPCOM_RING); 434 435 /* there might be handshake issue with hardware which needs delay */ 436 mdelay(20); 437 438 /* Wait for response flag (bit 31) in C2PMSG_101 */ 439 ret = psp_wait_for( 440 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101), 441 MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0); 442 443 } else { 444 /* Wait for sOS ready for ring creation */ 445 ret = psp_wait_for( 446 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), 447 MBOX_TOS_READY_FLAG, MBOX_TOS_READY_MASK, 0); 448 if (ret) { 449 DRM_ERROR("Failed to wait for trust OS ready for ring creation\n"); 450 return ret; 451 } 452 453 /* Write low address of the ring to C2PMSG_69 */ 454 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 455 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_69, psp_ring_reg); 456 /* Write high address of the ring to C2PMSG_70 */ 457 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 458 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_70, psp_ring_reg); 459 /* Write size of ring to C2PMSG_71 */ 460 psp_ring_reg = ring->ring_size; 461 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_71, psp_ring_reg); 462 /* Write the ring initialization command to C2PMSG_64 */ 463 psp_ring_reg = ring_type; 464 psp_ring_reg = psp_ring_reg << 16; 465 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, psp_ring_reg); 466 467 /* there might be handshake issue with hardware which needs delay */ 468 mdelay(20); 469 470 /* Wait for response flag (bit 31) in C2PMSG_64 */ 471 ret = psp_wait_for( 472 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), 473 MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0); 474 } 475 476 return ret; 477 } 478 479 static int psp_v13_0_ring_destroy(struct psp_context *psp, 480 enum psp_ring_type ring_type) 481 { 482 int ret = 0; 483 struct psp_ring *ring = &psp->km_ring; 484 struct amdgpu_device *adev = psp->adev; 485 486 ret = psp_v13_0_ring_stop(psp, ring_type); 487 if (ret) 488 DRM_ERROR("Fail to stop psp ring\n"); 489 490 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 491 &ring->ring_mem_mc_addr, 492 (void **)&ring->ring_mem); 493 494 return ret; 495 } 496 497 static uint32_t psp_v13_0_ring_get_wptr(struct psp_context *psp) 498 { 499 uint32_t data; 500 struct amdgpu_device *adev = psp->adev; 501 502 if (amdgpu_sriov_vf(adev)) 503 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102); 504 else 505 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67); 506 507 return data; 508 } 509 510 static void psp_v13_0_ring_set_wptr(struct psp_context *psp, uint32_t value) 511 { 512 struct amdgpu_device *adev = psp->adev; 513 514 if (amdgpu_sriov_vf(adev)) { 515 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, value); 516 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, 517 GFX_CTRL_CMD_ID_CONSUME_CMD); 518 } else 519 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67, value); 520 } 521 522 static int psp_v13_0_memory_training_send_msg(struct psp_context *psp, int msg) 523 { 524 int ret; 525 int i; 526 uint32_t data_32; 527 int max_wait; 528 struct amdgpu_device *adev = psp->adev; 529 530 data_32 = (psp->mem_train_ctx.c2p_train_data_offset >> 20); 531 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, data_32); 532 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, msg); 533 534 max_wait = MEM_TRAIN_SEND_MSG_TIMEOUT_US / adev->usec_timeout; 535 for (i = 0; i < max_wait; i++) { 536 ret = psp_wait_for( 537 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 538 0x80000000, 0x80000000, PSP_WAITREG_NOVERBOSE); 539 if (ret == 0) 540 break; 541 } 542 if (i < max_wait) 543 ret = 0; 544 else 545 ret = -ETIME; 546 547 dev_dbg(adev->dev, "training %s %s, cost %d @ %d ms\n", 548 (msg == PSP_BL__DRAM_SHORT_TRAIN) ? "short" : "long", 549 (ret == 0) ? "succeed" : "failed", 550 i, adev->usec_timeout/1000); 551 return ret; 552 } 553 554 555 static int psp_v13_0_memory_training(struct psp_context *psp, uint32_t ops) 556 { 557 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 558 uint32_t *pcache = (uint32_t *)ctx->sys_cache; 559 struct amdgpu_device *adev = psp->adev; 560 uint32_t p2c_header[4]; 561 uint32_t sz; 562 void *buf; 563 int ret, idx; 564 565 if (ctx->init == PSP_MEM_TRAIN_NOT_SUPPORT) { 566 dev_dbg(adev->dev, "Memory training is not supported.\n"); 567 return 0; 568 } else if (ctx->init != PSP_MEM_TRAIN_INIT_SUCCESS) { 569 dev_err(adev->dev, "Memory training initialization failure.\n"); 570 return -EINVAL; 571 } 572 573 if (psp_v13_0_is_sos_alive(psp)) { 574 dev_dbg(adev->dev, "SOS is alive, skip memory training.\n"); 575 return 0; 576 } 577 578 amdgpu_device_vram_access(adev, ctx->p2c_train_data_offset, p2c_header, sizeof(p2c_header), false); 579 dev_dbg(adev->dev, "sys_cache[%08x,%08x,%08x,%08x] p2c_header[%08x,%08x,%08x,%08x]\n", 580 pcache[0], pcache[1], pcache[2], pcache[3], 581 p2c_header[0], p2c_header[1], p2c_header[2], p2c_header[3]); 582 583 if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) { 584 dev_dbg(adev->dev, "Short training depends on restore.\n"); 585 ops |= PSP_MEM_TRAIN_RESTORE; 586 } 587 588 if ((ops & PSP_MEM_TRAIN_RESTORE) && 589 pcache[0] != MEM_TRAIN_SYSTEM_SIGNATURE) { 590 dev_dbg(adev->dev, "sys_cache[0] is invalid, restore depends on save.\n"); 591 ops |= PSP_MEM_TRAIN_SAVE; 592 } 593 594 if (p2c_header[0] == MEM_TRAIN_SYSTEM_SIGNATURE && 595 !(pcache[0] == MEM_TRAIN_SYSTEM_SIGNATURE && 596 pcache[3] == p2c_header[3])) { 597 dev_dbg(adev->dev, "sys_cache is invalid or out-of-date, need save training data to sys_cache.\n"); 598 ops |= PSP_MEM_TRAIN_SAVE; 599 } 600 601 if ((ops & PSP_MEM_TRAIN_SAVE) && 602 p2c_header[0] != MEM_TRAIN_SYSTEM_SIGNATURE) { 603 dev_dbg(adev->dev, "p2c_header[0] is invalid, save depends on long training.\n"); 604 ops |= PSP_MEM_TRAIN_SEND_LONG_MSG; 605 } 606 607 if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) { 608 ops &= ~PSP_MEM_TRAIN_SEND_SHORT_MSG; 609 ops |= PSP_MEM_TRAIN_SAVE; 610 } 611 612 dev_dbg(adev->dev, "Memory training ops:%x.\n", ops); 613 614 if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) { 615 /* 616 * Long training will encroach a certain amount on the bottom of VRAM; 617 * save the content from the bottom of VRAM to system memory 618 * before training, and restore it after training to avoid 619 * VRAM corruption. 620 */ 621 sz = BIST_MEM_TRAINING_ENCROACHED_SIZE; 622 623 if (adev->gmc.visible_vram_size < sz || !adev->mman.aper_base_kaddr) { 624 dev_err(adev->dev, "visible_vram_size %llx or aper_base_kaddr %p is not initialized.\n", 625 adev->gmc.visible_vram_size, 626 adev->mman.aper_base_kaddr); 627 return -EINVAL; 628 } 629 630 buf = vmalloc(sz); 631 if (!buf) { 632 dev_err(adev->dev, "failed to allocate system memory.\n"); 633 return -ENOMEM; 634 } 635 636 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 637 memcpy_fromio(buf, adev->mman.aper_base_kaddr, sz); 638 ret = psp_v13_0_memory_training_send_msg(psp, PSP_BL__DRAM_LONG_TRAIN); 639 if (ret) { 640 DRM_ERROR("Send long training msg failed.\n"); 641 vfree(buf); 642 drm_dev_exit(idx); 643 return ret; 644 } 645 646 memcpy_toio(adev->mman.aper_base_kaddr, buf, sz); 647 amdgpu_device_flush_hdp(adev, NULL); 648 vfree(buf); 649 drm_dev_exit(idx); 650 } else { 651 vfree(buf); 652 return -ENODEV; 653 } 654 } 655 656 if (ops & PSP_MEM_TRAIN_SAVE) { 657 amdgpu_device_vram_access(psp->adev, ctx->p2c_train_data_offset, ctx->sys_cache, ctx->train_data_size, false); 658 } 659 660 if (ops & PSP_MEM_TRAIN_RESTORE) { 661 amdgpu_device_vram_access(psp->adev, ctx->c2p_train_data_offset, ctx->sys_cache, ctx->train_data_size, true); 662 } 663 664 if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) { 665 ret = psp_v13_0_memory_training_send_msg(psp, (amdgpu_force_long_training > 0) ? 666 PSP_BL__DRAM_LONG_TRAIN : PSP_BL__DRAM_SHORT_TRAIN); 667 if (ret) { 668 dev_err(adev->dev, "send training msg failed.\n"); 669 return ret; 670 } 671 } 672 ctx->training_cnt++; 673 return 0; 674 } 675 676 static int psp_v13_0_load_usbc_pd_fw(struct psp_context *psp, uint64_t fw_pri_mc_addr) 677 { 678 struct amdgpu_device *adev = psp->adev; 679 uint32_t reg_status; 680 int ret, i = 0; 681 682 /* 683 * LFB address which is aligned to 1MB address and has to be 684 * right-shifted by 20 so that LFB address can be passed on a 32-bit C2P 685 * register 686 */ 687 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, (fw_pri_mc_addr >> 20)); 688 689 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 690 0x80000000, 0x80000000, 0); 691 if (ret) 692 return ret; 693 694 /* Fireup interrupt so PSP can pick up the address */ 695 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, (GFX_CMD_USB_PD_USE_LFB << 16)); 696 697 /* FW load takes very long time */ 698 do { 699 msleep(1000); 700 reg_status = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35); 701 702 if (reg_status & 0x80000000) 703 goto done; 704 705 } while (++i < USBC_PD_POLLING_LIMIT_S); 706 707 return -ETIME; 708 done: 709 710 if ((reg_status & 0xFFFF) != 0) { 711 DRM_ERROR("Address load failed - MP0_SMN_C2PMSG_35.Bits [15:0] = %04x\n", 712 reg_status & 0xFFFF); 713 return -EIO; 714 } 715 716 return 0; 717 } 718 719 static int psp_v13_0_read_usbc_pd_fw(struct psp_context *psp, uint32_t *fw_ver) 720 { 721 struct amdgpu_device *adev = psp->adev; 722 int ret; 723 724 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, C2PMSG_CMD_GFX_USB_PD_FW_VER); 725 726 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 727 0x80000000, 0x80000000, 0); 728 if (!ret) 729 *fw_ver = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36); 730 731 return ret; 732 } 733 734 static int psp_v13_0_exec_spi_cmd(struct psp_context *psp, int cmd) 735 { 736 uint32_t reg_status = 0, reg_val = 0; 737 struct amdgpu_device *adev = psp->adev; 738 int ret; 739 740 /* clear MBX ready (MBOX_READY_MASK bit is 0) and set update command */ 741 reg_val |= (cmd << 16); 742 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115, reg_val); 743 744 /* Ring the doorbell */ 745 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_73, 1); 746 747 if (cmd == C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE || 748 cmd == C2PMSG_CMD_SPI_GET_FLASH_IMAGE) 749 ret = psp_wait_for_spirom_update(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115), 750 MBOX_READY_FLAG, MBOX_READY_MASK, PSP_SPIROM_UPDATE_TIMEOUT); 751 else 752 ret = psp_wait_for( 753 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115), 754 MBOX_READY_FLAG, MBOX_READY_MASK, 0); 755 if (ret) { 756 dev_err(adev->dev, "SPI cmd %x timed out, ret = %d", cmd, ret); 757 return ret; 758 } 759 760 reg_status = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115); 761 if ((reg_status & 0xFFFF) != 0) { 762 dev_err(adev->dev, "SPI cmd %x failed, fail status = %04x\n", 763 cmd, reg_status & 0xFFFF); 764 return -EIO; 765 } 766 767 return 0; 768 } 769 770 static int psp_v13_0_update_spirom(struct psp_context *psp, 771 uint64_t fw_pri_mc_addr) 772 { 773 struct amdgpu_device *adev = psp->adev; 774 int ret; 775 776 /* Confirm PSP is ready to start */ 777 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115), 778 MBOX_READY_FLAG, MBOX_READY_MASK, 0); 779 if (ret) { 780 dev_err(adev->dev, "PSP Not ready to start processing, ret = %d", ret); 781 return ret; 782 } 783 784 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, lower_32_bits(fw_pri_mc_addr)); 785 786 ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_LO); 787 if (ret) 788 return ret; 789 790 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, upper_32_bits(fw_pri_mc_addr)); 791 792 ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI); 793 if (ret) 794 return ret; 795 796 psp->vbflash_done = true; 797 798 ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE); 799 if (ret) 800 return ret; 801 802 return 0; 803 } 804 805 static int psp_v13_0_dump_spirom(struct psp_context *psp, 806 uint64_t fw_pri_mc_addr) 807 { 808 struct amdgpu_device *adev = psp->adev; 809 int ret; 810 811 /* Confirm PSP is ready to start */ 812 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115), 813 MBOX_READY_FLAG, MBOX_READY_MASK, 0); 814 if (ret) { 815 dev_err(adev->dev, "PSP Not ready to start processing, ret = %d", ret); 816 return ret; 817 } 818 819 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, lower_32_bits(fw_pri_mc_addr)); 820 821 ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_GET_ROM_IMAGE_ADDR_LO); 822 if (ret) 823 return ret; 824 825 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, upper_32_bits(fw_pri_mc_addr)); 826 827 ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_GET_ROM_IMAGE_ADDR_HI); 828 if (ret) 829 return ret; 830 831 ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_GET_FLASH_IMAGE); 832 833 return ret; 834 } 835 836 static int psp_v13_0_vbflash_status(struct psp_context *psp) 837 { 838 struct amdgpu_device *adev = psp->adev; 839 840 return RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115); 841 } 842 843 static int psp_v13_0_fatal_error_recovery_quirk(struct psp_context *psp) 844 { 845 struct amdgpu_device *adev = psp->adev; 846 847 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 10)) { 848 uint32_t reg_data; 849 /* MP1 fatal error: trigger PSP dram read to unhalt PSP 850 * during MP1 triggered sync flood. 851 */ 852 reg_data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67); 853 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67, reg_data + 0x10); 854 855 /* delay 1000ms for the mode1 reset for fatal error 856 * to be recovered back. 857 */ 858 msleep(1000); 859 } 860 861 return 0; 862 } 863 864 static bool psp_v13_0_get_ras_capability(struct psp_context *psp) 865 { 866 struct amdgpu_device *adev = psp->adev; 867 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 868 u32 reg_data; 869 870 /* query ras cap should be done from host side */ 871 if (amdgpu_sriov_vf(adev)) 872 return false; 873 874 if (!con) 875 return false; 876 877 if ((amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) || 878 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 12) || 879 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14) || 880 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 15)) && 881 (!(adev->flags & AMD_IS_APU))) { 882 reg_data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_127); 883 adev->ras_hw_enabled = (reg_data & GENMASK_ULL(23, 0)); 884 con->poison_supported = ((reg_data & GENMASK_ULL(24, 24)) >> 24) ? true : false; 885 return true; 886 } else { 887 return false; 888 } 889 } 890 891 static bool psp_v13_0_is_aux_sos_load_required(struct psp_context *psp) 892 { 893 struct amdgpu_device *adev = psp->adev; 894 u32 pmfw_ver; 895 896 if (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 6)) 897 return false; 898 899 /* load 4e version of sos if pmfw version less than 85.115.0 */ 900 pmfw_ver = RREG32(regMP1_PUB_SCRATCH0 / 4); 901 902 return (pmfw_ver < 0x557300); 903 } 904 905 static bool psp_v13_0_is_reload_needed(struct psp_context *psp) 906 { 907 uint32_t ucode_ver; 908 909 if (!psp_v13_0_is_sos_alive(psp)) 910 return false; 911 912 /* Restrict reload support only to specific IP versions */ 913 switch (amdgpu_ip_version(psp->adev, MP0_HWIP, 0)) { 914 case IP_VERSION(13, 0, 2): 915 case IP_VERSION(13, 0, 6): 916 case IP_VERSION(13, 0, 14): 917 /* TOS version read from microcode header */ 918 ucode_ver = psp->sos.fw_version; 919 /* Read TOS version from hardware */ 920 psp_v13_0_init_sos_version(psp); 921 return (ucode_ver != psp->sos.fw_version); 922 default: 923 return false; 924 } 925 926 return false; 927 } 928 929 static int psp_v13_0_reg_program_no_ring(struct psp_context *psp, uint32_t val, 930 enum psp_reg_prog_id id) 931 { 932 struct amdgpu_device *adev = psp->adev; 933 int ret = -EOPNOTSUPP; 934 935 /* PSP will broadcast the value to all instances */ 936 if (amdgpu_sriov_vf(adev)) { 937 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_GBR_IH_SET); 938 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, id); 939 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_103, val); 940 941 ret = psp_wait_for( 942 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101), 943 0x80000000, 0x80000000, 0); 944 } 945 946 return ret; 947 } 948 949 static const struct psp_funcs psp_v13_0_funcs = { 950 .init_microcode = psp_v13_0_init_microcode, 951 .wait_for_bootloader = psp_v13_0_wait_for_bootloader_steady_state, 952 .bootloader_load_kdb = psp_v13_0_bootloader_load_kdb, 953 .bootloader_load_spl = psp_v13_0_bootloader_load_spl, 954 .bootloader_load_sysdrv = psp_v13_0_bootloader_load_sysdrv, 955 .bootloader_load_soc_drv = psp_v13_0_bootloader_load_soc_drv, 956 .bootloader_load_intf_drv = psp_v13_0_bootloader_load_intf_drv, 957 .bootloader_load_dbg_drv = psp_v13_0_bootloader_load_dbg_drv, 958 .bootloader_load_ras_drv = psp_v13_0_bootloader_load_ras_drv, 959 .bootloader_load_spdm_drv = psp_v13_0_bootloader_load_spdm_drv, 960 .bootloader_load_sos = psp_v13_0_bootloader_load_sos, 961 .ring_create = psp_v13_0_ring_create, 962 .ring_stop = psp_v13_0_ring_stop, 963 .ring_destroy = psp_v13_0_ring_destroy, 964 .ring_get_wptr = psp_v13_0_ring_get_wptr, 965 .ring_set_wptr = psp_v13_0_ring_set_wptr, 966 .mem_training = psp_v13_0_memory_training, 967 .load_usbc_pd_fw = psp_v13_0_load_usbc_pd_fw, 968 .read_usbc_pd_fw = psp_v13_0_read_usbc_pd_fw, 969 .update_spirom = psp_v13_0_update_spirom, 970 .dump_spirom = psp_v13_0_dump_spirom, 971 .vbflash_stat = psp_v13_0_vbflash_status, 972 .fatal_error_recovery_quirk = psp_v13_0_fatal_error_recovery_quirk, 973 .get_ras_capability = psp_v13_0_get_ras_capability, 974 .is_aux_sos_load_required = psp_v13_0_is_aux_sos_load_required, 975 .is_reload_needed = psp_v13_0_is_reload_needed, 976 .reg_program_no_ring = psp_v13_0_reg_program_no_ring, 977 }; 978 979 void psp_v13_0_set_psp_funcs(struct psp_context *psp) 980 { 981 psp->funcs = &psp_v13_0_funcs; 982 } 983