1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <drm/drm_drv.h> 24 #include <linux/vmalloc.h> 25 #include "amdgpu.h" 26 #include "amdgpu_psp.h" 27 #include "amdgpu_ucode.h" 28 #include "soc15_common.h" 29 #include "psp_v13_0.h" 30 #include "amdgpu_ras.h" 31 32 #include "mp/mp_13_0_2_offset.h" 33 #include "mp/mp_13_0_2_sh_mask.h" 34 35 MODULE_FIRMWARE("amdgpu/aldebaran_sos.bin"); 36 MODULE_FIRMWARE("amdgpu/aldebaran_ta.bin"); 37 MODULE_FIRMWARE("amdgpu/aldebaran_cap.bin"); 38 MODULE_FIRMWARE("amdgpu/yellow_carp_toc.bin"); 39 MODULE_FIRMWARE("amdgpu/yellow_carp_ta.bin"); 40 MODULE_FIRMWARE("amdgpu/psp_13_0_5_toc.bin"); 41 MODULE_FIRMWARE("amdgpu/psp_13_0_5_ta.bin"); 42 MODULE_FIRMWARE("amdgpu/psp_13_0_8_toc.bin"); 43 MODULE_FIRMWARE("amdgpu/psp_13_0_8_ta.bin"); 44 MODULE_FIRMWARE("amdgpu/psp_13_0_0_sos.bin"); 45 MODULE_FIRMWARE("amdgpu/psp_13_0_0_ta.bin"); 46 MODULE_FIRMWARE("amdgpu/psp_13_0_7_sos.bin"); 47 MODULE_FIRMWARE("amdgpu/psp_13_0_7_ta.bin"); 48 MODULE_FIRMWARE("amdgpu/psp_13_0_10_sos.bin"); 49 MODULE_FIRMWARE("amdgpu/psp_13_0_10_ta.bin"); 50 MODULE_FIRMWARE("amdgpu/psp_13_0_11_toc.bin"); 51 MODULE_FIRMWARE("amdgpu/psp_13_0_11_ta.bin"); 52 MODULE_FIRMWARE("amdgpu/psp_13_0_6_sos.bin"); 53 MODULE_FIRMWARE("amdgpu/psp_13_0_6_ta.bin"); 54 MODULE_FIRMWARE("amdgpu/psp_13_0_14_sos.bin"); 55 MODULE_FIRMWARE("amdgpu/psp_13_0_14_ta.bin"); 56 MODULE_FIRMWARE("amdgpu/psp_14_0_0_toc.bin"); 57 MODULE_FIRMWARE("amdgpu/psp_14_0_0_ta.bin"); 58 MODULE_FIRMWARE("amdgpu/psp_14_0_1_toc.bin"); 59 MODULE_FIRMWARE("amdgpu/psp_14_0_1_ta.bin"); 60 61 /* For large FW files the time to complete can be very long */ 62 #define USBC_PD_POLLING_LIMIT_S 240 63 64 /* Read USB-PD from LFB */ 65 #define GFX_CMD_USB_PD_USE_LFB 0x480 66 67 /* Retry times for vmbx ready wait */ 68 #define PSP_VMBX_POLLING_LIMIT 3000 69 70 /* VBIOS gfl defines */ 71 #define MBOX_READY_MASK 0x80000000 72 #define MBOX_STATUS_MASK 0x0000FFFF 73 #define MBOX_COMMAND_MASK 0x00FF0000 74 #define MBOX_READY_FLAG 0x80000000 75 #define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_LO 0x2 76 #define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI 0x3 77 #define C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE 0x4 78 79 /* memory training timeout define */ 80 #define MEM_TRAIN_SEND_MSG_TIMEOUT_US 3000000 81 82 static int psp_v13_0_init_microcode(struct psp_context *psp) 83 { 84 struct amdgpu_device *adev = psp->adev; 85 char ucode_prefix[30]; 86 int err = 0; 87 88 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); 89 90 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 91 case IP_VERSION(13, 0, 2): 92 err = psp_init_sos_microcode(psp, ucode_prefix); 93 if (err) 94 return err; 95 /* It's not necessary to load ras ta on Guest side */ 96 if (!amdgpu_sriov_vf(adev)) { 97 err = psp_init_ta_microcode(psp, ucode_prefix); 98 if (err) 99 return err; 100 } 101 break; 102 case IP_VERSION(13, 0, 1): 103 case IP_VERSION(13, 0, 3): 104 case IP_VERSION(13, 0, 5): 105 case IP_VERSION(13, 0, 8): 106 case IP_VERSION(13, 0, 11): 107 case IP_VERSION(14, 0, 0): 108 case IP_VERSION(14, 0, 1): 109 err = psp_init_toc_microcode(psp, ucode_prefix); 110 if (err) 111 return err; 112 err = psp_init_ta_microcode(psp, ucode_prefix); 113 if (err) 114 return err; 115 break; 116 case IP_VERSION(13, 0, 0): 117 case IP_VERSION(13, 0, 6): 118 case IP_VERSION(13, 0, 7): 119 case IP_VERSION(13, 0, 10): 120 case IP_VERSION(13, 0, 14): 121 err = psp_init_sos_microcode(psp, ucode_prefix); 122 if (err) 123 return err; 124 /* It's not necessary to load ras ta on Guest side */ 125 err = psp_init_ta_microcode(psp, ucode_prefix); 126 if (err) 127 return err; 128 break; 129 default: 130 BUG(); 131 } 132 133 return 0; 134 } 135 136 static bool psp_v13_0_is_sos_alive(struct psp_context *psp) 137 { 138 struct amdgpu_device *adev = psp->adev; 139 uint32_t sol_reg; 140 141 sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81); 142 143 return sol_reg != 0x0; 144 } 145 146 static int psp_v13_0_wait_for_vmbx_ready(struct psp_context *psp) 147 { 148 struct amdgpu_device *adev = psp->adev; 149 int retry_loop, ret; 150 151 for (retry_loop = 0; retry_loop < PSP_VMBX_POLLING_LIMIT; retry_loop++) { 152 /* Wait for bootloader to signify that is 153 ready having bit 31 of C2PMSG_33 set to 1 */ 154 ret = psp_wait_for( 155 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_33), 156 0x80000000, 0xffffffff, false); 157 158 if (ret == 0) 159 break; 160 } 161 162 if (ret) 163 dev_warn(adev->dev, "Bootloader wait timed out"); 164 165 return ret; 166 } 167 168 static int psp_v13_0_wait_for_bootloader(struct psp_context *psp) 169 { 170 struct amdgpu_device *adev = psp->adev; 171 int retry_loop, retry_cnt, ret; 172 173 retry_cnt = 174 ((amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) || 175 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14))) ? 176 PSP_VMBX_POLLING_LIMIT : 177 10; 178 /* Wait for bootloader to signify that it is ready having bit 31 of 179 * C2PMSG_35 set to 1. All other bits are expected to be cleared. 180 * If there is an error in processing command, bits[7:0] will be set. 181 * This is applicable for PSP v13.0.6 and newer. 182 */ 183 for (retry_loop = 0; retry_loop < retry_cnt; retry_loop++) { 184 ret = psp_wait_for( 185 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 186 0x80000000, 0xffffffff, false); 187 188 if (ret == 0) 189 return 0; 190 } 191 192 return ret; 193 } 194 195 static int psp_v13_0_wait_for_bootloader_steady_state(struct psp_context *psp) 196 { 197 struct amdgpu_device *adev = psp->adev; 198 int ret; 199 200 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) || 201 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14)) { 202 ret = psp_v13_0_wait_for_vmbx_ready(psp); 203 if (ret) 204 amdgpu_ras_query_boot_status(adev, 4); 205 206 ret = psp_v13_0_wait_for_bootloader(psp); 207 if (ret) 208 amdgpu_ras_query_boot_status(adev, 4); 209 210 return ret; 211 } 212 213 return 0; 214 } 215 216 static int psp_v13_0_bootloader_load_component(struct psp_context *psp, 217 struct psp_bin_desc *bin_desc, 218 enum psp_bootloader_cmd bl_cmd) 219 { 220 int ret; 221 uint32_t psp_gfxdrv_command_reg = 0; 222 struct amdgpu_device *adev = psp->adev; 223 224 /* Check tOS sign of life register to confirm sys driver and sOS 225 * are already been loaded. 226 */ 227 if (psp_v13_0_is_sos_alive(psp)) 228 return 0; 229 230 ret = psp_v13_0_wait_for_bootloader(psp); 231 if (ret) 232 return ret; 233 234 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 235 236 /* Copy PSP KDB binary to memory */ 237 memcpy(psp->fw_pri_buf, bin_desc->start_addr, bin_desc->size_bytes); 238 239 /* Provide the PSP KDB to bootloader */ 240 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, 241 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 242 psp_gfxdrv_command_reg = bl_cmd; 243 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, 244 psp_gfxdrv_command_reg); 245 246 ret = psp_v13_0_wait_for_bootloader(psp); 247 248 return ret; 249 } 250 251 static int psp_v13_0_bootloader_load_kdb(struct psp_context *psp) 252 { 253 return psp_v13_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_KEY_DATABASE); 254 } 255 256 static int psp_v13_0_bootloader_load_spl(struct psp_context *psp) 257 { 258 return psp_v13_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_TOS_SPL_TABLE); 259 } 260 261 static int psp_v13_0_bootloader_load_sysdrv(struct psp_context *psp) 262 { 263 return psp_v13_0_bootloader_load_component(psp, &psp->sys, PSP_BL__LOAD_SYSDRV); 264 } 265 266 static int psp_v13_0_bootloader_load_soc_drv(struct psp_context *psp) 267 { 268 return psp_v13_0_bootloader_load_component(psp, &psp->soc_drv, PSP_BL__LOAD_SOCDRV); 269 } 270 271 static int psp_v13_0_bootloader_load_intf_drv(struct psp_context *psp) 272 { 273 return psp_v13_0_bootloader_load_component(psp, &psp->intf_drv, PSP_BL__LOAD_INTFDRV); 274 } 275 276 static int psp_v13_0_bootloader_load_dbg_drv(struct psp_context *psp) 277 { 278 return psp_v13_0_bootloader_load_component(psp, &psp->dbg_drv, PSP_BL__LOAD_DBGDRV); 279 } 280 281 static int psp_v13_0_bootloader_load_ras_drv(struct psp_context *psp) 282 { 283 return psp_v13_0_bootloader_load_component(psp, &psp->ras_drv, PSP_BL__LOAD_RASDRV); 284 } 285 286 static inline void psp_v13_0_init_sos_version(struct psp_context *psp) 287 { 288 struct amdgpu_device *adev = psp->adev; 289 290 psp->sos.fw_version = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_58); 291 } 292 293 static int psp_v13_0_bootloader_load_sos(struct psp_context *psp) 294 { 295 int ret; 296 unsigned int psp_gfxdrv_command_reg = 0; 297 struct amdgpu_device *adev = psp->adev; 298 299 /* Check sOS sign of life register to confirm sys driver and sOS 300 * are already been loaded. 301 */ 302 if (psp_v13_0_is_sos_alive(psp)) { 303 psp_v13_0_init_sos_version(psp); 304 return 0; 305 } 306 307 ret = psp_v13_0_wait_for_bootloader(psp); 308 if (ret) 309 return ret; 310 311 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 312 313 /* Copy Secure OS binary to PSP memory */ 314 memcpy(psp->fw_pri_buf, psp->sos.start_addr, psp->sos.size_bytes); 315 316 /* Provide the PSP secure OS to bootloader */ 317 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, 318 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 319 psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV; 320 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, 321 psp_gfxdrv_command_reg); 322 323 /* there might be handshake issue with hardware which needs delay */ 324 mdelay(20); 325 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_81), 326 RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81), 327 0, true); 328 329 if (!ret) 330 psp_v13_0_init_sos_version(psp); 331 332 return ret; 333 } 334 335 static int psp_v13_0_ring_stop(struct psp_context *psp, 336 enum psp_ring_type ring_type) 337 { 338 int ret = 0; 339 struct amdgpu_device *adev = psp->adev; 340 341 if (amdgpu_sriov_vf(adev)) { 342 /* Write the ring destroy command*/ 343 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, 344 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING); 345 /* there might be handshake issue with hardware which needs delay */ 346 mdelay(20); 347 /* Wait for response flag (bit 31) */ 348 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101), 349 0x80000000, 0x80000000, false); 350 } else { 351 /* Write the ring destroy command*/ 352 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, 353 GFX_CTRL_CMD_ID_DESTROY_RINGS); 354 /* there might be handshake issue with hardware which needs delay */ 355 mdelay(20); 356 /* Wait for response flag (bit 31) */ 357 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), 358 0x80000000, 0x80000000, false); 359 } 360 361 return ret; 362 } 363 364 static int psp_v13_0_ring_create(struct psp_context *psp, 365 enum psp_ring_type ring_type) 366 { 367 int ret = 0; 368 unsigned int psp_ring_reg = 0; 369 struct psp_ring *ring = &psp->km_ring; 370 struct amdgpu_device *adev = psp->adev; 371 372 if (amdgpu_sriov_vf(adev)) { 373 ret = psp_v13_0_ring_stop(psp, ring_type); 374 if (ret) { 375 DRM_ERROR("psp_v13_0_ring_stop_sriov failed!\n"); 376 return ret; 377 } 378 379 /* Write low address of the ring to C2PMSG_102 */ 380 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 381 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, psp_ring_reg); 382 /* Write high address of the ring to C2PMSG_103 */ 383 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 384 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_103, psp_ring_reg); 385 386 /* Write the ring initialization command to C2PMSG_101 */ 387 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, 388 GFX_CTRL_CMD_ID_INIT_GPCOM_RING); 389 390 /* there might be handshake issue with hardware which needs delay */ 391 mdelay(20); 392 393 /* Wait for response flag (bit 31) in C2PMSG_101 */ 394 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101), 395 0x80000000, 0x8000FFFF, false); 396 397 } else { 398 /* Wait for sOS ready for ring creation */ 399 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), 400 0x80000000, 0x80000000, false); 401 if (ret) { 402 DRM_ERROR("Failed to wait for trust OS ready for ring creation\n"); 403 return ret; 404 } 405 406 /* Write low address of the ring to C2PMSG_69 */ 407 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 408 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_69, psp_ring_reg); 409 /* Write high address of the ring to C2PMSG_70 */ 410 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 411 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_70, psp_ring_reg); 412 /* Write size of ring to C2PMSG_71 */ 413 psp_ring_reg = ring->ring_size; 414 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_71, psp_ring_reg); 415 /* Write the ring initialization command to C2PMSG_64 */ 416 psp_ring_reg = ring_type; 417 psp_ring_reg = psp_ring_reg << 16; 418 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, psp_ring_reg); 419 420 /* there might be handshake issue with hardware which needs delay */ 421 mdelay(20); 422 423 /* Wait for response flag (bit 31) in C2PMSG_64 */ 424 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), 425 0x80000000, 0x8000FFFF, false); 426 } 427 428 return ret; 429 } 430 431 static int psp_v13_0_ring_destroy(struct psp_context *psp, 432 enum psp_ring_type ring_type) 433 { 434 int ret = 0; 435 struct psp_ring *ring = &psp->km_ring; 436 struct amdgpu_device *adev = psp->adev; 437 438 ret = psp_v13_0_ring_stop(psp, ring_type); 439 if (ret) 440 DRM_ERROR("Fail to stop psp ring\n"); 441 442 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 443 &ring->ring_mem_mc_addr, 444 (void **)&ring->ring_mem); 445 446 return ret; 447 } 448 449 static uint32_t psp_v13_0_ring_get_wptr(struct psp_context *psp) 450 { 451 uint32_t data; 452 struct amdgpu_device *adev = psp->adev; 453 454 if (amdgpu_sriov_vf(adev)) 455 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102); 456 else 457 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67); 458 459 return data; 460 } 461 462 static void psp_v13_0_ring_set_wptr(struct psp_context *psp, uint32_t value) 463 { 464 struct amdgpu_device *adev = psp->adev; 465 466 if (amdgpu_sriov_vf(adev)) { 467 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, value); 468 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, 469 GFX_CTRL_CMD_ID_CONSUME_CMD); 470 } else 471 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67, value); 472 } 473 474 static int psp_v13_0_memory_training_send_msg(struct psp_context *psp, int msg) 475 { 476 int ret; 477 int i; 478 uint32_t data_32; 479 int max_wait; 480 struct amdgpu_device *adev = psp->adev; 481 482 data_32 = (psp->mem_train_ctx.c2p_train_data_offset >> 20); 483 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, data_32); 484 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, msg); 485 486 max_wait = MEM_TRAIN_SEND_MSG_TIMEOUT_US / adev->usec_timeout; 487 for (i = 0; i < max_wait; i++) { 488 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 489 0x80000000, 0x80000000, false); 490 if (ret == 0) 491 break; 492 } 493 if (i < max_wait) 494 ret = 0; 495 else 496 ret = -ETIME; 497 498 dev_dbg(adev->dev, "training %s %s, cost %d @ %d ms\n", 499 (msg == PSP_BL__DRAM_SHORT_TRAIN) ? "short" : "long", 500 (ret == 0) ? "succeed" : "failed", 501 i, adev->usec_timeout/1000); 502 return ret; 503 } 504 505 506 static int psp_v13_0_memory_training(struct psp_context *psp, uint32_t ops) 507 { 508 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 509 uint32_t *pcache = (uint32_t *)ctx->sys_cache; 510 struct amdgpu_device *adev = psp->adev; 511 uint32_t p2c_header[4]; 512 uint32_t sz; 513 void *buf; 514 int ret, idx; 515 516 if (ctx->init == PSP_MEM_TRAIN_NOT_SUPPORT) { 517 dev_dbg(adev->dev, "Memory training is not supported.\n"); 518 return 0; 519 } else if (ctx->init != PSP_MEM_TRAIN_INIT_SUCCESS) { 520 dev_err(adev->dev, "Memory training initialization failure.\n"); 521 return -EINVAL; 522 } 523 524 if (psp_v13_0_is_sos_alive(psp)) { 525 dev_dbg(adev->dev, "SOS is alive, skip memory training.\n"); 526 return 0; 527 } 528 529 amdgpu_device_vram_access(adev, ctx->p2c_train_data_offset, p2c_header, sizeof(p2c_header), false); 530 dev_dbg(adev->dev, "sys_cache[%08x,%08x,%08x,%08x] p2c_header[%08x,%08x,%08x,%08x]\n", 531 pcache[0], pcache[1], pcache[2], pcache[3], 532 p2c_header[0], p2c_header[1], p2c_header[2], p2c_header[3]); 533 534 if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) { 535 dev_dbg(adev->dev, "Short training depends on restore.\n"); 536 ops |= PSP_MEM_TRAIN_RESTORE; 537 } 538 539 if ((ops & PSP_MEM_TRAIN_RESTORE) && 540 pcache[0] != MEM_TRAIN_SYSTEM_SIGNATURE) { 541 dev_dbg(adev->dev, "sys_cache[0] is invalid, restore depends on save.\n"); 542 ops |= PSP_MEM_TRAIN_SAVE; 543 } 544 545 if (p2c_header[0] == MEM_TRAIN_SYSTEM_SIGNATURE && 546 !(pcache[0] == MEM_TRAIN_SYSTEM_SIGNATURE && 547 pcache[3] == p2c_header[3])) { 548 dev_dbg(adev->dev, "sys_cache is invalid or out-of-date, need save training data to sys_cache.\n"); 549 ops |= PSP_MEM_TRAIN_SAVE; 550 } 551 552 if ((ops & PSP_MEM_TRAIN_SAVE) && 553 p2c_header[0] != MEM_TRAIN_SYSTEM_SIGNATURE) { 554 dev_dbg(adev->dev, "p2c_header[0] is invalid, save depends on long training.\n"); 555 ops |= PSP_MEM_TRAIN_SEND_LONG_MSG; 556 } 557 558 if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) { 559 ops &= ~PSP_MEM_TRAIN_SEND_SHORT_MSG; 560 ops |= PSP_MEM_TRAIN_SAVE; 561 } 562 563 dev_dbg(adev->dev, "Memory training ops:%x.\n", ops); 564 565 if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) { 566 /* 567 * Long training will encroach a certain amount on the bottom of VRAM; 568 * save the content from the bottom of VRAM to system memory 569 * before training, and restore it after training to avoid 570 * VRAM corruption. 571 */ 572 sz = BIST_MEM_TRAINING_ENCROACHED_SIZE; 573 574 if (adev->gmc.visible_vram_size < sz || !adev->mman.aper_base_kaddr) { 575 dev_err(adev->dev, "visible_vram_size %llx or aper_base_kaddr %p is not initialized.\n", 576 adev->gmc.visible_vram_size, 577 adev->mman.aper_base_kaddr); 578 return -EINVAL; 579 } 580 581 buf = vmalloc(sz); 582 if (!buf) { 583 dev_err(adev->dev, "failed to allocate system memory.\n"); 584 return -ENOMEM; 585 } 586 587 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 588 memcpy_fromio(buf, adev->mman.aper_base_kaddr, sz); 589 ret = psp_v13_0_memory_training_send_msg(psp, PSP_BL__DRAM_LONG_TRAIN); 590 if (ret) { 591 DRM_ERROR("Send long training msg failed.\n"); 592 vfree(buf); 593 drm_dev_exit(idx); 594 return ret; 595 } 596 597 memcpy_toio(adev->mman.aper_base_kaddr, buf, sz); 598 adev->hdp.funcs->flush_hdp(adev, NULL); 599 vfree(buf); 600 drm_dev_exit(idx); 601 } else { 602 vfree(buf); 603 return -ENODEV; 604 } 605 } 606 607 if (ops & PSP_MEM_TRAIN_SAVE) { 608 amdgpu_device_vram_access(psp->adev, ctx->p2c_train_data_offset, ctx->sys_cache, ctx->train_data_size, false); 609 } 610 611 if (ops & PSP_MEM_TRAIN_RESTORE) { 612 amdgpu_device_vram_access(psp->adev, ctx->c2p_train_data_offset, ctx->sys_cache, ctx->train_data_size, true); 613 } 614 615 if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) { 616 ret = psp_v13_0_memory_training_send_msg(psp, (amdgpu_force_long_training > 0) ? 617 PSP_BL__DRAM_LONG_TRAIN : PSP_BL__DRAM_SHORT_TRAIN); 618 if (ret) { 619 dev_err(adev->dev, "send training msg failed.\n"); 620 return ret; 621 } 622 } 623 ctx->training_cnt++; 624 return 0; 625 } 626 627 static int psp_v13_0_load_usbc_pd_fw(struct psp_context *psp, uint64_t fw_pri_mc_addr) 628 { 629 struct amdgpu_device *adev = psp->adev; 630 uint32_t reg_status; 631 int ret, i = 0; 632 633 /* 634 * LFB address which is aligned to 1MB address and has to be 635 * right-shifted by 20 so that LFB address can be passed on a 32-bit C2P 636 * register 637 */ 638 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, (fw_pri_mc_addr >> 20)); 639 640 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 641 0x80000000, 0x80000000, false); 642 if (ret) 643 return ret; 644 645 /* Fireup interrupt so PSP can pick up the address */ 646 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, (GFX_CMD_USB_PD_USE_LFB << 16)); 647 648 /* FW load takes very long time */ 649 do { 650 msleep(1000); 651 reg_status = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35); 652 653 if (reg_status & 0x80000000) 654 goto done; 655 656 } while (++i < USBC_PD_POLLING_LIMIT_S); 657 658 return -ETIME; 659 done: 660 661 if ((reg_status & 0xFFFF) != 0) { 662 DRM_ERROR("Address load failed - MP0_SMN_C2PMSG_35.Bits [15:0] = %04x\n", 663 reg_status & 0xFFFF); 664 return -EIO; 665 } 666 667 return 0; 668 } 669 670 static int psp_v13_0_read_usbc_pd_fw(struct psp_context *psp, uint32_t *fw_ver) 671 { 672 struct amdgpu_device *adev = psp->adev; 673 int ret; 674 675 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, C2PMSG_CMD_GFX_USB_PD_FW_VER); 676 677 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 678 0x80000000, 0x80000000, false); 679 if (!ret) 680 *fw_ver = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36); 681 682 return ret; 683 } 684 685 static int psp_v13_0_exec_spi_cmd(struct psp_context *psp, int cmd) 686 { 687 uint32_t reg_status = 0, reg_val = 0; 688 struct amdgpu_device *adev = psp->adev; 689 int ret; 690 691 /* clear MBX ready (MBOX_READY_MASK bit is 0) and set update command */ 692 reg_val |= (cmd << 16); 693 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115, reg_val); 694 695 /* Ring the doorbell */ 696 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_73, 1); 697 698 if (cmd == C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE) 699 ret = psp_wait_for_spirom_update(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115), 700 MBOX_READY_FLAG, MBOX_READY_MASK, PSP_SPIROM_UPDATE_TIMEOUT); 701 else 702 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115), 703 MBOX_READY_FLAG, MBOX_READY_MASK, false); 704 if (ret) { 705 dev_err(adev->dev, "SPI cmd %x timed out, ret = %d", cmd, ret); 706 return ret; 707 } 708 709 reg_status = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115); 710 if ((reg_status & 0xFFFF) != 0) { 711 dev_err(adev->dev, "SPI cmd %x failed, fail status = %04x\n", 712 cmd, reg_status & 0xFFFF); 713 return -EIO; 714 } 715 716 return 0; 717 } 718 719 static int psp_v13_0_update_spirom(struct psp_context *psp, 720 uint64_t fw_pri_mc_addr) 721 { 722 struct amdgpu_device *adev = psp->adev; 723 int ret; 724 725 /* Confirm PSP is ready to start */ 726 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115), 727 MBOX_READY_FLAG, MBOX_READY_MASK, false); 728 if (ret) { 729 dev_err(adev->dev, "PSP Not ready to start processing, ret = %d", ret); 730 return ret; 731 } 732 733 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, lower_32_bits(fw_pri_mc_addr)); 734 735 ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_LO); 736 if (ret) 737 return ret; 738 739 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, upper_32_bits(fw_pri_mc_addr)); 740 741 ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI); 742 if (ret) 743 return ret; 744 745 psp->vbflash_done = true; 746 747 ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE); 748 if (ret) 749 return ret; 750 751 return 0; 752 } 753 754 static int psp_v13_0_vbflash_status(struct psp_context *psp) 755 { 756 struct amdgpu_device *adev = psp->adev; 757 758 return RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115); 759 } 760 761 static int psp_v13_0_fatal_error_recovery_quirk(struct psp_context *psp) 762 { 763 struct amdgpu_device *adev = psp->adev; 764 765 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 10)) { 766 uint32_t reg_data; 767 /* MP1 fatal error: trigger PSP dram read to unhalt PSP 768 * during MP1 triggered sync flood. 769 */ 770 reg_data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67); 771 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67, reg_data + 0x10); 772 773 /* delay 1000ms for the mode1 reset for fatal error 774 * to be recovered back. 775 */ 776 msleep(1000); 777 } 778 779 return 0; 780 } 781 782 static bool psp_v13_0_get_ras_capability(struct psp_context *psp) 783 { 784 struct amdgpu_device *adev = psp->adev; 785 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 786 u32 reg_data; 787 788 /* query ras cap should be done from host side */ 789 if (amdgpu_sriov_vf(adev)) 790 return false; 791 792 if (!con) 793 return false; 794 795 if ((amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) || 796 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14)) && 797 (!(adev->flags & AMD_IS_APU))) { 798 reg_data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_127); 799 adev->ras_hw_enabled = (reg_data & GENMASK_ULL(23, 0)); 800 con->poison_supported = ((reg_data & GENMASK_ULL(24, 24)) >> 24) ? true : false; 801 return true; 802 } else { 803 return false; 804 } 805 } 806 807 static const struct psp_funcs psp_v13_0_funcs = { 808 .init_microcode = psp_v13_0_init_microcode, 809 .wait_for_bootloader = psp_v13_0_wait_for_bootloader_steady_state, 810 .bootloader_load_kdb = psp_v13_0_bootloader_load_kdb, 811 .bootloader_load_spl = psp_v13_0_bootloader_load_spl, 812 .bootloader_load_sysdrv = psp_v13_0_bootloader_load_sysdrv, 813 .bootloader_load_soc_drv = psp_v13_0_bootloader_load_soc_drv, 814 .bootloader_load_intf_drv = psp_v13_0_bootloader_load_intf_drv, 815 .bootloader_load_dbg_drv = psp_v13_0_bootloader_load_dbg_drv, 816 .bootloader_load_ras_drv = psp_v13_0_bootloader_load_ras_drv, 817 .bootloader_load_sos = psp_v13_0_bootloader_load_sos, 818 .ring_create = psp_v13_0_ring_create, 819 .ring_stop = psp_v13_0_ring_stop, 820 .ring_destroy = psp_v13_0_ring_destroy, 821 .ring_get_wptr = psp_v13_0_ring_get_wptr, 822 .ring_set_wptr = psp_v13_0_ring_set_wptr, 823 .mem_training = psp_v13_0_memory_training, 824 .load_usbc_pd_fw = psp_v13_0_load_usbc_pd_fw, 825 .read_usbc_pd_fw = psp_v13_0_read_usbc_pd_fw, 826 .update_spirom = psp_v13_0_update_spirom, 827 .vbflash_stat = psp_v13_0_vbflash_status, 828 .fatal_error_recovery_quirk = psp_v13_0_fatal_error_recovery_quirk, 829 .get_ras_capability = psp_v13_0_get_ras_capability, 830 }; 831 832 void psp_v13_0_set_psp_funcs(struct psp_context *psp) 833 { 834 psp->funcs = &psp_v13_0_funcs; 835 } 836