1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <drm/drm_drv.h> 24 #include <linux/vmalloc.h> 25 #include "amdgpu.h" 26 #include "amdgpu_psp.h" 27 #include "amdgpu_ucode.h" 28 #include "soc15_common.h" 29 #include "psp_v13_0.h" 30 #include "amdgpu_ras.h" 31 32 #include "mp/mp_13_0_2_offset.h" 33 #include "mp/mp_13_0_2_sh_mask.h" 34 35 MODULE_FIRMWARE("amdgpu/aldebaran_sos.bin"); 36 MODULE_FIRMWARE("amdgpu/aldebaran_ta.bin"); 37 MODULE_FIRMWARE("amdgpu/aldebaran_cap.bin"); 38 MODULE_FIRMWARE("amdgpu/yellow_carp_toc.bin"); 39 MODULE_FIRMWARE("amdgpu/yellow_carp_ta.bin"); 40 MODULE_FIRMWARE("amdgpu/psp_13_0_5_toc.bin"); 41 MODULE_FIRMWARE("amdgpu/psp_13_0_5_ta.bin"); 42 MODULE_FIRMWARE("amdgpu/psp_13_0_8_toc.bin"); 43 MODULE_FIRMWARE("amdgpu/psp_13_0_8_ta.bin"); 44 MODULE_FIRMWARE("amdgpu/psp_13_0_0_sos.bin"); 45 MODULE_FIRMWARE("amdgpu/psp_13_0_0_ta.bin"); 46 MODULE_FIRMWARE("amdgpu/psp_13_0_7_sos.bin"); 47 MODULE_FIRMWARE("amdgpu/psp_13_0_7_ta.bin"); 48 MODULE_FIRMWARE("amdgpu/psp_13_0_10_sos.bin"); 49 MODULE_FIRMWARE("amdgpu/psp_13_0_10_ta.bin"); 50 MODULE_FIRMWARE("amdgpu/psp_13_0_11_toc.bin"); 51 MODULE_FIRMWARE("amdgpu/psp_13_0_11_ta.bin"); 52 MODULE_FIRMWARE("amdgpu/psp_13_0_6_sos.bin"); 53 MODULE_FIRMWARE("amdgpu/psp_13_0_6_ta.bin"); 54 MODULE_FIRMWARE("amdgpu/psp_13_0_12_sos.bin"); 55 MODULE_FIRMWARE("amdgpu/psp_13_0_12_ta.bin"); 56 MODULE_FIRMWARE("amdgpu/psp_13_0_14_sos.bin"); 57 MODULE_FIRMWARE("amdgpu/psp_13_0_14_ta.bin"); 58 MODULE_FIRMWARE("amdgpu/psp_14_0_0_toc.bin"); 59 MODULE_FIRMWARE("amdgpu/psp_14_0_0_ta.bin"); 60 MODULE_FIRMWARE("amdgpu/psp_14_0_1_toc.bin"); 61 MODULE_FIRMWARE("amdgpu/psp_14_0_1_ta.bin"); 62 MODULE_FIRMWARE("amdgpu/psp_14_0_4_toc.bin"); 63 MODULE_FIRMWARE("amdgpu/psp_14_0_4_ta.bin"); 64 65 /* For large FW files the time to complete can be very long */ 66 #define USBC_PD_POLLING_LIMIT_S 240 67 68 /* Read USB-PD from LFB */ 69 #define GFX_CMD_USB_PD_USE_LFB 0x480 70 71 /* Retry times for vmbx ready wait */ 72 #define PSP_VMBX_POLLING_LIMIT 3000 73 74 /* memory training timeout define */ 75 #define MEM_TRAIN_SEND_MSG_TIMEOUT_US 3000000 76 77 #define regMP1_PUB_SCRATCH0 0x3b10090 78 79 #define PSP13_BL_STATUS_SIZE 100 80 81 static int psp_v13_0_init_microcode(struct psp_context *psp) 82 { 83 struct amdgpu_device *adev = psp->adev; 84 char ucode_prefix[30]; 85 int err = 0; 86 87 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); 88 89 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 90 case IP_VERSION(13, 0, 2): 91 err = psp_init_sos_microcode(psp, ucode_prefix); 92 if (err) 93 return err; 94 /* It's not necessary to load ras ta on Guest side */ 95 if (!amdgpu_sriov_vf(adev)) { 96 err = psp_init_ta_microcode(psp, ucode_prefix); 97 if (err) 98 return err; 99 } 100 break; 101 case IP_VERSION(13, 0, 1): 102 case IP_VERSION(13, 0, 3): 103 case IP_VERSION(13, 0, 5): 104 case IP_VERSION(13, 0, 8): 105 case IP_VERSION(13, 0, 11): 106 case IP_VERSION(14, 0, 0): 107 case IP_VERSION(14, 0, 1): 108 case IP_VERSION(14, 0, 4): 109 err = psp_init_toc_microcode(psp, ucode_prefix); 110 if (err) 111 return err; 112 err = psp_init_ta_microcode(psp, ucode_prefix); 113 if (err) 114 return err; 115 break; 116 case IP_VERSION(13, 0, 0): 117 case IP_VERSION(13, 0, 6): 118 case IP_VERSION(13, 0, 7): 119 case IP_VERSION(13, 0, 10): 120 case IP_VERSION(13, 0, 12): 121 case IP_VERSION(13, 0, 14): 122 err = psp_init_sos_microcode(psp, ucode_prefix); 123 if (err) 124 return err; 125 /* It's not necessary to load ras ta on Guest side */ 126 err = psp_init_ta_microcode(psp, ucode_prefix); 127 if (err) 128 return err; 129 break; 130 default: 131 BUG(); 132 } 133 134 return 0; 135 } 136 137 static bool psp_v13_0_is_sos_alive(struct psp_context *psp) 138 { 139 struct amdgpu_device *adev = psp->adev; 140 uint32_t sol_reg; 141 142 sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81); 143 144 return sol_reg != 0x0; 145 } 146 147 static void psp_v13_0_bootloader_print_status(struct psp_context *psp, 148 const char *msg) 149 { 150 struct amdgpu_device *adev = psp->adev; 151 u32 bl_status_reg; 152 char bl_status_msg[PSP13_BL_STATUS_SIZE]; 153 int i, at; 154 155 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) || 156 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 12) || 157 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14)) { 158 at = 0; 159 for_each_inst(i, adev->aid_mask) { 160 bl_status_reg = 161 (SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_92) 162 << 2) + 163 adev->asic_funcs->encode_ext_smn_addressing(i); 164 at += snprintf(bl_status_msg + at, 165 PSP13_BL_STATUS_SIZE - at, 166 " status(%02i): 0x%08x", i, 167 RREG32_PCIE_EXT(bl_status_reg)); 168 } 169 dev_info(adev->dev, "%s - %s", msg, bl_status_msg); 170 } 171 } 172 173 static int psp_v13_0_wait_for_vmbx_ready(struct psp_context *psp) 174 { 175 struct amdgpu_device *adev = psp->adev; 176 int retry_loop, ret; 177 178 for (retry_loop = 0; retry_loop < PSP_VMBX_POLLING_LIMIT; retry_loop++) { 179 /* Wait for bootloader to signify that is 180 ready having bit 31 of C2PMSG_33 set to 1 */ 181 ret = psp_wait_for( 182 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_33), 183 0x80000000, 0xffffffff, false); 184 185 if (ret == 0) 186 break; 187 } 188 189 if (ret) 190 dev_warn(adev->dev, "Bootloader wait timed out"); 191 192 return ret; 193 } 194 195 static int psp_v13_0_wait_for_bootloader(struct psp_context *psp) 196 { 197 struct amdgpu_device *adev = psp->adev; 198 int retry_loop, retry_cnt, ret; 199 200 retry_cnt = 201 ((amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) || 202 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 12) || 203 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14))) ? 204 PSP_VMBX_POLLING_LIMIT : 205 10; 206 /* Wait for bootloader to signify that it is ready having bit 31 of 207 * C2PMSG_35 set to 1. All other bits are expected to be cleared. 208 * If there is an error in processing command, bits[7:0] will be set. 209 * This is applicable for PSP v13.0.6 and newer. 210 */ 211 for (retry_loop = 0; retry_loop < retry_cnt; retry_loop++) { 212 ret = psp_wait_for( 213 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 214 0x80000000, 0xffffffff, false); 215 216 if (ret == 0) 217 return 0; 218 if (retry_loop && !(retry_loop % 10)) 219 psp_v13_0_bootloader_print_status( 220 psp, "Waiting for bootloader completion"); 221 } 222 223 return ret; 224 } 225 226 static int psp_v13_0_wait_for_bootloader_steady_state(struct psp_context *psp) 227 { 228 struct amdgpu_device *adev = psp->adev; 229 int ret; 230 231 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) || 232 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 12) || 233 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14)) { 234 ret = psp_v13_0_wait_for_vmbx_ready(psp); 235 if (ret) 236 amdgpu_ras_query_boot_status(adev, 4); 237 238 ret = psp_v13_0_wait_for_bootloader(psp); 239 if (ret) 240 amdgpu_ras_query_boot_status(adev, 4); 241 242 return ret; 243 } 244 245 return 0; 246 } 247 248 static int psp_v13_0_bootloader_load_component(struct psp_context *psp, 249 struct psp_bin_desc *bin_desc, 250 enum psp_bootloader_cmd bl_cmd) 251 { 252 int ret; 253 uint32_t psp_gfxdrv_command_reg = 0; 254 struct amdgpu_device *adev = psp->adev; 255 256 /* Check tOS sign of life register to confirm sys driver and sOS 257 * are already been loaded. 258 */ 259 if (psp_v13_0_is_sos_alive(psp)) 260 return 0; 261 262 ret = psp_v13_0_wait_for_bootloader(psp); 263 if (ret) 264 return ret; 265 266 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 267 268 /* Copy PSP KDB binary to memory */ 269 memcpy(psp->fw_pri_buf, bin_desc->start_addr, bin_desc->size_bytes); 270 271 /* Provide the PSP KDB to bootloader */ 272 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, 273 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 274 psp_gfxdrv_command_reg = bl_cmd; 275 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, 276 psp_gfxdrv_command_reg); 277 278 ret = psp_v13_0_wait_for_bootloader(psp); 279 280 return ret; 281 } 282 283 static int psp_v13_0_bootloader_load_kdb(struct psp_context *psp) 284 { 285 return psp_v13_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_KEY_DATABASE); 286 } 287 288 static int psp_v13_0_bootloader_load_spl(struct psp_context *psp) 289 { 290 return psp_v13_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_TOS_SPL_TABLE); 291 } 292 293 static int psp_v13_0_bootloader_load_sysdrv(struct psp_context *psp) 294 { 295 return psp_v13_0_bootloader_load_component(psp, &psp->sys, PSP_BL__LOAD_SYSDRV); 296 } 297 298 static int psp_v13_0_bootloader_load_soc_drv(struct psp_context *psp) 299 { 300 return psp_v13_0_bootloader_load_component(psp, &psp->soc_drv, PSP_BL__LOAD_SOCDRV); 301 } 302 303 static int psp_v13_0_bootloader_load_intf_drv(struct psp_context *psp) 304 { 305 return psp_v13_0_bootloader_load_component(psp, &psp->intf_drv, PSP_BL__LOAD_INTFDRV); 306 } 307 308 static int psp_v13_0_bootloader_load_dbg_drv(struct psp_context *psp) 309 { 310 return psp_v13_0_bootloader_load_component(psp, &psp->dbg_drv, PSP_BL__LOAD_DBGDRV); 311 } 312 313 static int psp_v13_0_bootloader_load_ras_drv(struct psp_context *psp) 314 { 315 return psp_v13_0_bootloader_load_component(psp, &psp->ras_drv, PSP_BL__LOAD_RASDRV); 316 } 317 318 static int psp_v13_0_bootloader_load_spdm_drv(struct psp_context *psp) 319 { 320 return psp_v13_0_bootloader_load_component(psp, &psp->spdm_drv, PSP_BL__LOAD_SPDMDRV); 321 } 322 323 static inline void psp_v13_0_init_sos_version(struct psp_context *psp) 324 { 325 struct amdgpu_device *adev = psp->adev; 326 327 psp->sos.fw_version = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_58); 328 } 329 330 static int psp_v13_0_bootloader_load_sos(struct psp_context *psp) 331 { 332 int ret; 333 unsigned int psp_gfxdrv_command_reg = 0; 334 struct amdgpu_device *adev = psp->adev; 335 336 /* Check sOS sign of life register to confirm sys driver and sOS 337 * are already been loaded. 338 */ 339 if (psp_v13_0_is_sos_alive(psp)) { 340 psp_v13_0_init_sos_version(psp); 341 return 0; 342 } 343 344 ret = psp_v13_0_wait_for_bootloader(psp); 345 if (ret) 346 return ret; 347 348 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 349 350 /* Copy Secure OS binary to PSP memory */ 351 memcpy(psp->fw_pri_buf, psp->sos.start_addr, psp->sos.size_bytes); 352 353 /* Provide the PSP secure OS to bootloader */ 354 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, 355 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 356 psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV; 357 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, 358 psp_gfxdrv_command_reg); 359 360 /* there might be handshake issue with hardware which needs delay */ 361 mdelay(20); 362 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_81), 363 RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81), 364 0, true); 365 366 if (!ret) 367 psp_v13_0_init_sos_version(psp); 368 369 return ret; 370 } 371 372 static int psp_v13_0_ring_stop(struct psp_context *psp, 373 enum psp_ring_type ring_type) 374 { 375 int ret = 0; 376 struct amdgpu_device *adev = psp->adev; 377 378 if (amdgpu_sriov_vf(adev)) { 379 /* Write the ring destroy command*/ 380 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, 381 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING); 382 /* there might be handshake issue with hardware which needs delay */ 383 mdelay(20); 384 /* Wait for response flag (bit 31) */ 385 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101), 386 0x80000000, 0x80000000, false); 387 } else { 388 /* Write the ring destroy command*/ 389 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, 390 GFX_CTRL_CMD_ID_DESTROY_RINGS); 391 /* there might be handshake issue with hardware which needs delay */ 392 mdelay(20); 393 /* Wait for response flag (bit 31) */ 394 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), 395 0x80000000, 0x80000000, false); 396 } 397 398 return ret; 399 } 400 401 static int psp_v13_0_ring_create(struct psp_context *psp, 402 enum psp_ring_type ring_type) 403 { 404 int ret = 0; 405 unsigned int psp_ring_reg = 0; 406 struct psp_ring *ring = &psp->km_ring; 407 struct amdgpu_device *adev = psp->adev; 408 409 if (amdgpu_sriov_vf(adev)) { 410 ret = psp_v13_0_ring_stop(psp, ring_type); 411 if (ret) { 412 DRM_ERROR("psp_v13_0_ring_stop_sriov failed!\n"); 413 return ret; 414 } 415 416 /* Write low address of the ring to C2PMSG_102 */ 417 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 418 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, psp_ring_reg); 419 /* Write high address of the ring to C2PMSG_103 */ 420 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 421 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_103, psp_ring_reg); 422 423 /* Write the ring initialization command to C2PMSG_101 */ 424 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, 425 GFX_CTRL_CMD_ID_INIT_GPCOM_RING); 426 427 /* there might be handshake issue with hardware which needs delay */ 428 mdelay(20); 429 430 /* Wait for response flag (bit 31) in C2PMSG_101 */ 431 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101), 432 0x80000000, 0x8000FFFF, false); 433 434 } else { 435 /* Wait for sOS ready for ring creation */ 436 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), 437 0x80000000, 0x80000000, false); 438 if (ret) { 439 DRM_ERROR("Failed to wait for trust OS ready for ring creation\n"); 440 return ret; 441 } 442 443 /* Write low address of the ring to C2PMSG_69 */ 444 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 445 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_69, psp_ring_reg); 446 /* Write high address of the ring to C2PMSG_70 */ 447 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 448 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_70, psp_ring_reg); 449 /* Write size of ring to C2PMSG_71 */ 450 psp_ring_reg = ring->ring_size; 451 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_71, psp_ring_reg); 452 /* Write the ring initialization command to C2PMSG_64 */ 453 psp_ring_reg = ring_type; 454 psp_ring_reg = psp_ring_reg << 16; 455 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, psp_ring_reg); 456 457 /* there might be handshake issue with hardware which needs delay */ 458 mdelay(20); 459 460 /* Wait for response flag (bit 31) in C2PMSG_64 */ 461 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), 462 0x80000000, 0x8000FFFF, false); 463 } 464 465 return ret; 466 } 467 468 static int psp_v13_0_ring_destroy(struct psp_context *psp, 469 enum psp_ring_type ring_type) 470 { 471 int ret = 0; 472 struct psp_ring *ring = &psp->km_ring; 473 struct amdgpu_device *adev = psp->adev; 474 475 ret = psp_v13_0_ring_stop(psp, ring_type); 476 if (ret) 477 DRM_ERROR("Fail to stop psp ring\n"); 478 479 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 480 &ring->ring_mem_mc_addr, 481 (void **)&ring->ring_mem); 482 483 return ret; 484 } 485 486 static uint32_t psp_v13_0_ring_get_wptr(struct psp_context *psp) 487 { 488 uint32_t data; 489 struct amdgpu_device *adev = psp->adev; 490 491 if (amdgpu_sriov_vf(adev)) 492 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102); 493 else 494 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67); 495 496 return data; 497 } 498 499 static void psp_v13_0_ring_set_wptr(struct psp_context *psp, uint32_t value) 500 { 501 struct amdgpu_device *adev = psp->adev; 502 503 if (amdgpu_sriov_vf(adev)) { 504 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, value); 505 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, 506 GFX_CTRL_CMD_ID_CONSUME_CMD); 507 } else 508 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67, value); 509 } 510 511 static int psp_v13_0_memory_training_send_msg(struct psp_context *psp, int msg) 512 { 513 int ret; 514 int i; 515 uint32_t data_32; 516 int max_wait; 517 struct amdgpu_device *adev = psp->adev; 518 519 data_32 = (psp->mem_train_ctx.c2p_train_data_offset >> 20); 520 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, data_32); 521 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, msg); 522 523 max_wait = MEM_TRAIN_SEND_MSG_TIMEOUT_US / adev->usec_timeout; 524 for (i = 0; i < max_wait; i++) { 525 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 526 0x80000000, 0x80000000, false); 527 if (ret == 0) 528 break; 529 } 530 if (i < max_wait) 531 ret = 0; 532 else 533 ret = -ETIME; 534 535 dev_dbg(adev->dev, "training %s %s, cost %d @ %d ms\n", 536 (msg == PSP_BL__DRAM_SHORT_TRAIN) ? "short" : "long", 537 (ret == 0) ? "succeed" : "failed", 538 i, adev->usec_timeout/1000); 539 return ret; 540 } 541 542 543 static int psp_v13_0_memory_training(struct psp_context *psp, uint32_t ops) 544 { 545 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 546 uint32_t *pcache = (uint32_t *)ctx->sys_cache; 547 struct amdgpu_device *adev = psp->adev; 548 uint32_t p2c_header[4]; 549 uint32_t sz; 550 void *buf; 551 int ret, idx; 552 553 if (ctx->init == PSP_MEM_TRAIN_NOT_SUPPORT) { 554 dev_dbg(adev->dev, "Memory training is not supported.\n"); 555 return 0; 556 } else if (ctx->init != PSP_MEM_TRAIN_INIT_SUCCESS) { 557 dev_err(adev->dev, "Memory training initialization failure.\n"); 558 return -EINVAL; 559 } 560 561 if (psp_v13_0_is_sos_alive(psp)) { 562 dev_dbg(adev->dev, "SOS is alive, skip memory training.\n"); 563 return 0; 564 } 565 566 amdgpu_device_vram_access(adev, ctx->p2c_train_data_offset, p2c_header, sizeof(p2c_header), false); 567 dev_dbg(adev->dev, "sys_cache[%08x,%08x,%08x,%08x] p2c_header[%08x,%08x,%08x,%08x]\n", 568 pcache[0], pcache[1], pcache[2], pcache[3], 569 p2c_header[0], p2c_header[1], p2c_header[2], p2c_header[3]); 570 571 if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) { 572 dev_dbg(adev->dev, "Short training depends on restore.\n"); 573 ops |= PSP_MEM_TRAIN_RESTORE; 574 } 575 576 if ((ops & PSP_MEM_TRAIN_RESTORE) && 577 pcache[0] != MEM_TRAIN_SYSTEM_SIGNATURE) { 578 dev_dbg(adev->dev, "sys_cache[0] is invalid, restore depends on save.\n"); 579 ops |= PSP_MEM_TRAIN_SAVE; 580 } 581 582 if (p2c_header[0] == MEM_TRAIN_SYSTEM_SIGNATURE && 583 !(pcache[0] == MEM_TRAIN_SYSTEM_SIGNATURE && 584 pcache[3] == p2c_header[3])) { 585 dev_dbg(adev->dev, "sys_cache is invalid or out-of-date, need save training data to sys_cache.\n"); 586 ops |= PSP_MEM_TRAIN_SAVE; 587 } 588 589 if ((ops & PSP_MEM_TRAIN_SAVE) && 590 p2c_header[0] != MEM_TRAIN_SYSTEM_SIGNATURE) { 591 dev_dbg(adev->dev, "p2c_header[0] is invalid, save depends on long training.\n"); 592 ops |= PSP_MEM_TRAIN_SEND_LONG_MSG; 593 } 594 595 if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) { 596 ops &= ~PSP_MEM_TRAIN_SEND_SHORT_MSG; 597 ops |= PSP_MEM_TRAIN_SAVE; 598 } 599 600 dev_dbg(adev->dev, "Memory training ops:%x.\n", ops); 601 602 if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) { 603 /* 604 * Long training will encroach a certain amount on the bottom of VRAM; 605 * save the content from the bottom of VRAM to system memory 606 * before training, and restore it after training to avoid 607 * VRAM corruption. 608 */ 609 sz = BIST_MEM_TRAINING_ENCROACHED_SIZE; 610 611 if (adev->gmc.visible_vram_size < sz || !adev->mman.aper_base_kaddr) { 612 dev_err(adev->dev, "visible_vram_size %llx or aper_base_kaddr %p is not initialized.\n", 613 adev->gmc.visible_vram_size, 614 adev->mman.aper_base_kaddr); 615 return -EINVAL; 616 } 617 618 buf = vmalloc(sz); 619 if (!buf) { 620 dev_err(adev->dev, "failed to allocate system memory.\n"); 621 return -ENOMEM; 622 } 623 624 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 625 memcpy_fromio(buf, adev->mman.aper_base_kaddr, sz); 626 ret = psp_v13_0_memory_training_send_msg(psp, PSP_BL__DRAM_LONG_TRAIN); 627 if (ret) { 628 DRM_ERROR("Send long training msg failed.\n"); 629 vfree(buf); 630 drm_dev_exit(idx); 631 return ret; 632 } 633 634 memcpy_toio(adev->mman.aper_base_kaddr, buf, sz); 635 amdgpu_device_flush_hdp(adev, NULL); 636 vfree(buf); 637 drm_dev_exit(idx); 638 } else { 639 vfree(buf); 640 return -ENODEV; 641 } 642 } 643 644 if (ops & PSP_MEM_TRAIN_SAVE) { 645 amdgpu_device_vram_access(psp->adev, ctx->p2c_train_data_offset, ctx->sys_cache, ctx->train_data_size, false); 646 } 647 648 if (ops & PSP_MEM_TRAIN_RESTORE) { 649 amdgpu_device_vram_access(psp->adev, ctx->c2p_train_data_offset, ctx->sys_cache, ctx->train_data_size, true); 650 } 651 652 if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) { 653 ret = psp_v13_0_memory_training_send_msg(psp, (amdgpu_force_long_training > 0) ? 654 PSP_BL__DRAM_LONG_TRAIN : PSP_BL__DRAM_SHORT_TRAIN); 655 if (ret) { 656 dev_err(adev->dev, "send training msg failed.\n"); 657 return ret; 658 } 659 } 660 ctx->training_cnt++; 661 return 0; 662 } 663 664 static int psp_v13_0_load_usbc_pd_fw(struct psp_context *psp, uint64_t fw_pri_mc_addr) 665 { 666 struct amdgpu_device *adev = psp->adev; 667 uint32_t reg_status; 668 int ret, i = 0; 669 670 /* 671 * LFB address which is aligned to 1MB address and has to be 672 * right-shifted by 20 so that LFB address can be passed on a 32-bit C2P 673 * register 674 */ 675 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, (fw_pri_mc_addr >> 20)); 676 677 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 678 0x80000000, 0x80000000, false); 679 if (ret) 680 return ret; 681 682 /* Fireup interrupt so PSP can pick up the address */ 683 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, (GFX_CMD_USB_PD_USE_LFB << 16)); 684 685 /* FW load takes very long time */ 686 do { 687 msleep(1000); 688 reg_status = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35); 689 690 if (reg_status & 0x80000000) 691 goto done; 692 693 } while (++i < USBC_PD_POLLING_LIMIT_S); 694 695 return -ETIME; 696 done: 697 698 if ((reg_status & 0xFFFF) != 0) { 699 DRM_ERROR("Address load failed - MP0_SMN_C2PMSG_35.Bits [15:0] = %04x\n", 700 reg_status & 0xFFFF); 701 return -EIO; 702 } 703 704 return 0; 705 } 706 707 static int psp_v13_0_read_usbc_pd_fw(struct psp_context *psp, uint32_t *fw_ver) 708 { 709 struct amdgpu_device *adev = psp->adev; 710 int ret; 711 712 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, C2PMSG_CMD_GFX_USB_PD_FW_VER); 713 714 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 715 0x80000000, 0x80000000, false); 716 if (!ret) 717 *fw_ver = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36); 718 719 return ret; 720 } 721 722 static int psp_v13_0_exec_spi_cmd(struct psp_context *psp, int cmd) 723 { 724 uint32_t reg_status = 0, reg_val = 0; 725 struct amdgpu_device *adev = psp->adev; 726 int ret; 727 728 /* clear MBX ready (MBOX_READY_MASK bit is 0) and set update command */ 729 reg_val |= (cmd << 16); 730 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115, reg_val); 731 732 /* Ring the doorbell */ 733 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_73, 1); 734 735 if (cmd == C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE || 736 cmd == C2PMSG_CMD_SPI_GET_FLASH_IMAGE) 737 ret = psp_wait_for_spirom_update(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115), 738 MBOX_READY_FLAG, MBOX_READY_MASK, PSP_SPIROM_UPDATE_TIMEOUT); 739 else 740 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115), 741 MBOX_READY_FLAG, MBOX_READY_MASK, false); 742 if (ret) { 743 dev_err(adev->dev, "SPI cmd %x timed out, ret = %d", cmd, ret); 744 return ret; 745 } 746 747 reg_status = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115); 748 if ((reg_status & 0xFFFF) != 0) { 749 dev_err(adev->dev, "SPI cmd %x failed, fail status = %04x\n", 750 cmd, reg_status & 0xFFFF); 751 return -EIO; 752 } 753 754 return 0; 755 } 756 757 static int psp_v13_0_update_spirom(struct psp_context *psp, 758 uint64_t fw_pri_mc_addr) 759 { 760 struct amdgpu_device *adev = psp->adev; 761 int ret; 762 763 /* Confirm PSP is ready to start */ 764 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115), 765 MBOX_READY_FLAG, MBOX_READY_MASK, false); 766 if (ret) { 767 dev_err(adev->dev, "PSP Not ready to start processing, ret = %d", ret); 768 return ret; 769 } 770 771 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, lower_32_bits(fw_pri_mc_addr)); 772 773 ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_LO); 774 if (ret) 775 return ret; 776 777 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, upper_32_bits(fw_pri_mc_addr)); 778 779 ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI); 780 if (ret) 781 return ret; 782 783 psp->vbflash_done = true; 784 785 ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE); 786 if (ret) 787 return ret; 788 789 return 0; 790 } 791 792 static int psp_v13_0_dump_spirom(struct psp_context *psp, 793 uint64_t fw_pri_mc_addr) 794 { 795 struct amdgpu_device *adev = psp->adev; 796 int ret; 797 798 /* Confirm PSP is ready to start */ 799 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115), 800 MBOX_READY_FLAG, MBOX_READY_MASK, false); 801 if (ret) { 802 dev_err(adev->dev, "PSP Not ready to start processing, ret = %d", ret); 803 return ret; 804 } 805 806 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, lower_32_bits(fw_pri_mc_addr)); 807 808 ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_GET_ROM_IMAGE_ADDR_LO); 809 if (ret) 810 return ret; 811 812 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, upper_32_bits(fw_pri_mc_addr)); 813 814 ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_GET_ROM_IMAGE_ADDR_HI); 815 if (ret) 816 return ret; 817 818 ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_GET_FLASH_IMAGE); 819 820 return ret; 821 } 822 823 static int psp_v13_0_vbflash_status(struct psp_context *psp) 824 { 825 struct amdgpu_device *adev = psp->adev; 826 827 return RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115); 828 } 829 830 static int psp_v13_0_fatal_error_recovery_quirk(struct psp_context *psp) 831 { 832 struct amdgpu_device *adev = psp->adev; 833 834 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 10)) { 835 uint32_t reg_data; 836 /* MP1 fatal error: trigger PSP dram read to unhalt PSP 837 * during MP1 triggered sync flood. 838 */ 839 reg_data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67); 840 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67, reg_data + 0x10); 841 842 /* delay 1000ms for the mode1 reset for fatal error 843 * to be recovered back. 844 */ 845 msleep(1000); 846 } 847 848 return 0; 849 } 850 851 static bool psp_v13_0_get_ras_capability(struct psp_context *psp) 852 { 853 struct amdgpu_device *adev = psp->adev; 854 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 855 u32 reg_data; 856 857 /* query ras cap should be done from host side */ 858 if (amdgpu_sriov_vf(adev)) 859 return false; 860 861 if (!con) 862 return false; 863 864 if ((amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) || 865 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 12) || 866 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14)) && 867 (!(adev->flags & AMD_IS_APU))) { 868 reg_data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_127); 869 adev->ras_hw_enabled = (reg_data & GENMASK_ULL(23, 0)); 870 con->poison_supported = ((reg_data & GENMASK_ULL(24, 24)) >> 24) ? true : false; 871 return true; 872 } else { 873 return false; 874 } 875 } 876 877 static bool psp_v13_0_is_aux_sos_load_required(struct psp_context *psp) 878 { 879 struct amdgpu_device *adev = psp->adev; 880 u32 pmfw_ver; 881 882 if (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 6)) 883 return false; 884 885 /* load 4e version of sos if pmfw version less than 85.115.0 */ 886 pmfw_ver = RREG32(regMP1_PUB_SCRATCH0 / 4); 887 888 return (pmfw_ver < 0x557300); 889 } 890 891 static bool psp_v13_0_is_reload_needed(struct psp_context *psp) 892 { 893 uint32_t ucode_ver; 894 895 if (!psp_v13_0_is_sos_alive(psp)) 896 return false; 897 898 /* Restrict reload support only to specific IP versions */ 899 switch (amdgpu_ip_version(psp->adev, MP0_HWIP, 0)) { 900 case IP_VERSION(13, 0, 2): 901 case IP_VERSION(13, 0, 6): 902 case IP_VERSION(13, 0, 14): 903 /* TOS version read from microcode header */ 904 ucode_ver = psp->sos.fw_version; 905 /* Read TOS version from hardware */ 906 psp_v13_0_init_sos_version(psp); 907 return (ucode_ver != psp->sos.fw_version); 908 default: 909 return false; 910 } 911 912 return false; 913 } 914 915 static int psp_v13_0_reg_program_no_ring(struct psp_context *psp, uint32_t val, 916 enum psp_reg_prog_id id) 917 { 918 struct amdgpu_device *adev = psp->adev; 919 int ret = -EOPNOTSUPP; 920 921 /* PSP will broadcast the value to all instances */ 922 if (amdgpu_sriov_vf(adev)) { 923 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_GBR_IH_SET); 924 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, id); 925 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_103, val); 926 927 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101), 928 0x80000000, 0x80000000, false); 929 } 930 931 return ret; 932 } 933 934 static const struct psp_funcs psp_v13_0_funcs = { 935 .init_microcode = psp_v13_0_init_microcode, 936 .wait_for_bootloader = psp_v13_0_wait_for_bootloader_steady_state, 937 .bootloader_load_kdb = psp_v13_0_bootloader_load_kdb, 938 .bootloader_load_spl = psp_v13_0_bootloader_load_spl, 939 .bootloader_load_sysdrv = psp_v13_0_bootloader_load_sysdrv, 940 .bootloader_load_soc_drv = psp_v13_0_bootloader_load_soc_drv, 941 .bootloader_load_intf_drv = psp_v13_0_bootloader_load_intf_drv, 942 .bootloader_load_dbg_drv = psp_v13_0_bootloader_load_dbg_drv, 943 .bootloader_load_ras_drv = psp_v13_0_bootloader_load_ras_drv, 944 .bootloader_load_spdm_drv = psp_v13_0_bootloader_load_spdm_drv, 945 .bootloader_load_sos = psp_v13_0_bootloader_load_sos, 946 .ring_create = psp_v13_0_ring_create, 947 .ring_stop = psp_v13_0_ring_stop, 948 .ring_destroy = psp_v13_0_ring_destroy, 949 .ring_get_wptr = psp_v13_0_ring_get_wptr, 950 .ring_set_wptr = psp_v13_0_ring_set_wptr, 951 .mem_training = psp_v13_0_memory_training, 952 .load_usbc_pd_fw = psp_v13_0_load_usbc_pd_fw, 953 .read_usbc_pd_fw = psp_v13_0_read_usbc_pd_fw, 954 .update_spirom = psp_v13_0_update_spirom, 955 .dump_spirom = psp_v13_0_dump_spirom, 956 .vbflash_stat = psp_v13_0_vbflash_status, 957 .fatal_error_recovery_quirk = psp_v13_0_fatal_error_recovery_quirk, 958 .get_ras_capability = psp_v13_0_get_ras_capability, 959 .is_aux_sos_load_required = psp_v13_0_is_aux_sos_load_required, 960 .is_reload_needed = psp_v13_0_is_reload_needed, 961 .reg_program_no_ring = psp_v13_0_reg_program_no_ring, 962 }; 963 964 void psp_v13_0_set_psp_funcs(struct psp_context *psp) 965 { 966 psp->funcs = &psp_v13_0_funcs; 967 } 968