1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #include <linux/firmware.h> 24 #include <linux/module.h> 25 #include "amdgpu.h" 26 #include "amdgpu_psp.h" 27 #include "amdgpu_ucode.h" 28 #include "soc15_common.h" 29 #include "psp_v12_0.h" 30 31 #include "mp/mp_12_0_0_offset.h" 32 #include "mp/mp_12_0_0_sh_mask.h" 33 #include "gc/gc_9_0_offset.h" 34 #include "sdma0/sdma0_4_0_offset.h" 35 #include "nbio/nbio_7_4_offset.h" 36 37 MODULE_FIRMWARE("amdgpu/renoir_asd.bin"); 38 MODULE_FIRMWARE("amdgpu/renoir_ta.bin"); 39 MODULE_FIRMWARE("amdgpu/green_sardine_asd.bin"); 40 MODULE_FIRMWARE("amdgpu/green_sardine_ta.bin"); 41 42 /* address block */ 43 #define smnMP1_FIRMWARE_FLAGS 0x3010024 44 45 static int psp_v12_0_init_microcode(struct psp_context *psp) 46 { 47 struct amdgpu_device *adev = psp->adev; 48 char ucode_prefix[30]; 49 int err = 0; 50 DRM_DEBUG("\n"); 51 52 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); 53 54 err = psp_init_asd_microcode(psp, ucode_prefix); 55 if (err) 56 return err; 57 58 err = psp_init_ta_microcode(psp, ucode_prefix); 59 if (err) 60 return err; 61 62 /* only supported on renoir */ 63 if (!(adev->apu_flags & AMD_APU_IS_RENOIR)) 64 adev->psp.securedisplay_context.context.bin_desc.size_bytes = 0; 65 66 return 0; 67 } 68 69 static int psp_v12_0_bootloader_load_sysdrv(struct psp_context *psp) 70 { 71 int ret; 72 uint32_t psp_gfxdrv_command_reg = 0; 73 struct amdgpu_device *adev = psp->adev; 74 uint32_t sol_reg; 75 76 /* Check sOS sign of life register to confirm sys driver and sOS 77 * are already been loaded. 78 */ 79 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 80 if (sol_reg) 81 return 0; 82 83 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */ 84 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 85 0x80000000, 0x80000000, 0); 86 if (ret) 87 return ret; 88 89 /* Copy PSP System Driver binary to memory */ 90 ret = psp_copy_fw(psp, psp->sys.start_addr, psp->sys.size_bytes); 91 if (ret) 92 return ret; 93 94 /* Provide the sys driver to bootloader */ 95 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, 96 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 97 psp_gfxdrv_command_reg = 1 << 16; 98 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 99 psp_gfxdrv_command_reg); 100 101 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 102 0x80000000, 0x80000000, 0); 103 104 return ret; 105 } 106 107 static int psp_v12_0_bootloader_load_sos(struct psp_context *psp) 108 { 109 int ret; 110 unsigned int psp_gfxdrv_command_reg = 0; 111 struct amdgpu_device *adev = psp->adev; 112 uint32_t sol_reg; 113 114 /* Check sOS sign of life register to confirm sys driver and sOS 115 * are already been loaded. 116 */ 117 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 118 if (sol_reg) 119 return 0; 120 121 /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */ 122 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 123 0x80000000, 0x80000000, 0); 124 if (ret) 125 return ret; 126 127 /* Copy Secure OS binary to PSP memory */ 128 ret = psp_copy_fw(psp, psp->sos.start_addr, psp->sos.size_bytes); 129 if (ret) 130 return ret; 131 132 /* Provide the PSP secure OS to bootloader */ 133 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, 134 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 135 psp_gfxdrv_command_reg = 2 << 16; 136 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 137 psp_gfxdrv_command_reg); 138 139 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81), 140 RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81), 0, 141 PSP_WAITREG_CHANGED); 142 143 return ret; 144 } 145 146 static int psp_v12_0_ring_create(struct psp_context *psp, 147 enum psp_ring_type ring_type) 148 { 149 int ret = 0; 150 unsigned int psp_ring_reg = 0; 151 struct psp_ring *ring = &psp->km_ring; 152 struct amdgpu_device *adev = psp->adev; 153 154 /* Write low address of the ring to C2PMSG_69 */ 155 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 156 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg); 157 /* Write high address of the ring to C2PMSG_70 */ 158 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 159 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg); 160 /* Write size of ring to C2PMSG_71 */ 161 psp_ring_reg = ring->ring_size; 162 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg); 163 /* Write the ring initialization command to C2PMSG_64 */ 164 psp_ring_reg = ring_type; 165 psp_ring_reg = psp_ring_reg << 16; 166 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg); 167 168 /* Wait for response flag (bit 31) in C2PMSG_64 */ 169 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 170 MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0); 171 172 return ret; 173 } 174 175 static int psp_v12_0_ring_stop(struct psp_context *psp, 176 enum psp_ring_type ring_type) 177 { 178 int ret = 0; 179 struct amdgpu_device *adev = psp->adev; 180 181 /* Write the ring destroy command*/ 182 if (amdgpu_sriov_vf(adev)) 183 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, 184 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING); 185 else 186 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, 187 GFX_CTRL_CMD_ID_DESTROY_RINGS); 188 189 /* Wait for response flag (bit 31) */ 190 if (amdgpu_sriov_vf(adev)) 191 ret = psp_wait_for( 192 psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), 193 MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0); 194 else 195 ret = psp_wait_for( 196 psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 197 MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0); 198 199 return ret; 200 } 201 202 static int psp_v12_0_ring_destroy(struct psp_context *psp, 203 enum psp_ring_type ring_type) 204 { 205 int ret = 0; 206 struct psp_ring *ring = &psp->km_ring; 207 struct amdgpu_device *adev = psp->adev; 208 209 ret = psp_v12_0_ring_stop(psp, ring_type); 210 if (ret) 211 DRM_ERROR("Fail to stop psp ring\n"); 212 213 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 214 &ring->ring_mem_mc_addr, 215 (void **)&ring->ring_mem); 216 217 return ret; 218 } 219 220 static int psp_v12_0_mode1_reset(struct psp_context *psp) 221 { 222 int ret; 223 uint32_t offset; 224 struct amdgpu_device *adev = psp->adev; 225 226 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64); 227 228 ret = psp_wait_for(psp, offset, MBOX_TOS_READY_FLAG, 229 MBOX_TOS_READY_MASK, 0); 230 231 if (ret) { 232 drm_info(adev_to_drm(adev), "psp is not working correctly before mode1 reset!\n"); 233 return -EINVAL; 234 } 235 236 /*send the mode 1 reset command*/ 237 WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST); 238 239 msleep(500); 240 241 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33); 242 243 ret = psp_wait_for(psp, offset, MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 244 0); 245 246 if (ret) { 247 drm_info(adev_to_drm(adev), "psp mode 1 reset failed!\n"); 248 return -EINVAL; 249 } 250 251 drm_info(adev_to_drm(adev), "psp mode1 reset succeed\n"); 252 253 return 0; 254 } 255 256 static uint32_t psp_v12_0_ring_get_wptr(struct psp_context *psp) 257 { 258 uint32_t data; 259 struct amdgpu_device *adev = psp->adev; 260 261 if (amdgpu_sriov_vf(adev)) 262 data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102); 263 else 264 data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67); 265 266 return data; 267 } 268 269 static void psp_v12_0_ring_set_wptr(struct psp_context *psp, uint32_t value) 270 { 271 struct amdgpu_device *adev = psp->adev; 272 273 if (amdgpu_sriov_vf(adev)) { 274 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, value); 275 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD); 276 } else 277 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value); 278 } 279 280 static const struct psp_funcs psp_v12_0_funcs = { 281 .init_microcode = psp_v12_0_init_microcode, 282 .bootloader_load_sysdrv = psp_v12_0_bootloader_load_sysdrv, 283 .bootloader_load_sos = psp_v12_0_bootloader_load_sos, 284 .ring_create = psp_v12_0_ring_create, 285 .ring_stop = psp_v12_0_ring_stop, 286 .ring_destroy = psp_v12_0_ring_destroy, 287 .mode1_reset = psp_v12_0_mode1_reset, 288 .ring_get_wptr = psp_v12_0_ring_get_wptr, 289 .ring_set_wptr = psp_v12_0_ring_set_wptr, 290 }; 291 292 void psp_v12_0_set_psp_funcs(struct psp_context *psp) 293 { 294 psp->funcs = &psp_v12_0_funcs; 295 } 296