1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #include <linux/firmware.h> 24 #include <linux/module.h> 25 #include <linux/vmalloc.h> 26 #include <drm/drm_drv.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_psp.h" 30 #include "amdgpu_ras.h" 31 #include "amdgpu_ucode.h" 32 #include "soc15_common.h" 33 #include "psp_v11_0.h" 34 35 #include "mp/mp_11_0_offset.h" 36 #include "mp/mp_11_0_sh_mask.h" 37 #include "gc/gc_9_0_offset.h" 38 #include "sdma0/sdma0_4_0_offset.h" 39 #include "nbio/nbio_7_4_offset.h" 40 41 #include "oss/osssys_4_0_offset.h" 42 #include "oss/osssys_4_0_sh_mask.h" 43 44 MODULE_FIRMWARE("amdgpu/vega20_sos.bin"); 45 MODULE_FIRMWARE("amdgpu/vega20_asd.bin"); 46 MODULE_FIRMWARE("amdgpu/vega20_ta.bin"); 47 MODULE_FIRMWARE("amdgpu/navi10_sos.bin"); 48 MODULE_FIRMWARE("amdgpu/navi10_asd.bin"); 49 MODULE_FIRMWARE("amdgpu/navi10_ta.bin"); 50 MODULE_FIRMWARE("amdgpu/navi14_sos.bin"); 51 MODULE_FIRMWARE("amdgpu/navi14_asd.bin"); 52 MODULE_FIRMWARE("amdgpu/navi14_ta.bin"); 53 MODULE_FIRMWARE("amdgpu/navi12_sos.bin"); 54 MODULE_FIRMWARE("amdgpu/navi12_asd.bin"); 55 MODULE_FIRMWARE("amdgpu/navi12_ta.bin"); 56 MODULE_FIRMWARE("amdgpu/navi12_cap.bin"); 57 MODULE_FIRMWARE("amdgpu/arcturus_sos.bin"); 58 MODULE_FIRMWARE("amdgpu/arcturus_asd.bin"); 59 MODULE_FIRMWARE("amdgpu/arcturus_ta.bin"); 60 MODULE_FIRMWARE("amdgpu/sienna_cichlid_sos.bin"); 61 MODULE_FIRMWARE("amdgpu/sienna_cichlid_ta.bin"); 62 MODULE_FIRMWARE("amdgpu/sienna_cichlid_cap.bin"); 63 MODULE_FIRMWARE("amdgpu/navy_flounder_sos.bin"); 64 MODULE_FIRMWARE("amdgpu/navy_flounder_ta.bin"); 65 MODULE_FIRMWARE("amdgpu/vangogh_asd.bin"); 66 MODULE_FIRMWARE("amdgpu/vangogh_toc.bin"); 67 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_sos.bin"); 68 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_ta.bin"); 69 MODULE_FIRMWARE("amdgpu/beige_goby_sos.bin"); 70 MODULE_FIRMWARE("amdgpu/beige_goby_ta.bin"); 71 72 /* address block */ 73 #define smnMP1_FIRMWARE_FLAGS 0x3010024 74 /* navi10 reg offset define */ 75 #define mmRLC_GPM_UCODE_ADDR_NV10 0x5b61 76 #define mmRLC_GPM_UCODE_DATA_NV10 0x5b62 77 #define mmSDMA0_UCODE_ADDR_NV10 0x5880 78 #define mmSDMA0_UCODE_DATA_NV10 0x5881 79 /* memory training timeout define */ 80 #define MEM_TRAIN_SEND_MSG_TIMEOUT_US 3000000 81 82 /* For large FW files the time to complete can be very long */ 83 #define USBC_PD_POLLING_LIMIT_S 240 84 85 /* Read USB-PD from LFB */ 86 #define GFX_CMD_USB_PD_USE_LFB 0x480 87 88 static int psp_v11_0_init_microcode(struct psp_context *psp) 89 { 90 struct amdgpu_device *adev = psp->adev; 91 char ucode_prefix[30]; 92 int err = 0; 93 94 DRM_DEBUG("\n"); 95 96 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); 97 98 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 99 case IP_VERSION(11, 0, 2): 100 case IP_VERSION(11, 0, 4): 101 err = psp_init_sos_microcode(psp, ucode_prefix); 102 if (err) 103 return err; 104 err = psp_init_asd_microcode(psp, ucode_prefix); 105 if (err) 106 return err; 107 err = psp_init_ta_microcode(psp, ucode_prefix); 108 adev->psp.securedisplay_context.context.bin_desc.size_bytes = 0; 109 break; 110 case IP_VERSION(11, 0, 0): 111 case IP_VERSION(11, 0, 5): 112 case IP_VERSION(11, 0, 9): 113 err = psp_init_sos_microcode(psp, ucode_prefix); 114 if (err) 115 return err; 116 err = psp_init_asd_microcode(psp, ucode_prefix); 117 if (err) 118 return err; 119 err = psp_init_ta_microcode(psp, ucode_prefix); 120 adev->psp.securedisplay_context.context.bin_desc.size_bytes = 0; 121 break; 122 case IP_VERSION(11, 0, 7): 123 case IP_VERSION(11, 0, 11): 124 case IP_VERSION(11, 0, 12): 125 case IP_VERSION(11, 0, 13): 126 err = psp_init_sos_microcode(psp, ucode_prefix); 127 if (err) 128 return err; 129 err = psp_init_ta_microcode(psp, ucode_prefix); 130 break; 131 case IP_VERSION(11, 5, 0): 132 case IP_VERSION(11, 5, 2): 133 err = psp_init_asd_microcode(psp, ucode_prefix); 134 if (err) 135 return err; 136 err = psp_init_toc_microcode(psp, ucode_prefix); 137 break; 138 default: 139 BUG(); 140 } 141 142 return err; 143 } 144 145 static int psp_v11_wait_for_tos_unload(struct psp_context *psp) 146 { 147 struct amdgpu_device *adev = psp->adev; 148 uint32_t sol_reg1, sol_reg2; 149 int retry_loop; 150 151 /* Wait for the TOS to be unloaded */ 152 for (retry_loop = 0; retry_loop < 20; retry_loop++) { 153 sol_reg1 = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 154 usleep_range(1000, 2000); 155 sol_reg2 = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 156 if (sol_reg1 == sol_reg2) 157 return 0; 158 } 159 dev_err(adev->dev, "TOS unload failed, C2PMSG_33: %x C2PMSG_81: %x", 160 RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_33), 161 RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81)); 162 163 return -ETIME; 164 } 165 166 static int psp_v11_0_wait_for_bootloader(struct psp_context *psp) 167 { 168 struct amdgpu_device *adev = psp->adev; 169 int ret; 170 int retry_loop; 171 172 /* For a reset done at the end of S3, only wait for TOS to be unloaded */ 173 if (adev->in_s3 && !(adev->flags & AMD_IS_APU) && amdgpu_in_reset(adev)) 174 return psp_v11_wait_for_tos_unload(psp); 175 176 for (retry_loop = 0; retry_loop < 20; retry_loop++) { 177 /* Wait for bootloader to signify that is 178 ready having bit 31 of C2PMSG_35 set to 1 */ 179 ret = psp_wait_for( 180 psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 181 0x80000000, 0x8000FFFF, PSP_WAITREG_NOVERBOSE); 182 183 if (ret == 0) 184 return 0; 185 } 186 187 return ret; 188 } 189 190 static bool psp_v11_0_is_sos_alive(struct psp_context *psp) 191 { 192 struct amdgpu_device *adev = psp->adev; 193 uint32_t sol_reg; 194 195 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 196 197 return sol_reg != 0x0; 198 } 199 200 static int psp_v11_0_bootloader_load_component(struct psp_context *psp, 201 struct psp_bin_desc *bin_desc, 202 enum psp_bootloader_cmd bl_cmd) 203 { 204 int ret; 205 uint32_t psp_gfxdrv_command_reg = 0; 206 struct amdgpu_device *adev = psp->adev; 207 208 /* Check sOS sign of life register to confirm sys driver and sOS 209 * are already been loaded. 210 */ 211 if (psp_v11_0_is_sos_alive(psp)) 212 return 0; 213 214 ret = psp_v11_0_wait_for_bootloader(psp); 215 if (ret) 216 return ret; 217 218 /* Copy PSP System Driver binary to memory */ 219 psp_copy_fw(psp, bin_desc->start_addr, bin_desc->size_bytes); 220 221 /* Provide the sys driver to bootloader */ 222 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, 223 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 224 psp_gfxdrv_command_reg = bl_cmd; 225 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 226 psp_gfxdrv_command_reg); 227 228 ret = psp_v11_0_wait_for_bootloader(psp); 229 230 return ret; 231 } 232 233 static int psp_v11_0_bootloader_load_kdb(struct psp_context *psp) 234 { 235 return psp_v11_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_KEY_DATABASE); 236 } 237 238 static int psp_v11_0_bootloader_load_spl(struct psp_context *psp) 239 { 240 return psp_v11_0_bootloader_load_component(psp, &psp->spl, PSP_BL__LOAD_TOS_SPL_TABLE); 241 } 242 243 static int psp_v11_0_bootloader_load_sysdrv(struct psp_context *psp) 244 { 245 return psp_v11_0_bootloader_load_component(psp, &psp->sys, PSP_BL__LOAD_SYSDRV); 246 } 247 248 static int psp_v11_0_bootloader_load_sos(struct psp_context *psp) 249 { 250 int ret; 251 unsigned int psp_gfxdrv_command_reg = 0; 252 struct amdgpu_device *adev = psp->adev; 253 254 /* Check sOS sign of life register to confirm sys driver and sOS 255 * are already been loaded. 256 */ 257 if (psp_v11_0_is_sos_alive(psp)) 258 return 0; 259 260 ret = psp_v11_0_wait_for_bootloader(psp); 261 if (ret) 262 return ret; 263 264 /* Copy Secure OS binary to PSP memory */ 265 psp_copy_fw(psp, psp->sos.start_addr, psp->sos.size_bytes); 266 267 /* Provide the PSP secure OS to bootloader */ 268 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, 269 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 270 psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV; 271 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 272 psp_gfxdrv_command_reg); 273 274 /* there might be handshake issue with hardware which needs delay */ 275 mdelay(20); 276 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81), 277 RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81), 0, 278 PSP_WAITREG_CHANGED); 279 280 return ret; 281 } 282 283 static int psp_v11_0_ring_stop(struct psp_context *psp, 284 enum psp_ring_type ring_type) 285 { 286 int ret = 0; 287 struct amdgpu_device *adev = psp->adev; 288 289 /* Write the ring destroy command*/ 290 if (amdgpu_sriov_vf(adev)) 291 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, 292 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING); 293 else 294 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, 295 GFX_CTRL_CMD_ID_DESTROY_RINGS); 296 297 /* there might be handshake issue with hardware which needs delay */ 298 mdelay(20); 299 300 /* Wait for response flag (bit 31) */ 301 if (amdgpu_sriov_vf(adev)) 302 ret = psp_wait_for( 303 psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), 304 MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0); 305 else 306 ret = psp_wait_for( 307 psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 308 MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0); 309 310 return ret; 311 } 312 313 static int psp_v11_0_ring_create(struct psp_context *psp, 314 enum psp_ring_type ring_type) 315 { 316 int ret = 0; 317 unsigned int psp_ring_reg = 0; 318 struct psp_ring *ring = &psp->km_ring; 319 struct amdgpu_device *adev = psp->adev; 320 321 if (amdgpu_sriov_vf(adev)) { 322 ring->ring_wptr = 0; 323 ret = psp_v11_0_ring_stop(psp, ring_type); 324 if (ret) { 325 DRM_ERROR("psp_v11_0_ring_stop_sriov failed!\n"); 326 return ret; 327 } 328 329 /* Write low address of the ring to C2PMSG_102 */ 330 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 331 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg); 332 /* Write high address of the ring to C2PMSG_103 */ 333 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 334 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg); 335 336 /* Write the ring initialization command to C2PMSG_101 */ 337 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, 338 GFX_CTRL_CMD_ID_INIT_GPCOM_RING); 339 340 /* there might be handshake issue with hardware which needs delay */ 341 mdelay(20); 342 343 /* Wait for response flag (bit 31) in C2PMSG_101 */ 344 ret = psp_wait_for( 345 psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), 346 MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0); 347 348 } else { 349 /* Wait for sOS ready for ring creation */ 350 ret = psp_wait_for( 351 psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 352 MBOX_TOS_READY_FLAG, MBOX_TOS_READY_MASK, 0); 353 if (ret) { 354 DRM_ERROR("Failed to wait for sOS ready for ring creation\n"); 355 return ret; 356 } 357 358 /* Write low address of the ring to C2PMSG_69 */ 359 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 360 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg); 361 /* Write high address of the ring to C2PMSG_70 */ 362 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 363 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg); 364 /* Write size of ring to C2PMSG_71 */ 365 psp_ring_reg = ring->ring_size; 366 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg); 367 /* Write the ring initialization command to C2PMSG_64 */ 368 psp_ring_reg = ring_type; 369 psp_ring_reg = psp_ring_reg << 16; 370 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg); 371 372 /* there might be handshake issue with hardware which needs delay */ 373 mdelay(20); 374 375 /* Wait for response flag (bit 31) in C2PMSG_64 */ 376 ret = psp_wait_for( 377 psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 378 MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0); 379 } 380 381 return ret; 382 } 383 384 385 static int psp_v11_0_ring_destroy(struct psp_context *psp, 386 enum psp_ring_type ring_type) 387 { 388 int ret = 0; 389 struct psp_ring *ring = &psp->km_ring; 390 struct amdgpu_device *adev = psp->adev; 391 392 ret = psp_v11_0_ring_stop(psp, ring_type); 393 if (ret) 394 DRM_ERROR("Fail to stop psp ring\n"); 395 396 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 397 &ring->ring_mem_mc_addr, 398 (void **)&ring->ring_mem); 399 400 return ret; 401 } 402 403 static int psp_v11_0_mode1_reset(struct psp_context *psp) 404 { 405 int ret; 406 uint32_t offset; 407 struct amdgpu_device *adev = psp->adev; 408 409 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64); 410 411 ret = psp_wait_for(psp, offset, MBOX_TOS_READY_FLAG, 412 MBOX_TOS_READY_MASK, 0); 413 414 if (ret) { 415 DRM_INFO("psp is not working correctly before mode1 reset!\n"); 416 return -EINVAL; 417 } 418 419 /*send the mode 1 reset command*/ 420 WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST); 421 422 msleep(500); 423 424 return 0; 425 } 426 427 static int psp_v11_0_memory_training_send_msg(struct psp_context *psp, int msg) 428 { 429 int ret; 430 int i; 431 uint32_t data_32; 432 int max_wait; 433 struct amdgpu_device *adev = psp->adev; 434 435 data_32 = (psp->mem_train_ctx.c2p_train_data_offset >> 20); 436 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, data_32); 437 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, msg); 438 439 max_wait = MEM_TRAIN_SEND_MSG_TIMEOUT_US / adev->usec_timeout; 440 for (i = 0; i < max_wait; i++) { 441 ret = psp_wait_for( 442 psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 443 0x80000000, 0x80000000, PSP_WAITREG_NOVERBOSE); 444 if (ret == 0) 445 break; 446 } 447 if (i < max_wait) 448 ret = 0; 449 else 450 ret = -ETIME; 451 452 DRM_DEBUG("training %s %s, cost %d @ %d ms\n", 453 (msg == PSP_BL__DRAM_SHORT_TRAIN) ? "short" : "long", 454 (ret == 0) ? "succeed" : "failed", 455 i, adev->usec_timeout/1000); 456 return ret; 457 } 458 459 /* 460 * save and restore process 461 */ 462 static int psp_v11_0_memory_training(struct psp_context *psp, uint32_t ops) 463 { 464 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 465 uint32_t *pcache = (uint32_t *)ctx->sys_cache; 466 struct amdgpu_device *adev = psp->adev; 467 uint32_t p2c_header[4]; 468 uint32_t sz; 469 void *buf; 470 int ret, idx; 471 472 if (ctx->init == PSP_MEM_TRAIN_NOT_SUPPORT) { 473 DRM_DEBUG("Memory training is not supported.\n"); 474 return 0; 475 } else if (ctx->init != PSP_MEM_TRAIN_INIT_SUCCESS) { 476 DRM_ERROR("Memory training initialization failure.\n"); 477 return -EINVAL; 478 } 479 480 if (psp_v11_0_is_sos_alive(psp)) { 481 DRM_DEBUG("SOS is alive, skip memory training.\n"); 482 return 0; 483 } 484 485 amdgpu_device_vram_access(adev, ctx->p2c_train_data_offset, p2c_header, sizeof(p2c_header), false); 486 DRM_DEBUG("sys_cache[%08x,%08x,%08x,%08x] p2c_header[%08x,%08x,%08x,%08x]\n", 487 pcache[0], pcache[1], pcache[2], pcache[3], 488 p2c_header[0], p2c_header[1], p2c_header[2], p2c_header[3]); 489 490 if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) { 491 DRM_DEBUG("Short training depends on restore.\n"); 492 ops |= PSP_MEM_TRAIN_RESTORE; 493 } 494 495 if ((ops & PSP_MEM_TRAIN_RESTORE) && 496 pcache[0] != MEM_TRAIN_SYSTEM_SIGNATURE) { 497 DRM_DEBUG("sys_cache[0] is invalid, restore depends on save.\n"); 498 ops |= PSP_MEM_TRAIN_SAVE; 499 } 500 501 if (p2c_header[0] == MEM_TRAIN_SYSTEM_SIGNATURE && 502 !(pcache[0] == MEM_TRAIN_SYSTEM_SIGNATURE && 503 pcache[3] == p2c_header[3])) { 504 DRM_DEBUG("sys_cache is invalid or out-of-date, need save training data to sys_cache.\n"); 505 ops |= PSP_MEM_TRAIN_SAVE; 506 } 507 508 if ((ops & PSP_MEM_TRAIN_SAVE) && 509 p2c_header[0] != MEM_TRAIN_SYSTEM_SIGNATURE) { 510 DRM_DEBUG("p2c_header[0] is invalid, save depends on long training.\n"); 511 ops |= PSP_MEM_TRAIN_SEND_LONG_MSG; 512 } 513 514 if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) { 515 ops &= ~PSP_MEM_TRAIN_SEND_SHORT_MSG; 516 ops |= PSP_MEM_TRAIN_SAVE; 517 } 518 519 DRM_DEBUG("Memory training ops:%x.\n", ops); 520 521 if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) { 522 /* 523 * Long training will encroach a certain amount on the bottom of VRAM; 524 * save the content from the bottom of VRAM to system memory 525 * before training, and restore it after training to avoid 526 * VRAM corruption. 527 */ 528 sz = BIST_MEM_TRAINING_ENCROACHED_SIZE; 529 530 if (adev->gmc.visible_vram_size < sz || !adev->mman.aper_base_kaddr) { 531 DRM_ERROR("visible_vram_size %llx or aper_base_kaddr %p is not initialized.\n", 532 adev->gmc.visible_vram_size, 533 adev->mman.aper_base_kaddr); 534 return -EINVAL; 535 } 536 537 buf = vmalloc(sz); 538 if (!buf) { 539 DRM_ERROR("failed to allocate system memory.\n"); 540 return -ENOMEM; 541 } 542 543 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 544 memcpy_fromio(buf, adev->mman.aper_base_kaddr, sz); 545 ret = psp_v11_0_memory_training_send_msg(psp, PSP_BL__DRAM_LONG_TRAIN); 546 if (ret) { 547 DRM_ERROR("Send long training msg failed.\n"); 548 vfree(buf); 549 drm_dev_exit(idx); 550 return ret; 551 } 552 553 memcpy_toio(adev->mman.aper_base_kaddr, buf, sz); 554 amdgpu_device_flush_hdp(adev, NULL); 555 vfree(buf); 556 drm_dev_exit(idx); 557 } else { 558 vfree(buf); 559 return -ENODEV; 560 } 561 } 562 563 if (ops & PSP_MEM_TRAIN_SAVE) { 564 amdgpu_device_vram_access(psp->adev, ctx->p2c_train_data_offset, ctx->sys_cache, ctx->train_data_size, false); 565 } 566 567 if (ops & PSP_MEM_TRAIN_RESTORE) { 568 amdgpu_device_vram_access(psp->adev, ctx->c2p_train_data_offset, ctx->sys_cache, ctx->train_data_size, true); 569 } 570 571 if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) { 572 ret = psp_v11_0_memory_training_send_msg(psp, (amdgpu_force_long_training > 0) ? 573 PSP_BL__DRAM_LONG_TRAIN : PSP_BL__DRAM_SHORT_TRAIN); 574 if (ret) { 575 DRM_ERROR("send training msg failed.\n"); 576 return ret; 577 } 578 } 579 ctx->training_cnt++; 580 return 0; 581 } 582 583 static uint32_t psp_v11_0_ring_get_wptr(struct psp_context *psp) 584 { 585 uint32_t data; 586 struct amdgpu_device *adev = psp->adev; 587 588 if (amdgpu_sriov_vf(adev)) 589 data = psp->km_ring.ring_wptr; 590 else 591 data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67); 592 593 return data; 594 } 595 596 static void psp_v11_0_ring_set_wptr(struct psp_context *psp, uint32_t value) 597 { 598 struct amdgpu_device *adev = psp->adev; 599 600 if (amdgpu_sriov_vf(adev)) { 601 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, value); 602 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD); 603 psp->km_ring.ring_wptr = value; 604 } else 605 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value); 606 } 607 608 static int psp_v11_0_load_usbc_pd_fw(struct psp_context *psp, uint64_t fw_pri_mc_addr) 609 { 610 struct amdgpu_device *adev = psp->adev; 611 uint32_t reg_status; 612 int ret, i = 0; 613 614 /* 615 * LFB address which is aligned to 1MB address and has to be 616 * right-shifted by 20 so that LFB address can be passed on a 32-bit C2P 617 * register 618 */ 619 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, (fw_pri_mc_addr >> 20)); 620 621 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 622 0x80000000, 0x80000000, 0); 623 if (ret) 624 return ret; 625 626 /* Fireup interrupt so PSP can pick up the address */ 627 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, (GFX_CMD_USB_PD_USE_LFB << 16)); 628 629 /* FW load takes very long time */ 630 do { 631 msleep(1000); 632 reg_status = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35); 633 634 if (reg_status & 0x80000000) 635 goto done; 636 637 } while (++i < USBC_PD_POLLING_LIMIT_S); 638 639 return -ETIME; 640 done: 641 642 if ((reg_status & 0xFFFF) != 0) { 643 DRM_ERROR("Address load failed - MP0_SMN_C2PMSG_35.Bits [15:0] = 0x%04x\n", 644 reg_status & 0xFFFF); 645 return -EIO; 646 } 647 648 return 0; 649 } 650 651 static int psp_v11_0_read_usbc_pd_fw(struct psp_context *psp, uint32_t *fw_ver) 652 { 653 struct amdgpu_device *adev = psp->adev; 654 int ret; 655 656 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, C2PMSG_CMD_GFX_USB_PD_FW_VER); 657 658 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 659 0x80000000, 0x80000000, 0); 660 if (!ret) 661 *fw_ver = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36); 662 663 return ret; 664 } 665 666 static const struct psp_funcs psp_v11_0_funcs = { 667 .init_microcode = psp_v11_0_init_microcode, 668 .bootloader_load_kdb = psp_v11_0_bootloader_load_kdb, 669 .bootloader_load_spl = psp_v11_0_bootloader_load_spl, 670 .bootloader_load_sysdrv = psp_v11_0_bootloader_load_sysdrv, 671 .bootloader_load_sos = psp_v11_0_bootloader_load_sos, 672 .ring_create = psp_v11_0_ring_create, 673 .ring_stop = psp_v11_0_ring_stop, 674 .ring_destroy = psp_v11_0_ring_destroy, 675 .mode1_reset = psp_v11_0_mode1_reset, 676 .mem_training = psp_v11_0_memory_training, 677 .ring_get_wptr = psp_v11_0_ring_get_wptr, 678 .ring_set_wptr = psp_v11_0_ring_set_wptr, 679 .load_usbc_pd_fw = psp_v11_0_load_usbc_pd_fw, 680 .read_usbc_pd_fw = psp_v11_0_read_usbc_pd_fw, 681 .wait_for_bootloader = psp_v11_0_wait_for_bootloader 682 }; 683 684 void psp_v11_0_set_psp_funcs(struct psp_context *psp) 685 { 686 psp->funcs = &psp_v11_0_funcs; 687 } 688