1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #include <linux/firmware.h> 24 #include <linux/module.h> 25 #include <linux/vmalloc.h> 26 #include <drm/drm_drv.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_psp.h" 30 #include "amdgpu_ras.h" 31 #include "amdgpu_ucode.h" 32 #include "soc15_common.h" 33 #include "psp_v11_0.h" 34 35 #include "mp/mp_11_0_offset.h" 36 #include "mp/mp_11_0_sh_mask.h" 37 #include "gc/gc_9_0_offset.h" 38 #include "sdma0/sdma0_4_0_offset.h" 39 #include "nbio/nbio_7_4_offset.h" 40 41 #include "oss/osssys_4_0_offset.h" 42 #include "oss/osssys_4_0_sh_mask.h" 43 44 MODULE_FIRMWARE("amdgpu/vega20_sos.bin"); 45 MODULE_FIRMWARE("amdgpu/vega20_asd.bin"); 46 MODULE_FIRMWARE("amdgpu/vega20_ta.bin"); 47 MODULE_FIRMWARE("amdgpu/navi10_sos.bin"); 48 MODULE_FIRMWARE("amdgpu/navi10_asd.bin"); 49 MODULE_FIRMWARE("amdgpu/navi10_ta.bin"); 50 MODULE_FIRMWARE("amdgpu/navi14_sos.bin"); 51 MODULE_FIRMWARE("amdgpu/navi14_asd.bin"); 52 MODULE_FIRMWARE("amdgpu/navi14_ta.bin"); 53 MODULE_FIRMWARE("amdgpu/navi12_sos.bin"); 54 MODULE_FIRMWARE("amdgpu/navi12_asd.bin"); 55 MODULE_FIRMWARE("amdgpu/navi12_ta.bin"); 56 MODULE_FIRMWARE("amdgpu/arcturus_sos.bin"); 57 MODULE_FIRMWARE("amdgpu/arcturus_asd.bin"); 58 MODULE_FIRMWARE("amdgpu/arcturus_ta.bin"); 59 MODULE_FIRMWARE("amdgpu/sienna_cichlid_sos.bin"); 60 MODULE_FIRMWARE("amdgpu/sienna_cichlid_ta.bin"); 61 MODULE_FIRMWARE("amdgpu/navy_flounder_sos.bin"); 62 MODULE_FIRMWARE("amdgpu/navy_flounder_ta.bin"); 63 MODULE_FIRMWARE("amdgpu/vangogh_asd.bin"); 64 MODULE_FIRMWARE("amdgpu/vangogh_toc.bin"); 65 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_sos.bin"); 66 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_ta.bin"); 67 MODULE_FIRMWARE("amdgpu/beige_goby_sos.bin"); 68 MODULE_FIRMWARE("amdgpu/beige_goby_ta.bin"); 69 70 /* address block */ 71 #define smnMP1_FIRMWARE_FLAGS 0x3010024 72 /* navi10 reg offset define */ 73 #define mmRLC_GPM_UCODE_ADDR_NV10 0x5b61 74 #define mmRLC_GPM_UCODE_DATA_NV10 0x5b62 75 #define mmSDMA0_UCODE_ADDR_NV10 0x5880 76 #define mmSDMA0_UCODE_DATA_NV10 0x5881 77 /* memory training timeout define */ 78 #define MEM_TRAIN_SEND_MSG_TIMEOUT_US 3000000 79 80 /* For large FW files the time to complete can be very long */ 81 #define USBC_PD_POLLING_LIMIT_S 240 82 83 /* Read USB-PD from LFB */ 84 #define GFX_CMD_USB_PD_USE_LFB 0x480 85 86 static int psp_v11_0_init_microcode(struct psp_context *psp) 87 { 88 struct amdgpu_device *adev = psp->adev; 89 const char *chip_name; 90 char fw_name[PSP_FW_NAME_LEN]; 91 int err = 0; 92 const struct ta_firmware_header_v1_0 *ta_hdr; 93 94 DRM_DEBUG("\n"); 95 96 switch (adev->asic_type) { 97 case CHIP_VEGA20: 98 chip_name = "vega20"; 99 break; 100 case CHIP_NAVI10: 101 chip_name = "navi10"; 102 break; 103 case CHIP_NAVI14: 104 chip_name = "navi14"; 105 break; 106 case CHIP_NAVI12: 107 chip_name = "navi12"; 108 break; 109 case CHIP_ARCTURUS: 110 chip_name = "arcturus"; 111 break; 112 case CHIP_SIENNA_CICHLID: 113 chip_name = "sienna_cichlid"; 114 break; 115 case CHIP_NAVY_FLOUNDER: 116 chip_name = "navy_flounder"; 117 break; 118 case CHIP_VANGOGH: 119 chip_name = "vangogh"; 120 break; 121 case CHIP_DIMGREY_CAVEFISH: 122 chip_name = "dimgrey_cavefish"; 123 break; 124 case CHIP_BEIGE_GOBY: 125 chip_name = "beige_goby"; 126 break; 127 default: 128 BUG(); 129 } 130 131 132 switch (adev->asic_type) { 133 case CHIP_VEGA20: 134 case CHIP_ARCTURUS: 135 err = psp_init_sos_microcode(psp, chip_name); 136 if (err) 137 return err; 138 err = psp_init_asd_microcode(psp, chip_name); 139 if (err) 140 return err; 141 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); 142 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev); 143 if (err) { 144 release_firmware(adev->psp.ta_fw); 145 adev->psp.ta_fw = NULL; 146 dev_info(adev->dev, 147 "psp v11.0: Failed to load firmware \"%s\"\n", fw_name); 148 } else { 149 err = amdgpu_ucode_validate(adev->psp.ta_fw); 150 if (err) 151 goto out2; 152 153 ta_hdr = (const struct ta_firmware_header_v1_0 *)adev->psp.ta_fw->data; 154 adev->psp.xgmi_context.context.bin_desc.feature_version = 155 le32_to_cpu(ta_hdr->xgmi.fw_version); 156 adev->psp.xgmi_context.context.bin_desc.size_bytes = 157 le32_to_cpu(ta_hdr->xgmi.size_bytes); 158 adev->psp.xgmi_context.context.bin_desc.start_addr = 159 (uint8_t *)ta_hdr + 160 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 161 adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version); 162 adev->psp.ras_context.context.bin_desc.feature_version = 163 le32_to_cpu(ta_hdr->ras.fw_version); 164 adev->psp.ras_context.context.bin_desc.size_bytes = 165 le32_to_cpu(ta_hdr->ras.size_bytes); 166 adev->psp.ras_context.context.bin_desc.start_addr = 167 (uint8_t *)adev->psp.xgmi_context.context.bin_desc.start_addr + 168 le32_to_cpu(ta_hdr->ras.offset_bytes); 169 } 170 break; 171 case CHIP_NAVI10: 172 case CHIP_NAVI14: 173 case CHIP_NAVI12: 174 err = psp_init_sos_microcode(psp, chip_name); 175 if (err) 176 return err; 177 err = psp_init_asd_microcode(psp, chip_name); 178 if (err) 179 return err; 180 if (amdgpu_sriov_vf(adev)) 181 break; 182 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); 183 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev); 184 if (err) { 185 release_firmware(adev->psp.ta_fw); 186 adev->psp.ta_fw = NULL; 187 dev_info(adev->dev, 188 "psp v11.0: Failed to load firmware \"%s\"\n", fw_name); 189 } else { 190 err = amdgpu_ucode_validate(adev->psp.ta_fw); 191 if (err) 192 goto out2; 193 194 ta_hdr = (const struct ta_firmware_header_v1_0 *)adev->psp.ta_fw->data; 195 adev->psp.hdcp_context.context.bin_desc.feature_version = 196 le32_to_cpu(ta_hdr->hdcp.fw_version); 197 adev->psp.hdcp_context.context.bin_desc.size_bytes = 198 le32_to_cpu(ta_hdr->hdcp.size_bytes); 199 adev->psp.hdcp_context.context.bin_desc.start_addr = 200 (uint8_t *)ta_hdr + 201 le32_to_cpu( 202 ta_hdr->header.ucode_array_offset_bytes); 203 204 adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version); 205 206 adev->psp.dtm_context.context.bin_desc.feature_version = 207 le32_to_cpu(ta_hdr->dtm.fw_version); 208 adev->psp.dtm_context.context.bin_desc.size_bytes = 209 le32_to_cpu(ta_hdr->dtm.size_bytes); 210 adev->psp.dtm_context.context.bin_desc.start_addr = 211 (uint8_t *)adev->psp.hdcp_context.context 212 .bin_desc.start_addr + 213 le32_to_cpu(ta_hdr->dtm.offset_bytes); 214 } 215 break; 216 case CHIP_SIENNA_CICHLID: 217 case CHIP_NAVY_FLOUNDER: 218 case CHIP_DIMGREY_CAVEFISH: 219 err = psp_init_sos_microcode(psp, chip_name); 220 if (err) 221 return err; 222 err = psp_init_ta_microcode(psp, chip_name); 223 if (err) 224 return err; 225 break; 226 case CHIP_BEIGE_GOBY: 227 err = psp_init_sos_microcode(psp, chip_name); 228 if (err) 229 return err; 230 err = psp_init_ta_microcode(psp, chip_name); 231 if (err) 232 return err; 233 break; 234 case CHIP_VANGOGH: 235 err = psp_init_asd_microcode(psp, chip_name); 236 if (err) 237 return err; 238 err = psp_init_toc_microcode(psp, chip_name); 239 if (err) 240 return err; 241 break; 242 default: 243 BUG(); 244 } 245 246 return 0; 247 248 out2: 249 release_firmware(adev->psp.ta_fw); 250 adev->psp.ta_fw = NULL; 251 return err; 252 } 253 254 static int psp_v11_0_wait_for_bootloader(struct psp_context *psp) 255 { 256 struct amdgpu_device *adev = psp->adev; 257 258 int ret; 259 int retry_loop; 260 261 for (retry_loop = 0; retry_loop < 10; retry_loop++) { 262 /* Wait for bootloader to signify that is 263 ready having bit 31 of C2PMSG_35 set to 1 */ 264 ret = psp_wait_for(psp, 265 SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 266 0x80000000, 267 0x80000000, 268 false); 269 270 if (ret == 0) 271 return 0; 272 } 273 274 return ret; 275 } 276 277 static bool psp_v11_0_is_sos_alive(struct psp_context *psp) 278 { 279 struct amdgpu_device *adev = psp->adev; 280 uint32_t sol_reg; 281 282 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 283 284 return sol_reg != 0x0; 285 } 286 287 static int psp_v11_0_bootloader_load_kdb(struct psp_context *psp) 288 { 289 int ret; 290 uint32_t psp_gfxdrv_command_reg = 0; 291 struct amdgpu_device *adev = psp->adev; 292 293 /* Check tOS sign of life register to confirm sys driver and sOS 294 * are already been loaded. 295 */ 296 if (psp_v11_0_is_sos_alive(psp)) 297 return 0; 298 299 ret = psp_v11_0_wait_for_bootloader(psp); 300 if (ret) 301 return ret; 302 303 /* Copy PSP KDB binary to memory */ 304 psp_copy_fw(psp, psp->kdb.start_addr, psp->kdb.size_bytes); 305 306 /* Provide the PSP KDB to bootloader */ 307 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, 308 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 309 psp_gfxdrv_command_reg = PSP_BL__LOAD_KEY_DATABASE; 310 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 311 psp_gfxdrv_command_reg); 312 313 ret = psp_v11_0_wait_for_bootloader(psp); 314 315 return ret; 316 } 317 318 static int psp_v11_0_bootloader_load_spl(struct psp_context *psp) 319 { 320 int ret; 321 uint32_t psp_gfxdrv_command_reg = 0; 322 struct amdgpu_device *adev = psp->adev; 323 324 /* Check tOS sign of life register to confirm sys driver and sOS 325 * are already been loaded. 326 */ 327 if (psp_v11_0_is_sos_alive(psp)) 328 return 0; 329 330 ret = psp_v11_0_wait_for_bootloader(psp); 331 if (ret) 332 return ret; 333 334 /* Copy PSP SPL binary to memory */ 335 psp_copy_fw(psp, psp->spl.start_addr, psp->spl.size_bytes); 336 337 /* Provide the PSP SPL to bootloader */ 338 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, 339 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 340 psp_gfxdrv_command_reg = PSP_BL__LOAD_TOS_SPL_TABLE; 341 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 342 psp_gfxdrv_command_reg); 343 344 ret = psp_v11_0_wait_for_bootloader(psp); 345 346 return ret; 347 } 348 349 static int psp_v11_0_bootloader_load_sysdrv(struct psp_context *psp) 350 { 351 int ret; 352 uint32_t psp_gfxdrv_command_reg = 0; 353 struct amdgpu_device *adev = psp->adev; 354 355 /* Check sOS sign of life register to confirm sys driver and sOS 356 * are already been loaded. 357 */ 358 if (psp_v11_0_is_sos_alive(psp)) 359 return 0; 360 361 ret = psp_v11_0_wait_for_bootloader(psp); 362 if (ret) 363 return ret; 364 365 /* Copy PSP System Driver binary to memory */ 366 psp_copy_fw(psp, psp->sys.start_addr, psp->sys.size_bytes); 367 368 /* Provide the sys driver to bootloader */ 369 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, 370 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 371 psp_gfxdrv_command_reg = PSP_BL__LOAD_SYSDRV; 372 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 373 psp_gfxdrv_command_reg); 374 375 /* there might be handshake issue with hardware which needs delay */ 376 mdelay(20); 377 378 ret = psp_v11_0_wait_for_bootloader(psp); 379 380 return ret; 381 } 382 383 static int psp_v11_0_bootloader_load_sos(struct psp_context *psp) 384 { 385 int ret; 386 unsigned int psp_gfxdrv_command_reg = 0; 387 struct amdgpu_device *adev = psp->adev; 388 389 /* Check sOS sign of life register to confirm sys driver and sOS 390 * are already been loaded. 391 */ 392 if (psp_v11_0_is_sos_alive(psp)) 393 return 0; 394 395 ret = psp_v11_0_wait_for_bootloader(psp); 396 if (ret) 397 return ret; 398 399 /* Copy Secure OS binary to PSP memory */ 400 psp_copy_fw(psp, psp->sos.start_addr, psp->sos.size_bytes); 401 402 /* Provide the PSP secure OS to bootloader */ 403 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, 404 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 405 psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV; 406 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 407 psp_gfxdrv_command_reg); 408 409 /* there might be handshake issue with hardware which needs delay */ 410 mdelay(20); 411 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81), 412 RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81), 413 0, true); 414 415 return ret; 416 } 417 418 static int psp_v11_0_ring_init(struct psp_context *psp, 419 enum psp_ring_type ring_type) 420 { 421 int ret = 0; 422 struct psp_ring *ring; 423 struct amdgpu_device *adev = psp->adev; 424 425 ring = &psp->km_ring; 426 427 ring->ring_type = ring_type; 428 429 /* allocate 4k Page of Local Frame Buffer memory for ring */ 430 ring->ring_size = 0x1000; 431 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE, 432 AMDGPU_GEM_DOMAIN_VRAM, 433 &adev->firmware.rbuf, 434 &ring->ring_mem_mc_addr, 435 (void **)&ring->ring_mem); 436 if (ret) { 437 ring->ring_size = 0; 438 return ret; 439 } 440 441 return 0; 442 } 443 444 static int psp_v11_0_ring_stop(struct psp_context *psp, 445 enum psp_ring_type ring_type) 446 { 447 int ret = 0; 448 struct amdgpu_device *adev = psp->adev; 449 450 /* Write the ring destroy command*/ 451 if (amdgpu_sriov_vf(adev)) 452 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, 453 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING); 454 else 455 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, 456 GFX_CTRL_CMD_ID_DESTROY_RINGS); 457 458 /* there might be handshake issue with hardware which needs delay */ 459 mdelay(20); 460 461 /* Wait for response flag (bit 31) */ 462 if (amdgpu_sriov_vf(adev)) 463 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), 464 0x80000000, 0x80000000, false); 465 else 466 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 467 0x80000000, 0x80000000, false); 468 469 return ret; 470 } 471 472 static int psp_v11_0_ring_create(struct psp_context *psp, 473 enum psp_ring_type ring_type) 474 { 475 int ret = 0; 476 unsigned int psp_ring_reg = 0; 477 struct psp_ring *ring = &psp->km_ring; 478 struct amdgpu_device *adev = psp->adev; 479 480 if (amdgpu_sriov_vf(adev)) { 481 ring->ring_wptr = 0; 482 ret = psp_v11_0_ring_stop(psp, ring_type); 483 if (ret) { 484 DRM_ERROR("psp_v11_0_ring_stop_sriov failed!\n"); 485 return ret; 486 } 487 488 /* Write low address of the ring to C2PMSG_102 */ 489 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 490 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg); 491 /* Write high address of the ring to C2PMSG_103 */ 492 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 493 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg); 494 495 /* Write the ring initialization command to C2PMSG_101 */ 496 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, 497 GFX_CTRL_CMD_ID_INIT_GPCOM_RING); 498 499 /* there might be handshake issue with hardware which needs delay */ 500 mdelay(20); 501 502 /* Wait for response flag (bit 31) in C2PMSG_101 */ 503 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), 504 0x80000000, 0x8000FFFF, false); 505 506 } else { 507 /* Wait for sOS ready for ring creation */ 508 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 509 0x80000000, 0x80000000, false); 510 if (ret) { 511 DRM_ERROR("Failed to wait for sOS ready for ring creation\n"); 512 return ret; 513 } 514 515 /* Write low address of the ring to C2PMSG_69 */ 516 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 517 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg); 518 /* Write high address of the ring to C2PMSG_70 */ 519 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 520 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg); 521 /* Write size of ring to C2PMSG_71 */ 522 psp_ring_reg = ring->ring_size; 523 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg); 524 /* Write the ring initialization command to C2PMSG_64 */ 525 psp_ring_reg = ring_type; 526 psp_ring_reg = psp_ring_reg << 16; 527 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg); 528 529 /* there might be handshake issue with hardware which needs delay */ 530 mdelay(20); 531 532 /* Wait for response flag (bit 31) in C2PMSG_64 */ 533 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 534 0x80000000, 0x8000FFFF, false); 535 } 536 537 return ret; 538 } 539 540 541 static int psp_v11_0_ring_destroy(struct psp_context *psp, 542 enum psp_ring_type ring_type) 543 { 544 int ret = 0; 545 struct psp_ring *ring = &psp->km_ring; 546 struct amdgpu_device *adev = psp->adev; 547 548 ret = psp_v11_0_ring_stop(psp, ring_type); 549 if (ret) 550 DRM_ERROR("Fail to stop psp ring\n"); 551 552 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 553 &ring->ring_mem_mc_addr, 554 (void **)&ring->ring_mem); 555 556 return ret; 557 } 558 559 static int psp_v11_0_mode1_reset(struct psp_context *psp) 560 { 561 int ret; 562 uint32_t offset; 563 struct amdgpu_device *adev = psp->adev; 564 565 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64); 566 567 ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false); 568 569 if (ret) { 570 DRM_INFO("psp is not working correctly before mode1 reset!\n"); 571 return -EINVAL; 572 } 573 574 /*send the mode 1 reset command*/ 575 WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST); 576 577 msleep(500); 578 579 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33); 580 581 ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false); 582 583 if (ret) { 584 DRM_INFO("psp mode 1 reset failed!\n"); 585 return -EINVAL; 586 } 587 588 DRM_INFO("psp mode1 reset succeed \n"); 589 590 return 0; 591 } 592 593 static int psp_v11_0_memory_training_send_msg(struct psp_context *psp, int msg) 594 { 595 int ret; 596 int i; 597 uint32_t data_32; 598 int max_wait; 599 struct amdgpu_device *adev = psp->adev; 600 601 data_32 = (psp->mem_train_ctx.c2p_train_data_offset >> 20); 602 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, data_32); 603 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, msg); 604 605 max_wait = MEM_TRAIN_SEND_MSG_TIMEOUT_US / adev->usec_timeout; 606 for (i = 0; i < max_wait; i++) { 607 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 608 0x80000000, 0x80000000, false); 609 if (ret == 0) 610 break; 611 } 612 if (i < max_wait) 613 ret = 0; 614 else 615 ret = -ETIME; 616 617 DRM_DEBUG("training %s %s, cost %d @ %d ms\n", 618 (msg == PSP_BL__DRAM_SHORT_TRAIN) ? "short" : "long", 619 (ret == 0) ? "succeed" : "failed", 620 i, adev->usec_timeout/1000); 621 return ret; 622 } 623 624 /* 625 * save and restore process 626 */ 627 static int psp_v11_0_memory_training(struct psp_context *psp, uint32_t ops) 628 { 629 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 630 uint32_t *pcache = (uint32_t *)ctx->sys_cache; 631 struct amdgpu_device *adev = psp->adev; 632 uint32_t p2c_header[4]; 633 uint32_t sz; 634 void *buf; 635 int ret, idx; 636 637 if (ctx->init == PSP_MEM_TRAIN_NOT_SUPPORT) { 638 DRM_DEBUG("Memory training is not supported.\n"); 639 return 0; 640 } else if (ctx->init != PSP_MEM_TRAIN_INIT_SUCCESS) { 641 DRM_ERROR("Memory training initialization failure.\n"); 642 return -EINVAL; 643 } 644 645 if (psp_v11_0_is_sos_alive(psp)) { 646 DRM_DEBUG("SOS is alive, skip memory training.\n"); 647 return 0; 648 } 649 650 amdgpu_device_vram_access(adev, ctx->p2c_train_data_offset, p2c_header, sizeof(p2c_header), false); 651 DRM_DEBUG("sys_cache[%08x,%08x,%08x,%08x] p2c_header[%08x,%08x,%08x,%08x]\n", 652 pcache[0], pcache[1], pcache[2], pcache[3], 653 p2c_header[0], p2c_header[1], p2c_header[2], p2c_header[3]); 654 655 if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) { 656 DRM_DEBUG("Short training depends on restore.\n"); 657 ops |= PSP_MEM_TRAIN_RESTORE; 658 } 659 660 if ((ops & PSP_MEM_TRAIN_RESTORE) && 661 pcache[0] != MEM_TRAIN_SYSTEM_SIGNATURE) { 662 DRM_DEBUG("sys_cache[0] is invalid, restore depends on save.\n"); 663 ops |= PSP_MEM_TRAIN_SAVE; 664 } 665 666 if (p2c_header[0] == MEM_TRAIN_SYSTEM_SIGNATURE && 667 !(pcache[0] == MEM_TRAIN_SYSTEM_SIGNATURE && 668 pcache[3] == p2c_header[3])) { 669 DRM_DEBUG("sys_cache is invalid or out-of-date, need save training data to sys_cache.\n"); 670 ops |= PSP_MEM_TRAIN_SAVE; 671 } 672 673 if ((ops & PSP_MEM_TRAIN_SAVE) && 674 p2c_header[0] != MEM_TRAIN_SYSTEM_SIGNATURE) { 675 DRM_DEBUG("p2c_header[0] is invalid, save depends on long training.\n"); 676 ops |= PSP_MEM_TRAIN_SEND_LONG_MSG; 677 } 678 679 if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) { 680 ops &= ~PSP_MEM_TRAIN_SEND_SHORT_MSG; 681 ops |= PSP_MEM_TRAIN_SAVE; 682 } 683 684 DRM_DEBUG("Memory training ops:%x.\n", ops); 685 686 if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) { 687 /* 688 * Long training will encroach a certain amount on the bottom of VRAM; 689 * save the content from the bottom of VRAM to system memory 690 * before training, and restore it after training to avoid 691 * VRAM corruption. 692 */ 693 sz = GDDR6_MEM_TRAINING_ENCROACHED_SIZE; 694 695 if (adev->gmc.visible_vram_size < sz || !adev->mman.aper_base_kaddr) { 696 DRM_ERROR("visible_vram_size %llx or aper_base_kaddr %p is not initialized.\n", 697 adev->gmc.visible_vram_size, 698 adev->mman.aper_base_kaddr); 699 return -EINVAL; 700 } 701 702 buf = vmalloc(sz); 703 if (!buf) { 704 DRM_ERROR("failed to allocate system memory.\n"); 705 return -ENOMEM; 706 } 707 708 if (drm_dev_enter(&adev->ddev, &idx)) { 709 memcpy_fromio(buf, adev->mman.aper_base_kaddr, sz); 710 ret = psp_v11_0_memory_training_send_msg(psp, PSP_BL__DRAM_LONG_TRAIN); 711 if (ret) { 712 DRM_ERROR("Send long training msg failed.\n"); 713 vfree(buf); 714 drm_dev_exit(idx); 715 return ret; 716 } 717 718 memcpy_toio(adev->mman.aper_base_kaddr, buf, sz); 719 adev->hdp.funcs->flush_hdp(adev, NULL); 720 vfree(buf); 721 drm_dev_exit(idx); 722 } else { 723 vfree(buf); 724 return -ENODEV; 725 } 726 } 727 728 if (ops & PSP_MEM_TRAIN_SAVE) { 729 amdgpu_device_vram_access(psp->adev, ctx->p2c_train_data_offset, ctx->sys_cache, ctx->train_data_size, false); 730 } 731 732 if (ops & PSP_MEM_TRAIN_RESTORE) { 733 amdgpu_device_vram_access(psp->adev, ctx->c2p_train_data_offset, ctx->sys_cache, ctx->train_data_size, true); 734 } 735 736 if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) { 737 ret = psp_v11_0_memory_training_send_msg(psp, (amdgpu_force_long_training > 0) ? 738 PSP_BL__DRAM_LONG_TRAIN : PSP_BL__DRAM_SHORT_TRAIN); 739 if (ret) { 740 DRM_ERROR("send training msg failed.\n"); 741 return ret; 742 } 743 } 744 ctx->training_cnt++; 745 return 0; 746 } 747 748 static uint32_t psp_v11_0_ring_get_wptr(struct psp_context *psp) 749 { 750 uint32_t data; 751 struct amdgpu_device *adev = psp->adev; 752 753 if (amdgpu_sriov_vf(adev)) 754 data = psp->km_ring.ring_wptr; 755 else 756 data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67); 757 758 return data; 759 } 760 761 static void psp_v11_0_ring_set_wptr(struct psp_context *psp, uint32_t value) 762 { 763 struct amdgpu_device *adev = psp->adev; 764 765 if (amdgpu_sriov_vf(adev)) { 766 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, value); 767 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD); 768 psp->km_ring.ring_wptr = value; 769 } else 770 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value); 771 } 772 773 static int psp_v11_0_load_usbc_pd_fw(struct psp_context *psp, uint64_t fw_pri_mc_addr) 774 { 775 struct amdgpu_device *adev = psp->adev; 776 uint32_t reg_status; 777 int ret, i = 0; 778 779 /* 780 * LFB address which is aligned to 1MB address and has to be 781 * right-shifted by 20 so that LFB address can be passed on a 32-bit C2P 782 * register 783 */ 784 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, (fw_pri_mc_addr >> 20)); 785 786 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 787 0x80000000, 0x80000000, false); 788 if (ret) 789 return ret; 790 791 /* Fireup interrupt so PSP can pick up the address */ 792 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, (GFX_CMD_USB_PD_USE_LFB << 16)); 793 794 /* FW load takes very long time */ 795 do { 796 msleep(1000); 797 reg_status = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35); 798 799 if (reg_status & 0x80000000) 800 goto done; 801 802 } while (++i < USBC_PD_POLLING_LIMIT_S); 803 804 return -ETIME; 805 done: 806 807 if ((reg_status & 0xFFFF) != 0) { 808 DRM_ERROR("Address load failed - MP0_SMN_C2PMSG_35.Bits [15:0] = 0x%04x\n", 809 reg_status & 0xFFFF); 810 return -EIO; 811 } 812 813 return 0; 814 } 815 816 static int psp_v11_0_read_usbc_pd_fw(struct psp_context *psp, uint32_t *fw_ver) 817 { 818 struct amdgpu_device *adev = psp->adev; 819 int ret; 820 821 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, C2PMSG_CMD_GFX_USB_PD_FW_VER); 822 823 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 824 0x80000000, 0x80000000, false); 825 if (!ret) 826 *fw_ver = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36); 827 828 return ret; 829 } 830 831 static const struct psp_funcs psp_v11_0_funcs = { 832 .init_microcode = psp_v11_0_init_microcode, 833 .bootloader_load_kdb = psp_v11_0_bootloader_load_kdb, 834 .bootloader_load_spl = psp_v11_0_bootloader_load_spl, 835 .bootloader_load_sysdrv = psp_v11_0_bootloader_load_sysdrv, 836 .bootloader_load_sos = psp_v11_0_bootloader_load_sos, 837 .ring_init = psp_v11_0_ring_init, 838 .ring_create = psp_v11_0_ring_create, 839 .ring_stop = psp_v11_0_ring_stop, 840 .ring_destroy = psp_v11_0_ring_destroy, 841 .mode1_reset = psp_v11_0_mode1_reset, 842 .mem_training = psp_v11_0_memory_training, 843 .ring_get_wptr = psp_v11_0_ring_get_wptr, 844 .ring_set_wptr = psp_v11_0_ring_set_wptr, 845 .load_usbc_pd_fw = psp_v11_0_load_usbc_pd_fw, 846 .read_usbc_pd_fw = psp_v11_0_read_usbc_pd_fw 847 }; 848 849 void psp_v11_0_set_psp_funcs(struct psp_context *psp) 850 { 851 psp->funcs = &psp_v11_0_funcs; 852 } 853