1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #include <linux/firmware.h> 24 #include <linux/module.h> 25 #include <linux/vmalloc.h> 26 #include <drm/drm_drv.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_psp.h" 30 #include "amdgpu_ras.h" 31 #include "amdgpu_ucode.h" 32 #include "soc15_common.h" 33 #include "psp_v11_0.h" 34 35 #include "mp/mp_11_0_offset.h" 36 #include "mp/mp_11_0_sh_mask.h" 37 #include "gc/gc_9_0_offset.h" 38 #include "sdma0/sdma0_4_0_offset.h" 39 #include "nbio/nbio_7_4_offset.h" 40 41 #include "oss/osssys_4_0_offset.h" 42 #include "oss/osssys_4_0_sh_mask.h" 43 44 MODULE_FIRMWARE("amdgpu/vega20_sos.bin"); 45 MODULE_FIRMWARE("amdgpu/vega20_asd.bin"); 46 MODULE_FIRMWARE("amdgpu/vega20_ta.bin"); 47 MODULE_FIRMWARE("amdgpu/navi10_sos.bin"); 48 MODULE_FIRMWARE("amdgpu/navi10_asd.bin"); 49 MODULE_FIRMWARE("amdgpu/navi10_ta.bin"); 50 MODULE_FIRMWARE("amdgpu/navi14_sos.bin"); 51 MODULE_FIRMWARE("amdgpu/navi14_asd.bin"); 52 MODULE_FIRMWARE("amdgpu/navi14_ta.bin"); 53 MODULE_FIRMWARE("amdgpu/navi12_sos.bin"); 54 MODULE_FIRMWARE("amdgpu/navi12_asd.bin"); 55 MODULE_FIRMWARE("amdgpu/navi12_ta.bin"); 56 MODULE_FIRMWARE("amdgpu/navi12_cap.bin"); 57 MODULE_FIRMWARE("amdgpu/arcturus_sos.bin"); 58 MODULE_FIRMWARE("amdgpu/arcturus_asd.bin"); 59 MODULE_FIRMWARE("amdgpu/arcturus_ta.bin"); 60 MODULE_FIRMWARE("amdgpu/sienna_cichlid_sos.bin"); 61 MODULE_FIRMWARE("amdgpu/sienna_cichlid_ta.bin"); 62 MODULE_FIRMWARE("amdgpu/sienna_cichlid_cap.bin"); 63 MODULE_FIRMWARE("amdgpu/navy_flounder_sos.bin"); 64 MODULE_FIRMWARE("amdgpu/navy_flounder_ta.bin"); 65 MODULE_FIRMWARE("amdgpu/vangogh_asd.bin"); 66 MODULE_FIRMWARE("amdgpu/vangogh_toc.bin"); 67 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_sos.bin"); 68 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_ta.bin"); 69 MODULE_FIRMWARE("amdgpu/beige_goby_sos.bin"); 70 MODULE_FIRMWARE("amdgpu/beige_goby_ta.bin"); 71 72 /* address block */ 73 #define smnMP1_FIRMWARE_FLAGS 0x3010024 74 /* navi10 reg offset define */ 75 #define mmRLC_GPM_UCODE_ADDR_NV10 0x5b61 76 #define mmRLC_GPM_UCODE_DATA_NV10 0x5b62 77 #define mmSDMA0_UCODE_ADDR_NV10 0x5880 78 #define mmSDMA0_UCODE_DATA_NV10 0x5881 79 /* memory training timeout define */ 80 #define MEM_TRAIN_SEND_MSG_TIMEOUT_US 3000000 81 82 /* For large FW files the time to complete can be very long */ 83 #define USBC_PD_POLLING_LIMIT_S 240 84 85 /* Read USB-PD from LFB */ 86 #define GFX_CMD_USB_PD_USE_LFB 0x480 87 88 static int psp_v11_0_init_microcode(struct psp_context *psp) 89 { 90 struct amdgpu_device *adev = psp->adev; 91 char ucode_prefix[30]; 92 int err = 0; 93 94 DRM_DEBUG("\n"); 95 96 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); 97 98 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 99 case IP_VERSION(11, 0, 2): 100 case IP_VERSION(11, 0, 4): 101 err = psp_init_sos_microcode(psp, ucode_prefix); 102 if (err) 103 return err; 104 err = psp_init_asd_microcode(psp, ucode_prefix); 105 if (err) 106 return err; 107 err = psp_init_ta_microcode(psp, ucode_prefix); 108 adev->psp.securedisplay_context.context.bin_desc.size_bytes = 0; 109 break; 110 case IP_VERSION(11, 0, 0): 111 case IP_VERSION(11, 0, 5): 112 case IP_VERSION(11, 0, 9): 113 err = psp_init_sos_microcode(psp, ucode_prefix); 114 if (err) 115 return err; 116 err = psp_init_asd_microcode(psp, ucode_prefix); 117 if (err) 118 return err; 119 err = psp_init_ta_microcode(psp, ucode_prefix); 120 adev->psp.securedisplay_context.context.bin_desc.size_bytes = 0; 121 break; 122 case IP_VERSION(11, 0, 7): 123 case IP_VERSION(11, 0, 11): 124 case IP_VERSION(11, 0, 12): 125 case IP_VERSION(11, 0, 13): 126 err = psp_init_sos_microcode(psp, ucode_prefix); 127 if (err) 128 return err; 129 err = psp_init_ta_microcode(psp, ucode_prefix); 130 break; 131 case IP_VERSION(11, 5, 0): 132 case IP_VERSION(11, 5, 2): 133 err = psp_init_asd_microcode(psp, ucode_prefix); 134 if (err) 135 return err; 136 err = psp_init_toc_microcode(psp, ucode_prefix); 137 break; 138 default: 139 BUG(); 140 } 141 142 return err; 143 } 144 145 static int psp_v11_0_wait_for_bootloader(struct psp_context *psp) 146 { 147 struct amdgpu_device *adev = psp->adev; 148 149 int ret; 150 int retry_loop; 151 152 for (retry_loop = 0; retry_loop < 10; retry_loop++) { 153 /* Wait for bootloader to signify that is 154 ready having bit 31 of C2PMSG_35 set to 1 */ 155 ret = psp_wait_for(psp, 156 SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 157 0x80000000, 158 0x80000000, 159 false); 160 161 if (ret == 0) 162 return 0; 163 } 164 165 return ret; 166 } 167 168 static bool psp_v11_0_is_sos_alive(struct psp_context *psp) 169 { 170 struct amdgpu_device *adev = psp->adev; 171 uint32_t sol_reg; 172 173 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 174 175 return sol_reg != 0x0; 176 } 177 178 static int psp_v11_0_bootloader_load_component(struct psp_context *psp, 179 struct psp_bin_desc *bin_desc, 180 enum psp_bootloader_cmd bl_cmd) 181 { 182 int ret; 183 uint32_t psp_gfxdrv_command_reg = 0; 184 struct amdgpu_device *adev = psp->adev; 185 186 /* Check sOS sign of life register to confirm sys driver and sOS 187 * are already been loaded. 188 */ 189 if (psp_v11_0_is_sos_alive(psp)) 190 return 0; 191 192 ret = psp_v11_0_wait_for_bootloader(psp); 193 if (ret) 194 return ret; 195 196 /* Copy PSP System Driver binary to memory */ 197 psp_copy_fw(psp, bin_desc->start_addr, bin_desc->size_bytes); 198 199 /* Provide the sys driver to bootloader */ 200 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, 201 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 202 psp_gfxdrv_command_reg = bl_cmd; 203 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 204 psp_gfxdrv_command_reg); 205 206 ret = psp_v11_0_wait_for_bootloader(psp); 207 208 return ret; 209 } 210 211 static int psp_v11_0_bootloader_load_kdb(struct psp_context *psp) 212 { 213 return psp_v11_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_KEY_DATABASE); 214 } 215 216 static int psp_v11_0_bootloader_load_spl(struct psp_context *psp) 217 { 218 return psp_v11_0_bootloader_load_component(psp, &psp->spl, PSP_BL__LOAD_TOS_SPL_TABLE); 219 } 220 221 static int psp_v11_0_bootloader_load_sysdrv(struct psp_context *psp) 222 { 223 return psp_v11_0_bootloader_load_component(psp, &psp->sys, PSP_BL__LOAD_SYSDRV); 224 } 225 226 static int psp_v11_0_bootloader_load_sos(struct psp_context *psp) 227 { 228 int ret; 229 unsigned int psp_gfxdrv_command_reg = 0; 230 struct amdgpu_device *adev = psp->adev; 231 232 /* Check sOS sign of life register to confirm sys driver and sOS 233 * are already been loaded. 234 */ 235 if (psp_v11_0_is_sos_alive(psp)) 236 return 0; 237 238 ret = psp_v11_0_wait_for_bootloader(psp); 239 if (ret) 240 return ret; 241 242 /* Copy Secure OS binary to PSP memory */ 243 psp_copy_fw(psp, psp->sos.start_addr, psp->sos.size_bytes); 244 245 /* Provide the PSP secure OS to bootloader */ 246 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, 247 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 248 psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV; 249 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 250 psp_gfxdrv_command_reg); 251 252 /* there might be handshake issue with hardware which needs delay */ 253 mdelay(20); 254 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81), 255 RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81), 256 0, true); 257 258 return ret; 259 } 260 261 static int psp_v11_0_ring_stop(struct psp_context *psp, 262 enum psp_ring_type ring_type) 263 { 264 int ret = 0; 265 struct amdgpu_device *adev = psp->adev; 266 267 /* Write the ring destroy command*/ 268 if (amdgpu_sriov_vf(adev)) 269 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, 270 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING); 271 else 272 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, 273 GFX_CTRL_CMD_ID_DESTROY_RINGS); 274 275 /* there might be handshake issue with hardware which needs delay */ 276 mdelay(20); 277 278 /* Wait for response flag (bit 31) */ 279 if (amdgpu_sriov_vf(adev)) 280 ret = psp_wait_for( 281 psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), 282 MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false); 283 else 284 ret = psp_wait_for( 285 psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 286 MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false); 287 288 return ret; 289 } 290 291 static int psp_v11_0_ring_create(struct psp_context *psp, 292 enum psp_ring_type ring_type) 293 { 294 int ret = 0; 295 unsigned int psp_ring_reg = 0; 296 struct psp_ring *ring = &psp->km_ring; 297 struct amdgpu_device *adev = psp->adev; 298 299 if (amdgpu_sriov_vf(adev)) { 300 ring->ring_wptr = 0; 301 ret = psp_v11_0_ring_stop(psp, ring_type); 302 if (ret) { 303 DRM_ERROR("psp_v11_0_ring_stop_sriov failed!\n"); 304 return ret; 305 } 306 307 /* Write low address of the ring to C2PMSG_102 */ 308 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 309 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg); 310 /* Write high address of the ring to C2PMSG_103 */ 311 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 312 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg); 313 314 /* Write the ring initialization command to C2PMSG_101 */ 315 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, 316 GFX_CTRL_CMD_ID_INIT_GPCOM_RING); 317 318 /* there might be handshake issue with hardware which needs delay */ 319 mdelay(20); 320 321 /* Wait for response flag (bit 31) in C2PMSG_101 */ 322 ret = psp_wait_for( 323 psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), 324 MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false); 325 326 } else { 327 /* Wait for sOS ready for ring creation */ 328 ret = psp_wait_for( 329 psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 330 MBOX_TOS_READY_FLAG, MBOX_TOS_READY_MASK, false); 331 if (ret) { 332 DRM_ERROR("Failed to wait for sOS ready for ring creation\n"); 333 return ret; 334 } 335 336 /* Write low address of the ring to C2PMSG_69 */ 337 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 338 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg); 339 /* Write high address of the ring to C2PMSG_70 */ 340 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 341 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg); 342 /* Write size of ring to C2PMSG_71 */ 343 psp_ring_reg = ring->ring_size; 344 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg); 345 /* Write the ring initialization command to C2PMSG_64 */ 346 psp_ring_reg = ring_type; 347 psp_ring_reg = psp_ring_reg << 16; 348 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg); 349 350 /* there might be handshake issue with hardware which needs delay */ 351 mdelay(20); 352 353 /* Wait for response flag (bit 31) in C2PMSG_64 */ 354 ret = psp_wait_for( 355 psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 356 MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false); 357 } 358 359 return ret; 360 } 361 362 363 static int psp_v11_0_ring_destroy(struct psp_context *psp, 364 enum psp_ring_type ring_type) 365 { 366 int ret = 0; 367 struct psp_ring *ring = &psp->km_ring; 368 struct amdgpu_device *adev = psp->adev; 369 370 ret = psp_v11_0_ring_stop(psp, ring_type); 371 if (ret) 372 DRM_ERROR("Fail to stop psp ring\n"); 373 374 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 375 &ring->ring_mem_mc_addr, 376 (void **)&ring->ring_mem); 377 378 return ret; 379 } 380 381 static int psp_v11_0_mode1_reset(struct psp_context *psp) 382 { 383 int ret; 384 uint32_t offset; 385 struct amdgpu_device *adev = psp->adev; 386 387 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64); 388 389 ret = psp_wait_for(psp, offset, MBOX_TOS_READY_FLAG, 390 MBOX_TOS_READY_MASK, false); 391 392 if (ret) { 393 DRM_INFO("psp is not working correctly before mode1 reset!\n"); 394 return -EINVAL; 395 } 396 397 /*send the mode 1 reset command*/ 398 WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST); 399 400 msleep(500); 401 402 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33); 403 404 ret = psp_wait_for(psp, offset, MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 405 false); 406 407 if (ret) { 408 DRM_INFO("psp mode 1 reset failed!\n"); 409 return -EINVAL; 410 } 411 412 DRM_INFO("psp mode1 reset succeed \n"); 413 414 return 0; 415 } 416 417 static int psp_v11_0_memory_training_send_msg(struct psp_context *psp, int msg) 418 { 419 int ret; 420 int i; 421 uint32_t data_32; 422 int max_wait; 423 struct amdgpu_device *adev = psp->adev; 424 425 data_32 = (psp->mem_train_ctx.c2p_train_data_offset >> 20); 426 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, data_32); 427 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, msg); 428 429 max_wait = MEM_TRAIN_SEND_MSG_TIMEOUT_US / adev->usec_timeout; 430 for (i = 0; i < max_wait; i++) { 431 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 432 0x80000000, 0x80000000, false); 433 if (ret == 0) 434 break; 435 } 436 if (i < max_wait) 437 ret = 0; 438 else 439 ret = -ETIME; 440 441 DRM_DEBUG("training %s %s, cost %d @ %d ms\n", 442 (msg == PSP_BL__DRAM_SHORT_TRAIN) ? "short" : "long", 443 (ret == 0) ? "succeed" : "failed", 444 i, adev->usec_timeout/1000); 445 return ret; 446 } 447 448 /* 449 * save and restore process 450 */ 451 static int psp_v11_0_memory_training(struct psp_context *psp, uint32_t ops) 452 { 453 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 454 uint32_t *pcache = (uint32_t *)ctx->sys_cache; 455 struct amdgpu_device *adev = psp->adev; 456 uint32_t p2c_header[4]; 457 uint32_t sz; 458 void *buf; 459 int ret, idx; 460 461 if (ctx->init == PSP_MEM_TRAIN_NOT_SUPPORT) { 462 DRM_DEBUG("Memory training is not supported.\n"); 463 return 0; 464 } else if (ctx->init != PSP_MEM_TRAIN_INIT_SUCCESS) { 465 DRM_ERROR("Memory training initialization failure.\n"); 466 return -EINVAL; 467 } 468 469 if (psp_v11_0_is_sos_alive(psp)) { 470 DRM_DEBUG("SOS is alive, skip memory training.\n"); 471 return 0; 472 } 473 474 amdgpu_device_vram_access(adev, ctx->p2c_train_data_offset, p2c_header, sizeof(p2c_header), false); 475 DRM_DEBUG("sys_cache[%08x,%08x,%08x,%08x] p2c_header[%08x,%08x,%08x,%08x]\n", 476 pcache[0], pcache[1], pcache[2], pcache[3], 477 p2c_header[0], p2c_header[1], p2c_header[2], p2c_header[3]); 478 479 if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) { 480 DRM_DEBUG("Short training depends on restore.\n"); 481 ops |= PSP_MEM_TRAIN_RESTORE; 482 } 483 484 if ((ops & PSP_MEM_TRAIN_RESTORE) && 485 pcache[0] != MEM_TRAIN_SYSTEM_SIGNATURE) { 486 DRM_DEBUG("sys_cache[0] is invalid, restore depends on save.\n"); 487 ops |= PSP_MEM_TRAIN_SAVE; 488 } 489 490 if (p2c_header[0] == MEM_TRAIN_SYSTEM_SIGNATURE && 491 !(pcache[0] == MEM_TRAIN_SYSTEM_SIGNATURE && 492 pcache[3] == p2c_header[3])) { 493 DRM_DEBUG("sys_cache is invalid or out-of-date, need save training data to sys_cache.\n"); 494 ops |= PSP_MEM_TRAIN_SAVE; 495 } 496 497 if ((ops & PSP_MEM_TRAIN_SAVE) && 498 p2c_header[0] != MEM_TRAIN_SYSTEM_SIGNATURE) { 499 DRM_DEBUG("p2c_header[0] is invalid, save depends on long training.\n"); 500 ops |= PSP_MEM_TRAIN_SEND_LONG_MSG; 501 } 502 503 if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) { 504 ops &= ~PSP_MEM_TRAIN_SEND_SHORT_MSG; 505 ops |= PSP_MEM_TRAIN_SAVE; 506 } 507 508 DRM_DEBUG("Memory training ops:%x.\n", ops); 509 510 if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) { 511 /* 512 * Long training will encroach a certain amount on the bottom of VRAM; 513 * save the content from the bottom of VRAM to system memory 514 * before training, and restore it after training to avoid 515 * VRAM corruption. 516 */ 517 sz = BIST_MEM_TRAINING_ENCROACHED_SIZE; 518 519 if (adev->gmc.visible_vram_size < sz || !adev->mman.aper_base_kaddr) { 520 DRM_ERROR("visible_vram_size %llx or aper_base_kaddr %p is not initialized.\n", 521 adev->gmc.visible_vram_size, 522 adev->mman.aper_base_kaddr); 523 return -EINVAL; 524 } 525 526 buf = vmalloc(sz); 527 if (!buf) { 528 DRM_ERROR("failed to allocate system memory.\n"); 529 return -ENOMEM; 530 } 531 532 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 533 memcpy_fromio(buf, adev->mman.aper_base_kaddr, sz); 534 ret = psp_v11_0_memory_training_send_msg(psp, PSP_BL__DRAM_LONG_TRAIN); 535 if (ret) { 536 DRM_ERROR("Send long training msg failed.\n"); 537 vfree(buf); 538 drm_dev_exit(idx); 539 return ret; 540 } 541 542 memcpy_toio(adev->mman.aper_base_kaddr, buf, sz); 543 amdgpu_device_flush_hdp(adev, NULL); 544 vfree(buf); 545 drm_dev_exit(idx); 546 } else { 547 vfree(buf); 548 return -ENODEV; 549 } 550 } 551 552 if (ops & PSP_MEM_TRAIN_SAVE) { 553 amdgpu_device_vram_access(psp->adev, ctx->p2c_train_data_offset, ctx->sys_cache, ctx->train_data_size, false); 554 } 555 556 if (ops & PSP_MEM_TRAIN_RESTORE) { 557 amdgpu_device_vram_access(psp->adev, ctx->c2p_train_data_offset, ctx->sys_cache, ctx->train_data_size, true); 558 } 559 560 if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) { 561 ret = psp_v11_0_memory_training_send_msg(psp, (amdgpu_force_long_training > 0) ? 562 PSP_BL__DRAM_LONG_TRAIN : PSP_BL__DRAM_SHORT_TRAIN); 563 if (ret) { 564 DRM_ERROR("send training msg failed.\n"); 565 return ret; 566 } 567 } 568 ctx->training_cnt++; 569 return 0; 570 } 571 572 static uint32_t psp_v11_0_ring_get_wptr(struct psp_context *psp) 573 { 574 uint32_t data; 575 struct amdgpu_device *adev = psp->adev; 576 577 if (amdgpu_sriov_vf(adev)) 578 data = psp->km_ring.ring_wptr; 579 else 580 data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67); 581 582 return data; 583 } 584 585 static void psp_v11_0_ring_set_wptr(struct psp_context *psp, uint32_t value) 586 { 587 struct amdgpu_device *adev = psp->adev; 588 589 if (amdgpu_sriov_vf(adev)) { 590 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, value); 591 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD); 592 psp->km_ring.ring_wptr = value; 593 } else 594 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value); 595 } 596 597 static int psp_v11_0_load_usbc_pd_fw(struct psp_context *psp, uint64_t fw_pri_mc_addr) 598 { 599 struct amdgpu_device *adev = psp->adev; 600 uint32_t reg_status; 601 int ret, i = 0; 602 603 /* 604 * LFB address which is aligned to 1MB address and has to be 605 * right-shifted by 20 so that LFB address can be passed on a 32-bit C2P 606 * register 607 */ 608 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, (fw_pri_mc_addr >> 20)); 609 610 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 611 0x80000000, 0x80000000, false); 612 if (ret) 613 return ret; 614 615 /* Fireup interrupt so PSP can pick up the address */ 616 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, (GFX_CMD_USB_PD_USE_LFB << 16)); 617 618 /* FW load takes very long time */ 619 do { 620 msleep(1000); 621 reg_status = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35); 622 623 if (reg_status & 0x80000000) 624 goto done; 625 626 } while (++i < USBC_PD_POLLING_LIMIT_S); 627 628 return -ETIME; 629 done: 630 631 if ((reg_status & 0xFFFF) != 0) { 632 DRM_ERROR("Address load failed - MP0_SMN_C2PMSG_35.Bits [15:0] = 0x%04x\n", 633 reg_status & 0xFFFF); 634 return -EIO; 635 } 636 637 return 0; 638 } 639 640 static int psp_v11_0_read_usbc_pd_fw(struct psp_context *psp, uint32_t *fw_ver) 641 { 642 struct amdgpu_device *adev = psp->adev; 643 int ret; 644 645 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, C2PMSG_CMD_GFX_USB_PD_FW_VER); 646 647 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 648 0x80000000, 0x80000000, false); 649 if (!ret) 650 *fw_ver = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36); 651 652 return ret; 653 } 654 655 static const struct psp_funcs psp_v11_0_funcs = { 656 .init_microcode = psp_v11_0_init_microcode, 657 .bootloader_load_kdb = psp_v11_0_bootloader_load_kdb, 658 .bootloader_load_spl = psp_v11_0_bootloader_load_spl, 659 .bootloader_load_sysdrv = psp_v11_0_bootloader_load_sysdrv, 660 .bootloader_load_sos = psp_v11_0_bootloader_load_sos, 661 .ring_create = psp_v11_0_ring_create, 662 .ring_stop = psp_v11_0_ring_stop, 663 .ring_destroy = psp_v11_0_ring_destroy, 664 .mode1_reset = psp_v11_0_mode1_reset, 665 .mem_training = psp_v11_0_memory_training, 666 .ring_get_wptr = psp_v11_0_ring_get_wptr, 667 .ring_set_wptr = psp_v11_0_ring_set_wptr, 668 .load_usbc_pd_fw = psp_v11_0_load_usbc_pd_fw, 669 .read_usbc_pd_fw = psp_v11_0_read_usbc_pd_fw 670 }; 671 672 void psp_v11_0_set_psp_funcs(struct psp_context *psp) 673 { 674 psp->funcs = &psp_v11_0_funcs; 675 } 676