1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #include <linux/firmware.h> 24 #include <linux/module.h> 25 #include <linux/vmalloc.h> 26 #include <drm/drm_drv.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_psp.h" 30 #include "amdgpu_ras.h" 31 #include "amdgpu_ucode.h" 32 #include "soc15_common.h" 33 #include "psp_v11_0.h" 34 35 #include "mp/mp_11_0_offset.h" 36 #include "mp/mp_11_0_sh_mask.h" 37 #include "gc/gc_9_0_offset.h" 38 #include "sdma0/sdma0_4_0_offset.h" 39 #include "nbio/nbio_7_4_offset.h" 40 41 #include "oss/osssys_4_0_offset.h" 42 #include "oss/osssys_4_0_sh_mask.h" 43 44 MODULE_FIRMWARE("amdgpu/vega20_sos.bin"); 45 MODULE_FIRMWARE("amdgpu/vega20_asd.bin"); 46 MODULE_FIRMWARE("amdgpu/vega20_ta.bin"); 47 MODULE_FIRMWARE("amdgpu/navi10_sos.bin"); 48 MODULE_FIRMWARE("amdgpu/navi10_asd.bin"); 49 MODULE_FIRMWARE("amdgpu/navi10_ta.bin"); 50 MODULE_FIRMWARE("amdgpu/navi14_sos.bin"); 51 MODULE_FIRMWARE("amdgpu/navi14_asd.bin"); 52 MODULE_FIRMWARE("amdgpu/navi14_ta.bin"); 53 MODULE_FIRMWARE("amdgpu/navi12_sos.bin"); 54 MODULE_FIRMWARE("amdgpu/navi12_asd.bin"); 55 MODULE_FIRMWARE("amdgpu/navi12_ta.bin"); 56 MODULE_FIRMWARE("amdgpu/navi12_cap.bin"); 57 MODULE_FIRMWARE("amdgpu/arcturus_sos.bin"); 58 MODULE_FIRMWARE("amdgpu/arcturus_asd.bin"); 59 MODULE_FIRMWARE("amdgpu/arcturus_ta.bin"); 60 MODULE_FIRMWARE("amdgpu/sienna_cichlid_sos.bin"); 61 MODULE_FIRMWARE("amdgpu/sienna_cichlid_ta.bin"); 62 MODULE_FIRMWARE("amdgpu/sienna_cichlid_cap.bin"); 63 MODULE_FIRMWARE("amdgpu/navy_flounder_sos.bin"); 64 MODULE_FIRMWARE("amdgpu/navy_flounder_ta.bin"); 65 MODULE_FIRMWARE("amdgpu/vangogh_asd.bin"); 66 MODULE_FIRMWARE("amdgpu/vangogh_toc.bin"); 67 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_sos.bin"); 68 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_ta.bin"); 69 MODULE_FIRMWARE("amdgpu/beige_goby_sos.bin"); 70 MODULE_FIRMWARE("amdgpu/beige_goby_ta.bin"); 71 72 /* address block */ 73 #define smnMP1_FIRMWARE_FLAGS 0x3010024 74 /* navi10 reg offset define */ 75 #define mmRLC_GPM_UCODE_ADDR_NV10 0x5b61 76 #define mmRLC_GPM_UCODE_DATA_NV10 0x5b62 77 #define mmSDMA0_UCODE_ADDR_NV10 0x5880 78 #define mmSDMA0_UCODE_DATA_NV10 0x5881 79 /* memory training timeout define */ 80 #define MEM_TRAIN_SEND_MSG_TIMEOUT_US 3000000 81 82 /* For large FW files the time to complete can be very long */ 83 #define USBC_PD_POLLING_LIMIT_S 240 84 85 /* Read USB-PD from LFB */ 86 #define GFX_CMD_USB_PD_USE_LFB 0x480 87 88 static int psp_v11_0_init_microcode(struct psp_context *psp) 89 { 90 struct amdgpu_device *adev = psp->adev; 91 char ucode_prefix[30]; 92 int err = 0; 93 94 DRM_DEBUG("\n"); 95 96 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); 97 98 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 99 case IP_VERSION(11, 0, 2): 100 case IP_VERSION(11, 0, 4): 101 err = psp_init_sos_microcode(psp, ucode_prefix); 102 if (err) 103 return err; 104 err = psp_init_asd_microcode(psp, ucode_prefix); 105 if (err) 106 return err; 107 err = psp_init_ta_microcode(psp, ucode_prefix); 108 adev->psp.securedisplay_context.context.bin_desc.size_bytes = 0; 109 break; 110 case IP_VERSION(11, 0, 0): 111 case IP_VERSION(11, 0, 5): 112 case IP_VERSION(11, 0, 9): 113 err = psp_init_sos_microcode(psp, ucode_prefix); 114 if (err) 115 return err; 116 err = psp_init_asd_microcode(psp, ucode_prefix); 117 if (err) 118 return err; 119 err = psp_init_ta_microcode(psp, ucode_prefix); 120 adev->psp.securedisplay_context.context.bin_desc.size_bytes = 0; 121 break; 122 case IP_VERSION(11, 0, 7): 123 case IP_VERSION(11, 0, 11): 124 case IP_VERSION(11, 0, 12): 125 case IP_VERSION(11, 0, 13): 126 err = psp_init_sos_microcode(psp, ucode_prefix); 127 if (err) 128 return err; 129 err = psp_init_ta_microcode(psp, ucode_prefix); 130 break; 131 case IP_VERSION(11, 5, 0): 132 case IP_VERSION(11, 5, 2): 133 err = psp_init_asd_microcode(psp, ucode_prefix); 134 if (err) 135 return err; 136 err = psp_init_toc_microcode(psp, ucode_prefix); 137 break; 138 default: 139 dev_warn(adev->dev, "Unsupported MP0 version 0x%08x\n", 140 amdgpu_ip_version(adev, MP0_HWIP, 0)); 141 return -EINVAL; 142 } 143 144 return err; 145 } 146 147 static int psp_v11_wait_for_tos_unload(struct psp_context *psp) 148 { 149 struct amdgpu_device *adev = psp->adev; 150 uint32_t sol_reg1, sol_reg2; 151 int retry_loop; 152 153 /* Wait for the TOS to be unloaded */ 154 for (retry_loop = 0; retry_loop < 20; retry_loop++) { 155 sol_reg1 = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 156 usleep_range(1000, 2000); 157 sol_reg2 = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 158 if (sol_reg1 == sol_reg2) 159 return 0; 160 } 161 dev_err(adev->dev, "TOS unload failed, C2PMSG_33: %x C2PMSG_81: %x", 162 RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_33), 163 RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81)); 164 165 return -ETIME; 166 } 167 168 static int psp_v11_0_wait_for_bootloader(struct psp_context *psp) 169 { 170 struct amdgpu_device *adev = psp->adev; 171 int ret; 172 int retry_loop; 173 174 /* For a reset done at the end of S3, only wait for TOS to be unloaded */ 175 if ((adev->in_s4 || adev->in_s3) && !(adev->flags & AMD_IS_APU) && 176 amdgpu_in_reset(adev)) 177 return psp_v11_wait_for_tos_unload(psp); 178 179 for (retry_loop = 0; retry_loop < 20; retry_loop++) { 180 /* Wait for bootloader to signify that is 181 ready having bit 31 of C2PMSG_35 set to 1 */ 182 ret = psp_wait_for( 183 psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 184 0x80000000, 0x8000FFFF, PSP_WAITREG_NOVERBOSE); 185 186 if (ret == 0) 187 return 0; 188 } 189 190 return ret; 191 } 192 193 static bool psp_v11_0_is_sos_alive(struct psp_context *psp) 194 { 195 struct amdgpu_device *adev = psp->adev; 196 uint32_t sol_reg; 197 198 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 199 200 return sol_reg != 0x0; 201 } 202 203 static int psp_v11_0_bootloader_load_component(struct psp_context *psp, 204 struct psp_bin_desc *bin_desc, 205 enum psp_bootloader_cmd bl_cmd) 206 { 207 int ret; 208 uint32_t psp_gfxdrv_command_reg = 0; 209 struct amdgpu_device *adev = psp->adev; 210 211 /* Check sOS sign of life register to confirm sys driver and sOS 212 * are already been loaded. 213 */ 214 if (psp_v11_0_is_sos_alive(psp)) 215 return 0; 216 217 ret = psp_v11_0_wait_for_bootloader(psp); 218 if (ret) 219 return ret; 220 221 /* Copy PSP System Driver binary to memory */ 222 ret = psp_copy_fw(psp, bin_desc->start_addr, bin_desc->size_bytes); 223 if (ret) 224 return ret; 225 226 /* Provide the sys driver to bootloader */ 227 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, 228 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 229 psp_gfxdrv_command_reg = bl_cmd; 230 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 231 psp_gfxdrv_command_reg); 232 233 ret = psp_v11_0_wait_for_bootloader(psp); 234 235 return ret; 236 } 237 238 static int psp_v11_0_bootloader_load_kdb(struct psp_context *psp) 239 { 240 return psp_v11_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_KEY_DATABASE); 241 } 242 243 static int psp_v11_0_bootloader_load_spl(struct psp_context *psp) 244 { 245 return psp_v11_0_bootloader_load_component(psp, &psp->spl, PSP_BL__LOAD_TOS_SPL_TABLE); 246 } 247 248 static int psp_v11_0_bootloader_load_sysdrv(struct psp_context *psp) 249 { 250 return psp_v11_0_bootloader_load_component(psp, &psp->sys, PSP_BL__LOAD_SYSDRV); 251 } 252 253 static int psp_v11_0_bootloader_load_sos(struct psp_context *psp) 254 { 255 int ret; 256 unsigned int psp_gfxdrv_command_reg = 0; 257 struct amdgpu_device *adev = psp->adev; 258 259 /* Check sOS sign of life register to confirm sys driver and sOS 260 * are already been loaded. 261 */ 262 if (psp_v11_0_is_sos_alive(psp)) 263 return 0; 264 265 ret = psp_v11_0_wait_for_bootloader(psp); 266 if (ret) 267 return ret; 268 269 /* Copy Secure OS binary to PSP memory */ 270 ret = psp_copy_fw(psp, psp->sos.start_addr, psp->sos.size_bytes); 271 if (ret) 272 return ret; 273 274 /* Provide the PSP secure OS to bootloader */ 275 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, 276 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 277 psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV; 278 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 279 psp_gfxdrv_command_reg); 280 281 /* there might be handshake issue with hardware which needs delay */ 282 mdelay(20); 283 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81), 284 RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81), 0, 285 PSP_WAITREG_CHANGED); 286 287 return ret; 288 } 289 290 static int psp_v11_0_ring_stop(struct psp_context *psp, 291 enum psp_ring_type ring_type) 292 { 293 int ret = 0; 294 struct amdgpu_device *adev = psp->adev; 295 296 /* Write the ring destroy command*/ 297 if (amdgpu_sriov_vf(adev)) 298 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, 299 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING); 300 else 301 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, 302 GFX_CTRL_CMD_ID_DESTROY_RINGS); 303 304 /* there might be handshake issue with hardware which needs delay */ 305 mdelay(20); 306 307 /* Wait for response flag (bit 31) */ 308 if (amdgpu_sriov_vf(adev)) 309 ret = psp_wait_for( 310 psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), 311 MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0); 312 else 313 ret = psp_wait_for( 314 psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 315 MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0); 316 317 return ret; 318 } 319 320 static int psp_v11_0_ring_create(struct psp_context *psp, 321 enum psp_ring_type ring_type) 322 { 323 int ret = 0; 324 unsigned int psp_ring_reg = 0; 325 struct psp_ring *ring = &psp->km_ring; 326 struct amdgpu_device *adev = psp->adev; 327 328 if (amdgpu_sriov_vf(adev)) { 329 ring->ring_wptr = 0; 330 ret = psp_v11_0_ring_stop(psp, ring_type); 331 if (ret) { 332 DRM_ERROR("psp_v11_0_ring_stop_sriov failed!\n"); 333 return ret; 334 } 335 336 /* Write low address of the ring to C2PMSG_102 */ 337 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 338 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg); 339 /* Write high address of the ring to C2PMSG_103 */ 340 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 341 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg); 342 343 /* Write the ring initialization command to C2PMSG_101 */ 344 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, 345 GFX_CTRL_CMD_ID_INIT_GPCOM_RING); 346 347 /* there might be handshake issue with hardware which needs delay */ 348 mdelay(20); 349 350 /* Wait for response flag (bit 31) in C2PMSG_101 */ 351 ret = psp_wait_for( 352 psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), 353 MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0); 354 355 } else { 356 /* Wait for sOS ready for ring creation */ 357 ret = psp_wait_for( 358 psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 359 MBOX_TOS_READY_FLAG, MBOX_TOS_READY_MASK, 0); 360 if (ret) { 361 DRM_ERROR("Failed to wait for sOS ready for ring creation\n"); 362 return ret; 363 } 364 365 /* Write low address of the ring to C2PMSG_69 */ 366 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 367 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg); 368 /* Write high address of the ring to C2PMSG_70 */ 369 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 370 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg); 371 /* Write size of ring to C2PMSG_71 */ 372 psp_ring_reg = ring->ring_size; 373 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg); 374 /* Write the ring initialization command to C2PMSG_64 */ 375 psp_ring_reg = ring_type; 376 psp_ring_reg = psp_ring_reg << 16; 377 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg); 378 379 /* there might be handshake issue with hardware which needs delay */ 380 mdelay(20); 381 382 /* Wait for response flag (bit 31) in C2PMSG_64 */ 383 ret = psp_wait_for( 384 psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 385 MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0); 386 } 387 388 return ret; 389 } 390 391 392 static int psp_v11_0_ring_destroy(struct psp_context *psp, 393 enum psp_ring_type ring_type) 394 { 395 int ret = 0; 396 struct psp_ring *ring = &psp->km_ring; 397 struct amdgpu_device *adev = psp->adev; 398 399 ret = psp_v11_0_ring_stop(psp, ring_type); 400 if (ret) 401 DRM_ERROR("Fail to stop psp ring\n"); 402 403 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 404 &ring->ring_mem_mc_addr, 405 (void **)&ring->ring_mem); 406 407 return ret; 408 } 409 410 static int psp_v11_0_mode1_reset(struct psp_context *psp) 411 { 412 int ret; 413 uint32_t offset; 414 struct amdgpu_device *adev = psp->adev; 415 416 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64); 417 418 ret = psp_wait_for(psp, offset, MBOX_TOS_READY_FLAG, 419 MBOX_TOS_READY_MASK, 0); 420 421 if (ret) { 422 drm_info(adev_to_drm(adev), "psp is not working correctly before mode1 reset!\n"); 423 return -EINVAL; 424 } 425 426 /*send the mode 1 reset command*/ 427 WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST); 428 429 msleep(500); 430 431 return 0; 432 } 433 434 static int psp_v11_0_memory_training_send_msg(struct psp_context *psp, int msg) 435 { 436 int ret; 437 int i; 438 uint32_t data_32; 439 int max_wait; 440 struct amdgpu_device *adev = psp->adev; 441 442 data_32 = (psp->mem_train_ctx.c2p_train_data_offset >> 20); 443 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, data_32); 444 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, msg); 445 446 max_wait = MEM_TRAIN_SEND_MSG_TIMEOUT_US / adev->usec_timeout; 447 for (i = 0; i < max_wait; i++) { 448 ret = psp_wait_for( 449 psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 450 0x80000000, 0x80000000, PSP_WAITREG_NOVERBOSE); 451 if (ret == 0) 452 break; 453 } 454 if (i < max_wait) 455 ret = 0; 456 else 457 ret = -ETIME; 458 459 DRM_DEBUG("training %s %s, cost %d @ %d ms\n", 460 (msg == PSP_BL__DRAM_SHORT_TRAIN) ? "short" : "long", 461 (ret == 0) ? "succeed" : "failed", 462 i, adev->usec_timeout/1000); 463 return ret; 464 } 465 466 /* 467 * save and restore process 468 */ 469 static int psp_v11_0_memory_training(struct psp_context *psp, uint32_t ops) 470 { 471 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 472 uint32_t *pcache = (uint32_t *)ctx->sys_cache; 473 struct amdgpu_device *adev = psp->adev; 474 uint32_t p2c_header[4]; 475 uint32_t sz; 476 void *buf; 477 int ret, idx; 478 479 if (ctx->init == PSP_MEM_TRAIN_NOT_SUPPORT) { 480 DRM_DEBUG("Memory training is not supported.\n"); 481 return 0; 482 } else if (ctx->init != PSP_MEM_TRAIN_INIT_SUCCESS) { 483 DRM_ERROR("Memory training initialization failure.\n"); 484 return -EINVAL; 485 } 486 487 if (psp_v11_0_is_sos_alive(psp)) { 488 DRM_DEBUG("SOS is alive, skip memory training.\n"); 489 return 0; 490 } 491 492 amdgpu_device_vram_access(adev, ctx->p2c_train_data_offset, p2c_header, sizeof(p2c_header), false); 493 DRM_DEBUG("sys_cache[%08x,%08x,%08x,%08x] p2c_header[%08x,%08x,%08x,%08x]\n", 494 pcache[0], pcache[1], pcache[2], pcache[3], 495 p2c_header[0], p2c_header[1], p2c_header[2], p2c_header[3]); 496 497 if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) { 498 DRM_DEBUG("Short training depends on restore.\n"); 499 ops |= PSP_MEM_TRAIN_RESTORE; 500 } 501 502 if ((ops & PSP_MEM_TRAIN_RESTORE) && 503 pcache[0] != MEM_TRAIN_SYSTEM_SIGNATURE) { 504 DRM_DEBUG("sys_cache[0] is invalid, restore depends on save.\n"); 505 ops |= PSP_MEM_TRAIN_SAVE; 506 } 507 508 if (p2c_header[0] == MEM_TRAIN_SYSTEM_SIGNATURE && 509 !(pcache[0] == MEM_TRAIN_SYSTEM_SIGNATURE && 510 pcache[3] == p2c_header[3])) { 511 DRM_DEBUG("sys_cache is invalid or out-of-date, need save training data to sys_cache.\n"); 512 ops |= PSP_MEM_TRAIN_SAVE; 513 } 514 515 if ((ops & PSP_MEM_TRAIN_SAVE) && 516 p2c_header[0] != MEM_TRAIN_SYSTEM_SIGNATURE) { 517 DRM_DEBUG("p2c_header[0] is invalid, save depends on long training.\n"); 518 ops |= PSP_MEM_TRAIN_SEND_LONG_MSG; 519 } 520 521 if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) { 522 ops &= ~PSP_MEM_TRAIN_SEND_SHORT_MSG; 523 ops |= PSP_MEM_TRAIN_SAVE; 524 } 525 526 DRM_DEBUG("Memory training ops:%x.\n", ops); 527 528 if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) { 529 /* 530 * Long training will encroach a certain amount on the bottom of VRAM; 531 * save the content from the bottom of VRAM to system memory 532 * before training, and restore it after training to avoid 533 * VRAM corruption. 534 */ 535 sz = BIST_MEM_TRAINING_ENCROACHED_SIZE; 536 537 if (adev->gmc.visible_vram_size < sz || !adev->mman.aper_base_kaddr) { 538 DRM_ERROR("visible_vram_size %llx or aper_base_kaddr %p is not initialized.\n", 539 adev->gmc.visible_vram_size, 540 adev->mman.aper_base_kaddr); 541 return -EINVAL; 542 } 543 544 buf = vmalloc(sz); 545 if (!buf) { 546 DRM_ERROR("failed to allocate system memory.\n"); 547 return -ENOMEM; 548 } 549 550 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 551 memcpy_fromio(buf, adev->mman.aper_base_kaddr, sz); 552 ret = psp_v11_0_memory_training_send_msg(psp, PSP_BL__DRAM_LONG_TRAIN); 553 if (ret) { 554 DRM_ERROR("Send long training msg failed.\n"); 555 vfree(buf); 556 drm_dev_exit(idx); 557 return ret; 558 } 559 560 memcpy_toio(adev->mman.aper_base_kaddr, buf, sz); 561 amdgpu_device_flush_hdp(adev, NULL); 562 vfree(buf); 563 drm_dev_exit(idx); 564 } else { 565 vfree(buf); 566 return -ENODEV; 567 } 568 } 569 570 if (ops & PSP_MEM_TRAIN_SAVE) { 571 amdgpu_device_vram_access(psp->adev, ctx->p2c_train_data_offset, ctx->sys_cache, ctx->train_data_size, false); 572 } 573 574 if (ops & PSP_MEM_TRAIN_RESTORE) { 575 amdgpu_device_vram_access(psp->adev, ctx->c2p_train_data_offset, ctx->sys_cache, ctx->train_data_size, true); 576 } 577 578 if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) { 579 ret = psp_v11_0_memory_training_send_msg(psp, (amdgpu_force_long_training > 0) ? 580 PSP_BL__DRAM_LONG_TRAIN : PSP_BL__DRAM_SHORT_TRAIN); 581 if (ret) { 582 DRM_ERROR("send training msg failed.\n"); 583 return ret; 584 } 585 } 586 ctx->training_cnt++; 587 return 0; 588 } 589 590 static uint32_t psp_v11_0_ring_get_wptr(struct psp_context *psp) 591 { 592 uint32_t data; 593 struct amdgpu_device *adev = psp->adev; 594 595 if (amdgpu_sriov_vf(adev)) 596 data = psp->km_ring.ring_wptr; 597 else 598 data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67); 599 600 return data; 601 } 602 603 static void psp_v11_0_ring_set_wptr(struct psp_context *psp, uint32_t value) 604 { 605 struct amdgpu_device *adev = psp->adev; 606 607 if (amdgpu_sriov_vf(adev)) { 608 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, value); 609 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD); 610 psp->km_ring.ring_wptr = value; 611 } else 612 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value); 613 } 614 615 static int psp_v11_0_load_usbc_pd_fw(struct psp_context *psp, uint64_t fw_pri_mc_addr) 616 { 617 struct amdgpu_device *adev = psp->adev; 618 uint32_t reg_status; 619 int ret, i = 0; 620 621 /* 622 * LFB address which is aligned to 1MB address and has to be 623 * right-shifted by 20 so that LFB address can be passed on a 32-bit C2P 624 * register 625 */ 626 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, (fw_pri_mc_addr >> 20)); 627 628 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 629 0x80000000, 0x80000000, 0); 630 if (ret) 631 return ret; 632 633 /* Fireup interrupt so PSP can pick up the address */ 634 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, (GFX_CMD_USB_PD_USE_LFB << 16)); 635 636 /* FW load takes very long time */ 637 do { 638 msleep(1000); 639 reg_status = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35); 640 641 if (reg_status & 0x80000000) 642 goto done; 643 644 } while (++i < USBC_PD_POLLING_LIMIT_S); 645 646 return -ETIME; 647 done: 648 649 if ((reg_status & 0xFFFF) != 0) { 650 DRM_ERROR("Address load failed - MP0_SMN_C2PMSG_35.Bits [15:0] = 0x%04x\n", 651 reg_status & 0xFFFF); 652 return -EIO; 653 } 654 655 return 0; 656 } 657 658 static int psp_v11_0_read_usbc_pd_fw(struct psp_context *psp, uint32_t *fw_ver) 659 { 660 struct amdgpu_device *adev = psp->adev; 661 int ret; 662 663 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, C2PMSG_CMD_GFX_USB_PD_FW_VER); 664 665 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 666 0x80000000, 0x80000000, 0); 667 if (!ret) 668 *fw_ver = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36); 669 670 return ret; 671 } 672 673 static const struct psp_funcs psp_v11_0_funcs = { 674 .init_microcode = psp_v11_0_init_microcode, 675 .bootloader_load_kdb = psp_v11_0_bootloader_load_kdb, 676 .bootloader_load_spl = psp_v11_0_bootloader_load_spl, 677 .bootloader_load_sysdrv = psp_v11_0_bootloader_load_sysdrv, 678 .bootloader_load_sos = psp_v11_0_bootloader_load_sos, 679 .ring_create = psp_v11_0_ring_create, 680 .ring_stop = psp_v11_0_ring_stop, 681 .ring_destroy = psp_v11_0_ring_destroy, 682 .mode1_reset = psp_v11_0_mode1_reset, 683 .mem_training = psp_v11_0_memory_training, 684 .ring_get_wptr = psp_v11_0_ring_get_wptr, 685 .ring_set_wptr = psp_v11_0_ring_set_wptr, 686 .load_usbc_pd_fw = psp_v11_0_load_usbc_pd_fw, 687 .read_usbc_pd_fw = psp_v11_0_read_usbc_pd_fw, 688 .wait_for_bootloader = psp_v11_0_wait_for_bootloader 689 }; 690 691 void psp_v11_0_set_psp_funcs(struct psp_context *psp) 692 { 693 psp->funcs = &psp_v11_0_funcs; 694 } 695