1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #include <linux/firmware.h> 24 #include <linux/module.h> 25 #include <linux/vmalloc.h> 26 #include <drm/drm_drv.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_psp.h" 30 #include "amdgpu_ras.h" 31 #include "amdgpu_ucode.h" 32 #include "soc15_common.h" 33 #include "psp_v11_0.h" 34 35 #include "mp/mp_11_0_offset.h" 36 #include "mp/mp_11_0_sh_mask.h" 37 #include "gc/gc_9_0_offset.h" 38 #include "sdma0/sdma0_4_0_offset.h" 39 #include "nbio/nbio_7_4_offset.h" 40 41 #include "oss/osssys_4_0_offset.h" 42 #include "oss/osssys_4_0_sh_mask.h" 43 44 MODULE_FIRMWARE("amdgpu/vega20_sos.bin"); 45 MODULE_FIRMWARE("amdgpu/vega20_asd.bin"); 46 MODULE_FIRMWARE("amdgpu/vega20_ta.bin"); 47 MODULE_FIRMWARE("amdgpu/navi10_sos.bin"); 48 MODULE_FIRMWARE("amdgpu/navi10_asd.bin"); 49 MODULE_FIRMWARE("amdgpu/navi10_ta.bin"); 50 MODULE_FIRMWARE("amdgpu/navi14_sos.bin"); 51 MODULE_FIRMWARE("amdgpu/navi14_asd.bin"); 52 MODULE_FIRMWARE("amdgpu/navi14_ta.bin"); 53 MODULE_FIRMWARE("amdgpu/navi12_sos.bin"); 54 MODULE_FIRMWARE("amdgpu/navi12_asd.bin"); 55 MODULE_FIRMWARE("amdgpu/navi12_ta.bin"); 56 MODULE_FIRMWARE("amdgpu/navi12_cap.bin"); 57 MODULE_FIRMWARE("amdgpu/arcturus_sos.bin"); 58 MODULE_FIRMWARE("amdgpu/arcturus_asd.bin"); 59 MODULE_FIRMWARE("amdgpu/arcturus_ta.bin"); 60 MODULE_FIRMWARE("amdgpu/sienna_cichlid_sos.bin"); 61 MODULE_FIRMWARE("amdgpu/sienna_cichlid_ta.bin"); 62 MODULE_FIRMWARE("amdgpu/sienna_cichlid_cap.bin"); 63 MODULE_FIRMWARE("amdgpu/navy_flounder_sos.bin"); 64 MODULE_FIRMWARE("amdgpu/navy_flounder_ta.bin"); 65 MODULE_FIRMWARE("amdgpu/vangogh_asd.bin"); 66 MODULE_FIRMWARE("amdgpu/vangogh_toc.bin"); 67 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_sos.bin"); 68 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_ta.bin"); 69 MODULE_FIRMWARE("amdgpu/beige_goby_sos.bin"); 70 MODULE_FIRMWARE("amdgpu/beige_goby_ta.bin"); 71 72 /* address block */ 73 #define smnMP1_FIRMWARE_FLAGS 0x3010024 74 /* navi10 reg offset define */ 75 #define mmRLC_GPM_UCODE_ADDR_NV10 0x5b61 76 #define mmRLC_GPM_UCODE_DATA_NV10 0x5b62 77 #define mmSDMA0_UCODE_ADDR_NV10 0x5880 78 #define mmSDMA0_UCODE_DATA_NV10 0x5881 79 /* memory training timeout define */ 80 #define MEM_TRAIN_SEND_MSG_TIMEOUT_US 3000000 81 82 /* For large FW files the time to complete can be very long */ 83 #define USBC_PD_POLLING_LIMIT_S 240 84 85 /* Read USB-PD from LFB */ 86 #define GFX_CMD_USB_PD_USE_LFB 0x480 87 88 static int psp_v11_0_init_microcode(struct psp_context *psp) 89 { 90 struct amdgpu_device *adev = psp->adev; 91 char ucode_prefix[30]; 92 int err = 0; 93 94 DRM_DEBUG("\n"); 95 96 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); 97 98 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 99 case IP_VERSION(11, 0, 2): 100 case IP_VERSION(11, 0, 4): 101 err = psp_init_sos_microcode(psp, ucode_prefix); 102 if (err) 103 return err; 104 err = psp_init_asd_microcode(psp, ucode_prefix); 105 if (err) 106 return err; 107 err = psp_init_ta_microcode(psp, ucode_prefix); 108 adev->psp.securedisplay_context.context.bin_desc.size_bytes = 0; 109 break; 110 case IP_VERSION(11, 0, 0): 111 case IP_VERSION(11, 0, 5): 112 case IP_VERSION(11, 0, 9): 113 err = psp_init_sos_microcode(psp, ucode_prefix); 114 if (err) 115 return err; 116 err = psp_init_asd_microcode(psp, ucode_prefix); 117 if (err) 118 return err; 119 err = psp_init_ta_microcode(psp, ucode_prefix); 120 adev->psp.securedisplay_context.context.bin_desc.size_bytes = 0; 121 break; 122 case IP_VERSION(11, 0, 7): 123 case IP_VERSION(11, 0, 11): 124 case IP_VERSION(11, 0, 12): 125 case IP_VERSION(11, 0, 13): 126 err = psp_init_sos_microcode(psp, ucode_prefix); 127 if (err) 128 return err; 129 err = psp_init_ta_microcode(psp, ucode_prefix); 130 break; 131 case IP_VERSION(11, 5, 0): 132 case IP_VERSION(11, 5, 2): 133 err = psp_init_asd_microcode(psp, ucode_prefix); 134 if (err) 135 return err; 136 err = psp_init_toc_microcode(psp, ucode_prefix); 137 break; 138 default: 139 BUG(); 140 } 141 142 return err; 143 } 144 145 static int psp_v11_wait_for_tos_unload(struct psp_context *psp) 146 { 147 struct amdgpu_device *adev = psp->adev; 148 uint32_t sol_reg1, sol_reg2; 149 int retry_loop; 150 151 /* Wait for the TOS to be unloaded */ 152 for (retry_loop = 0; retry_loop < 20; retry_loop++) { 153 sol_reg1 = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 154 usleep_range(1000, 2000); 155 sol_reg2 = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 156 if (sol_reg1 == sol_reg2) 157 return 0; 158 } 159 dev_err(adev->dev, "TOS unload failed, C2PMSG_33: %x C2PMSG_81: %x", 160 RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_33), 161 RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81)); 162 163 return -ETIME; 164 } 165 166 static int psp_v11_0_wait_for_bootloader(struct psp_context *psp) 167 { 168 struct amdgpu_device *adev = psp->adev; 169 int ret; 170 int retry_loop; 171 172 /* For a reset done at the end of S3, only wait for TOS to be unloaded */ 173 if ((adev->in_s4 || adev->in_s3) && !(adev->flags & AMD_IS_APU) && 174 amdgpu_in_reset(adev)) 175 return psp_v11_wait_for_tos_unload(psp); 176 177 for (retry_loop = 0; retry_loop < 20; retry_loop++) { 178 /* Wait for bootloader to signify that is 179 ready having bit 31 of C2PMSG_35 set to 1 */ 180 ret = psp_wait_for( 181 psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 182 0x80000000, 0x8000FFFF, PSP_WAITREG_NOVERBOSE); 183 184 if (ret == 0) 185 return 0; 186 } 187 188 return ret; 189 } 190 191 static bool psp_v11_0_is_sos_alive(struct psp_context *psp) 192 { 193 struct amdgpu_device *adev = psp->adev; 194 uint32_t sol_reg; 195 196 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 197 198 return sol_reg != 0x0; 199 } 200 201 static int psp_v11_0_bootloader_load_component(struct psp_context *psp, 202 struct psp_bin_desc *bin_desc, 203 enum psp_bootloader_cmd bl_cmd) 204 { 205 int ret; 206 uint32_t psp_gfxdrv_command_reg = 0; 207 struct amdgpu_device *adev = psp->adev; 208 209 /* Check sOS sign of life register to confirm sys driver and sOS 210 * are already been loaded. 211 */ 212 if (psp_v11_0_is_sos_alive(psp)) 213 return 0; 214 215 ret = psp_v11_0_wait_for_bootloader(psp); 216 if (ret) 217 return ret; 218 219 /* Copy PSP System Driver binary to memory */ 220 ret = psp_copy_fw(psp, bin_desc->start_addr, bin_desc->size_bytes); 221 if (ret) 222 return ret; 223 224 /* Provide the sys driver to bootloader */ 225 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, 226 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 227 psp_gfxdrv_command_reg = bl_cmd; 228 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 229 psp_gfxdrv_command_reg); 230 231 ret = psp_v11_0_wait_for_bootloader(psp); 232 233 return ret; 234 } 235 236 static int psp_v11_0_bootloader_load_kdb(struct psp_context *psp) 237 { 238 return psp_v11_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_KEY_DATABASE); 239 } 240 241 static int psp_v11_0_bootloader_load_spl(struct psp_context *psp) 242 { 243 return psp_v11_0_bootloader_load_component(psp, &psp->spl, PSP_BL__LOAD_TOS_SPL_TABLE); 244 } 245 246 static int psp_v11_0_bootloader_load_sysdrv(struct psp_context *psp) 247 { 248 return psp_v11_0_bootloader_load_component(psp, &psp->sys, PSP_BL__LOAD_SYSDRV); 249 } 250 251 static int psp_v11_0_bootloader_load_sos(struct psp_context *psp) 252 { 253 int ret; 254 unsigned int psp_gfxdrv_command_reg = 0; 255 struct amdgpu_device *adev = psp->adev; 256 257 /* Check sOS sign of life register to confirm sys driver and sOS 258 * are already been loaded. 259 */ 260 if (psp_v11_0_is_sos_alive(psp)) 261 return 0; 262 263 ret = psp_v11_0_wait_for_bootloader(psp); 264 if (ret) 265 return ret; 266 267 /* Copy Secure OS binary to PSP memory */ 268 ret = psp_copy_fw(psp, psp->sos.start_addr, psp->sos.size_bytes); 269 if (ret) 270 return ret; 271 272 /* Provide the PSP secure OS to bootloader */ 273 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, 274 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 275 psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV; 276 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 277 psp_gfxdrv_command_reg); 278 279 /* there might be handshake issue with hardware which needs delay */ 280 mdelay(20); 281 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81), 282 RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81), 0, 283 PSP_WAITREG_CHANGED); 284 285 return ret; 286 } 287 288 static int psp_v11_0_ring_stop(struct psp_context *psp, 289 enum psp_ring_type ring_type) 290 { 291 int ret = 0; 292 struct amdgpu_device *adev = psp->adev; 293 294 /* Write the ring destroy command*/ 295 if (amdgpu_sriov_vf(adev)) 296 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, 297 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING); 298 else 299 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, 300 GFX_CTRL_CMD_ID_DESTROY_RINGS); 301 302 /* there might be handshake issue with hardware which needs delay */ 303 mdelay(20); 304 305 /* Wait for response flag (bit 31) */ 306 if (amdgpu_sriov_vf(adev)) 307 ret = psp_wait_for( 308 psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), 309 MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0); 310 else 311 ret = psp_wait_for( 312 psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 313 MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0); 314 315 return ret; 316 } 317 318 static int psp_v11_0_ring_create(struct psp_context *psp, 319 enum psp_ring_type ring_type) 320 { 321 int ret = 0; 322 unsigned int psp_ring_reg = 0; 323 struct psp_ring *ring = &psp->km_ring; 324 struct amdgpu_device *adev = psp->adev; 325 326 if (amdgpu_sriov_vf(adev)) { 327 ring->ring_wptr = 0; 328 ret = psp_v11_0_ring_stop(psp, ring_type); 329 if (ret) { 330 DRM_ERROR("psp_v11_0_ring_stop_sriov failed!\n"); 331 return ret; 332 } 333 334 /* Write low address of the ring to C2PMSG_102 */ 335 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 336 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg); 337 /* Write high address of the ring to C2PMSG_103 */ 338 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 339 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg); 340 341 /* Write the ring initialization command to C2PMSG_101 */ 342 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, 343 GFX_CTRL_CMD_ID_INIT_GPCOM_RING); 344 345 /* there might be handshake issue with hardware which needs delay */ 346 mdelay(20); 347 348 /* Wait for response flag (bit 31) in C2PMSG_101 */ 349 ret = psp_wait_for( 350 psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), 351 MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0); 352 353 } else { 354 /* Wait for sOS ready for ring creation */ 355 ret = psp_wait_for( 356 psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 357 MBOX_TOS_READY_FLAG, MBOX_TOS_READY_MASK, 0); 358 if (ret) { 359 DRM_ERROR("Failed to wait for sOS ready for ring creation\n"); 360 return ret; 361 } 362 363 /* Write low address of the ring to C2PMSG_69 */ 364 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 365 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg); 366 /* Write high address of the ring to C2PMSG_70 */ 367 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 368 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg); 369 /* Write size of ring to C2PMSG_71 */ 370 psp_ring_reg = ring->ring_size; 371 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg); 372 /* Write the ring initialization command to C2PMSG_64 */ 373 psp_ring_reg = ring_type; 374 psp_ring_reg = psp_ring_reg << 16; 375 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg); 376 377 /* there might be handshake issue with hardware which needs delay */ 378 mdelay(20); 379 380 /* Wait for response flag (bit 31) in C2PMSG_64 */ 381 ret = psp_wait_for( 382 psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 383 MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0); 384 } 385 386 return ret; 387 } 388 389 390 static int psp_v11_0_ring_destroy(struct psp_context *psp, 391 enum psp_ring_type ring_type) 392 { 393 int ret = 0; 394 struct psp_ring *ring = &psp->km_ring; 395 struct amdgpu_device *adev = psp->adev; 396 397 ret = psp_v11_0_ring_stop(psp, ring_type); 398 if (ret) 399 DRM_ERROR("Fail to stop psp ring\n"); 400 401 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 402 &ring->ring_mem_mc_addr, 403 (void **)&ring->ring_mem); 404 405 return ret; 406 } 407 408 static int psp_v11_0_mode1_reset(struct psp_context *psp) 409 { 410 int ret; 411 uint32_t offset; 412 struct amdgpu_device *adev = psp->adev; 413 414 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64); 415 416 ret = psp_wait_for(psp, offset, MBOX_TOS_READY_FLAG, 417 MBOX_TOS_READY_MASK, 0); 418 419 if (ret) { 420 drm_info(adev_to_drm(adev), "psp is not working correctly before mode1 reset!\n"); 421 return -EINVAL; 422 } 423 424 /*send the mode 1 reset command*/ 425 WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST); 426 427 msleep(500); 428 429 return 0; 430 } 431 432 static int psp_v11_0_memory_training_send_msg(struct psp_context *psp, int msg) 433 { 434 int ret; 435 int i; 436 uint32_t data_32; 437 int max_wait; 438 struct amdgpu_device *adev = psp->adev; 439 440 data_32 = (psp->mem_train_ctx.c2p_train_data_offset >> 20); 441 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, data_32); 442 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, msg); 443 444 max_wait = MEM_TRAIN_SEND_MSG_TIMEOUT_US / adev->usec_timeout; 445 for (i = 0; i < max_wait; i++) { 446 ret = psp_wait_for( 447 psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 448 0x80000000, 0x80000000, PSP_WAITREG_NOVERBOSE); 449 if (ret == 0) 450 break; 451 } 452 if (i < max_wait) 453 ret = 0; 454 else 455 ret = -ETIME; 456 457 DRM_DEBUG("training %s %s, cost %d @ %d ms\n", 458 (msg == PSP_BL__DRAM_SHORT_TRAIN) ? "short" : "long", 459 (ret == 0) ? "succeed" : "failed", 460 i, adev->usec_timeout/1000); 461 return ret; 462 } 463 464 /* 465 * save and restore process 466 */ 467 static int psp_v11_0_memory_training(struct psp_context *psp, uint32_t ops) 468 { 469 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 470 uint32_t *pcache = (uint32_t *)ctx->sys_cache; 471 struct amdgpu_device *adev = psp->adev; 472 uint32_t p2c_header[4]; 473 uint32_t sz; 474 void *buf; 475 int ret, idx; 476 477 if (ctx->init == PSP_MEM_TRAIN_NOT_SUPPORT) { 478 DRM_DEBUG("Memory training is not supported.\n"); 479 return 0; 480 } else if (ctx->init != PSP_MEM_TRAIN_INIT_SUCCESS) { 481 DRM_ERROR("Memory training initialization failure.\n"); 482 return -EINVAL; 483 } 484 485 if (psp_v11_0_is_sos_alive(psp)) { 486 DRM_DEBUG("SOS is alive, skip memory training.\n"); 487 return 0; 488 } 489 490 amdgpu_device_vram_access(adev, ctx->p2c_train_data_offset, p2c_header, sizeof(p2c_header), false); 491 DRM_DEBUG("sys_cache[%08x,%08x,%08x,%08x] p2c_header[%08x,%08x,%08x,%08x]\n", 492 pcache[0], pcache[1], pcache[2], pcache[3], 493 p2c_header[0], p2c_header[1], p2c_header[2], p2c_header[3]); 494 495 if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) { 496 DRM_DEBUG("Short training depends on restore.\n"); 497 ops |= PSP_MEM_TRAIN_RESTORE; 498 } 499 500 if ((ops & PSP_MEM_TRAIN_RESTORE) && 501 pcache[0] != MEM_TRAIN_SYSTEM_SIGNATURE) { 502 DRM_DEBUG("sys_cache[0] is invalid, restore depends on save.\n"); 503 ops |= PSP_MEM_TRAIN_SAVE; 504 } 505 506 if (p2c_header[0] == MEM_TRAIN_SYSTEM_SIGNATURE && 507 !(pcache[0] == MEM_TRAIN_SYSTEM_SIGNATURE && 508 pcache[3] == p2c_header[3])) { 509 DRM_DEBUG("sys_cache is invalid or out-of-date, need save training data to sys_cache.\n"); 510 ops |= PSP_MEM_TRAIN_SAVE; 511 } 512 513 if ((ops & PSP_MEM_TRAIN_SAVE) && 514 p2c_header[0] != MEM_TRAIN_SYSTEM_SIGNATURE) { 515 DRM_DEBUG("p2c_header[0] is invalid, save depends on long training.\n"); 516 ops |= PSP_MEM_TRAIN_SEND_LONG_MSG; 517 } 518 519 if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) { 520 ops &= ~PSP_MEM_TRAIN_SEND_SHORT_MSG; 521 ops |= PSP_MEM_TRAIN_SAVE; 522 } 523 524 DRM_DEBUG("Memory training ops:%x.\n", ops); 525 526 if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) { 527 /* 528 * Long training will encroach a certain amount on the bottom of VRAM; 529 * save the content from the bottom of VRAM to system memory 530 * before training, and restore it after training to avoid 531 * VRAM corruption. 532 */ 533 sz = BIST_MEM_TRAINING_ENCROACHED_SIZE; 534 535 if (adev->gmc.visible_vram_size < sz || !adev->mman.aper_base_kaddr) { 536 DRM_ERROR("visible_vram_size %llx or aper_base_kaddr %p is not initialized.\n", 537 adev->gmc.visible_vram_size, 538 adev->mman.aper_base_kaddr); 539 return -EINVAL; 540 } 541 542 buf = vmalloc(sz); 543 if (!buf) { 544 DRM_ERROR("failed to allocate system memory.\n"); 545 return -ENOMEM; 546 } 547 548 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 549 memcpy_fromio(buf, adev->mman.aper_base_kaddr, sz); 550 ret = psp_v11_0_memory_training_send_msg(psp, PSP_BL__DRAM_LONG_TRAIN); 551 if (ret) { 552 DRM_ERROR("Send long training msg failed.\n"); 553 vfree(buf); 554 drm_dev_exit(idx); 555 return ret; 556 } 557 558 memcpy_toio(adev->mman.aper_base_kaddr, buf, sz); 559 amdgpu_device_flush_hdp(adev, NULL); 560 vfree(buf); 561 drm_dev_exit(idx); 562 } else { 563 vfree(buf); 564 return -ENODEV; 565 } 566 } 567 568 if (ops & PSP_MEM_TRAIN_SAVE) { 569 amdgpu_device_vram_access(psp->adev, ctx->p2c_train_data_offset, ctx->sys_cache, ctx->train_data_size, false); 570 } 571 572 if (ops & PSP_MEM_TRAIN_RESTORE) { 573 amdgpu_device_vram_access(psp->adev, ctx->c2p_train_data_offset, ctx->sys_cache, ctx->train_data_size, true); 574 } 575 576 if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) { 577 ret = psp_v11_0_memory_training_send_msg(psp, (amdgpu_force_long_training > 0) ? 578 PSP_BL__DRAM_LONG_TRAIN : PSP_BL__DRAM_SHORT_TRAIN); 579 if (ret) { 580 DRM_ERROR("send training msg failed.\n"); 581 return ret; 582 } 583 } 584 ctx->training_cnt++; 585 return 0; 586 } 587 588 static uint32_t psp_v11_0_ring_get_wptr(struct psp_context *psp) 589 { 590 uint32_t data; 591 struct amdgpu_device *adev = psp->adev; 592 593 if (amdgpu_sriov_vf(adev)) 594 data = psp->km_ring.ring_wptr; 595 else 596 data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67); 597 598 return data; 599 } 600 601 static void psp_v11_0_ring_set_wptr(struct psp_context *psp, uint32_t value) 602 { 603 struct amdgpu_device *adev = psp->adev; 604 605 if (amdgpu_sriov_vf(adev)) { 606 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, value); 607 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD); 608 psp->km_ring.ring_wptr = value; 609 } else 610 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value); 611 } 612 613 static int psp_v11_0_load_usbc_pd_fw(struct psp_context *psp, uint64_t fw_pri_mc_addr) 614 { 615 struct amdgpu_device *adev = psp->adev; 616 uint32_t reg_status; 617 int ret, i = 0; 618 619 /* 620 * LFB address which is aligned to 1MB address and has to be 621 * right-shifted by 20 so that LFB address can be passed on a 32-bit C2P 622 * register 623 */ 624 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, (fw_pri_mc_addr >> 20)); 625 626 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 627 0x80000000, 0x80000000, 0); 628 if (ret) 629 return ret; 630 631 /* Fireup interrupt so PSP can pick up the address */ 632 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, (GFX_CMD_USB_PD_USE_LFB << 16)); 633 634 /* FW load takes very long time */ 635 do { 636 msleep(1000); 637 reg_status = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35); 638 639 if (reg_status & 0x80000000) 640 goto done; 641 642 } while (++i < USBC_PD_POLLING_LIMIT_S); 643 644 return -ETIME; 645 done: 646 647 if ((reg_status & 0xFFFF) != 0) { 648 DRM_ERROR("Address load failed - MP0_SMN_C2PMSG_35.Bits [15:0] = 0x%04x\n", 649 reg_status & 0xFFFF); 650 return -EIO; 651 } 652 653 return 0; 654 } 655 656 static int psp_v11_0_read_usbc_pd_fw(struct psp_context *psp, uint32_t *fw_ver) 657 { 658 struct amdgpu_device *adev = psp->adev; 659 int ret; 660 661 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, C2PMSG_CMD_GFX_USB_PD_FW_VER); 662 663 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 664 0x80000000, 0x80000000, 0); 665 if (!ret) 666 *fw_ver = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36); 667 668 return ret; 669 } 670 671 static const struct psp_funcs psp_v11_0_funcs = { 672 .init_microcode = psp_v11_0_init_microcode, 673 .bootloader_load_kdb = psp_v11_0_bootloader_load_kdb, 674 .bootloader_load_spl = psp_v11_0_bootloader_load_spl, 675 .bootloader_load_sysdrv = psp_v11_0_bootloader_load_sysdrv, 676 .bootloader_load_sos = psp_v11_0_bootloader_load_sos, 677 .ring_create = psp_v11_0_ring_create, 678 .ring_stop = psp_v11_0_ring_stop, 679 .ring_destroy = psp_v11_0_ring_destroy, 680 .mode1_reset = psp_v11_0_mode1_reset, 681 .mem_training = psp_v11_0_memory_training, 682 .ring_get_wptr = psp_v11_0_ring_get_wptr, 683 .ring_set_wptr = psp_v11_0_ring_set_wptr, 684 .load_usbc_pd_fw = psp_v11_0_load_usbc_pd_fw, 685 .read_usbc_pd_fw = psp_v11_0_read_usbc_pd_fw, 686 .wait_for_bootloader = psp_v11_0_wait_for_bootloader 687 }; 688 689 void psp_v11_0_set_psp_funcs(struct psp_context *psp) 690 { 691 psp->funcs = &psp_v11_0_funcs; 692 } 693