1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 #include <linux/module.h> 28 #include <linux/pci.h> 29 30 #include "amdgpu.h" 31 #include "amdgpu_psp.h" 32 #include "amdgpu_ucode.h" 33 #include "soc15_common.h" 34 #include "psp_v10_0.h" 35 36 #include "mp/mp_10_0_offset.h" 37 #include "gc/gc_9_1_offset.h" 38 #include "sdma0/sdma0_4_1_offset.h" 39 40 MODULE_FIRMWARE("amdgpu/raven_asd.bin"); 41 MODULE_FIRMWARE("amdgpu/picasso_asd.bin"); 42 MODULE_FIRMWARE("amdgpu/raven2_asd.bin"); 43 MODULE_FIRMWARE("amdgpu/picasso_ta.bin"); 44 MODULE_FIRMWARE("amdgpu/raven2_ta.bin"); 45 MODULE_FIRMWARE("amdgpu/raven_ta.bin"); 46 47 static int psp_v10_0_init_microcode(struct psp_context *psp) 48 { 49 struct amdgpu_device *adev = psp->adev; 50 char ucode_prefix[30]; 51 int err = 0; 52 DRM_DEBUG("\n"); 53 54 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); 55 56 err = psp_init_asd_microcode(psp, ucode_prefix); 57 if (err) 58 return err; 59 60 err = psp_init_ta_microcode(psp, ucode_prefix); 61 if ((amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 1, 0)) && 62 (adev->pdev->revision == 0xa1) && 63 (psp->securedisplay_context.context.bin_desc.fw_version >= 64 0x27000008)) { 65 adev->psp.securedisplay_context.context.bin_desc.size_bytes = 0; 66 } 67 return err; 68 } 69 70 static int psp_v10_0_ring_create(struct psp_context *psp, 71 enum psp_ring_type ring_type) 72 { 73 int ret = 0; 74 unsigned int psp_ring_reg = 0; 75 struct psp_ring *ring = &psp->km_ring; 76 struct amdgpu_device *adev = psp->adev; 77 78 /* Write low address of the ring to C2PMSG_69 */ 79 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 80 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg); 81 /* Write high address of the ring to C2PMSG_70 */ 82 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 83 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg); 84 /* Write size of ring to C2PMSG_71 */ 85 psp_ring_reg = ring->ring_size; 86 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg); 87 /* Write the ring initialization command to C2PMSG_64 */ 88 psp_ring_reg = ring_type; 89 psp_ring_reg = psp_ring_reg << 16; 90 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg); 91 92 /* There might be handshake issue with hardware which needs delay */ 93 mdelay(20); 94 95 /* Wait for response flag (bit 31) in C2PMSG_64 */ 96 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 97 0x80000000, 0x8000FFFF, false); 98 99 return ret; 100 } 101 102 static int psp_v10_0_ring_stop(struct psp_context *psp, 103 enum psp_ring_type ring_type) 104 { 105 int ret = 0; 106 unsigned int psp_ring_reg = 0; 107 struct amdgpu_device *adev = psp->adev; 108 109 /* Write the ring destroy command to C2PMSG_64 */ 110 psp_ring_reg = 3 << 16; 111 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg); 112 113 /* There might be handshake issue with hardware which needs delay */ 114 mdelay(20); 115 116 /* Wait for response flag (bit 31) in C2PMSG_64 */ 117 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 118 0x80000000, 0x80000000, false); 119 120 return ret; 121 } 122 123 static int psp_v10_0_ring_destroy(struct psp_context *psp, 124 enum psp_ring_type ring_type) 125 { 126 int ret = 0; 127 struct psp_ring *ring = &psp->km_ring; 128 struct amdgpu_device *adev = psp->adev; 129 130 ret = psp_v10_0_ring_stop(psp, ring_type); 131 if (ret) 132 DRM_ERROR("Fail to stop psp ring\n"); 133 134 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 135 &ring->ring_mem_mc_addr, 136 (void **)&ring->ring_mem); 137 138 return ret; 139 } 140 141 static int psp_v10_0_mode1_reset(struct psp_context *psp) 142 { 143 DRM_INFO("psp mode 1 reset not supported now! \n"); 144 return -EINVAL; 145 } 146 147 static uint32_t psp_v10_0_ring_get_wptr(struct psp_context *psp) 148 { 149 struct amdgpu_device *adev = psp->adev; 150 151 return RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67); 152 } 153 154 static void psp_v10_0_ring_set_wptr(struct psp_context *psp, uint32_t value) 155 { 156 struct amdgpu_device *adev = psp->adev; 157 158 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value); 159 } 160 161 static const struct psp_funcs psp_v10_0_funcs = { 162 .init_microcode = psp_v10_0_init_microcode, 163 .ring_create = psp_v10_0_ring_create, 164 .ring_stop = psp_v10_0_ring_stop, 165 .ring_destroy = psp_v10_0_ring_destroy, 166 .mode1_reset = psp_v10_0_mode1_reset, 167 .ring_get_wptr = psp_v10_0_ring_get_wptr, 168 .ring_set_wptr = psp_v10_0_ring_set_wptr, 169 }; 170 171 void psp_v10_0_set_psp_funcs(struct psp_context *psp) 172 { 173 psp->funcs = &psp_v10_0_funcs; 174 } 175