1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/slab.h> 25 #include <linux/module.h> 26 #include <linux/pci.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_atombios.h" 30 #include "amdgpu_ih.h" 31 #include "amdgpu_uvd.h" 32 #include "amdgpu_vce.h" 33 #include "amdgpu_ucode.h" 34 #include "amdgpu_psp.h" 35 #include "amdgpu_smu.h" 36 #include "atom.h" 37 #include "amd_pcie.h" 38 39 #include "gc/gc_10_1_0_offset.h" 40 #include "gc/gc_10_1_0_sh_mask.h" 41 #include "hdp/hdp_5_0_0_offset.h" 42 #include "hdp/hdp_5_0_0_sh_mask.h" 43 #include "smuio/smuio_11_0_0_offset.h" 44 #include "mp/mp_11_0_offset.h" 45 46 #include "soc15.h" 47 #include "soc15_common.h" 48 #include "gmc_v10_0.h" 49 #include "gfxhub_v2_0.h" 50 #include "mmhub_v2_0.h" 51 #include "nbio_v2_3.h" 52 #include "nv.h" 53 #include "navi10_ih.h" 54 #include "gfx_v10_0.h" 55 #include "sdma_v5_0.h" 56 #include "sdma_v5_2.h" 57 #include "vcn_v2_0.h" 58 #include "jpeg_v2_0.h" 59 #include "vcn_v3_0.h" 60 #include "jpeg_v3_0.h" 61 #include "dce_virtual.h" 62 #include "mes_v10_1.h" 63 #include "mxgpu_nv.h" 64 65 static const struct amd_ip_funcs nv_common_ip_funcs; 66 67 /* 68 * Indirect registers accessor 69 */ 70 static u32 nv_pcie_rreg(struct amdgpu_device *adev, u32 reg) 71 { 72 unsigned long address, data; 73 address = adev->nbio.funcs->get_pcie_index_offset(adev); 74 data = adev->nbio.funcs->get_pcie_data_offset(adev); 75 76 return amdgpu_device_indirect_rreg(adev, address, data, reg); 77 } 78 79 static void nv_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 80 { 81 unsigned long address, data; 82 83 address = adev->nbio.funcs->get_pcie_index_offset(adev); 84 data = adev->nbio.funcs->get_pcie_data_offset(adev); 85 86 amdgpu_device_indirect_wreg(adev, address, data, reg, v); 87 } 88 89 static u64 nv_pcie_rreg64(struct amdgpu_device *adev, u32 reg) 90 { 91 unsigned long address, data; 92 address = adev->nbio.funcs->get_pcie_index_offset(adev); 93 data = adev->nbio.funcs->get_pcie_data_offset(adev); 94 95 return amdgpu_device_indirect_rreg64(adev, address, data, reg); 96 } 97 98 static void nv_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v) 99 { 100 unsigned long address, data; 101 102 address = adev->nbio.funcs->get_pcie_index_offset(adev); 103 data = adev->nbio.funcs->get_pcie_data_offset(adev); 104 105 amdgpu_device_indirect_wreg64(adev, address, data, reg, v); 106 } 107 108 static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg) 109 { 110 unsigned long flags, address, data; 111 u32 r; 112 113 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 114 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 115 116 spin_lock_irqsave(&adev->didt_idx_lock, flags); 117 WREG32(address, (reg)); 118 r = RREG32(data); 119 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 120 return r; 121 } 122 123 static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 124 { 125 unsigned long flags, address, data; 126 127 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 128 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 129 130 spin_lock_irqsave(&adev->didt_idx_lock, flags); 131 WREG32(address, (reg)); 132 WREG32(data, (v)); 133 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 134 } 135 136 static u32 nv_get_config_memsize(struct amdgpu_device *adev) 137 { 138 return adev->nbio.funcs->get_memsize(adev); 139 } 140 141 static u32 nv_get_xclk(struct amdgpu_device *adev) 142 { 143 return adev->clock.spll.reference_freq; 144 } 145 146 147 void nv_grbm_select(struct amdgpu_device *adev, 148 u32 me, u32 pipe, u32 queue, u32 vmid) 149 { 150 u32 grbm_gfx_cntl = 0; 151 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); 152 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); 153 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); 154 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); 155 156 WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL), grbm_gfx_cntl); 157 } 158 159 static void nv_vga_set_state(struct amdgpu_device *adev, bool state) 160 { 161 /* todo */ 162 } 163 164 static bool nv_read_disabled_bios(struct amdgpu_device *adev) 165 { 166 /* todo */ 167 return false; 168 } 169 170 static bool nv_read_bios_from_rom(struct amdgpu_device *adev, 171 u8 *bios, u32 length_bytes) 172 { 173 u32 *dw_ptr; 174 u32 i, length_dw; 175 176 if (bios == NULL) 177 return false; 178 if (length_bytes == 0) 179 return false; 180 /* APU vbios image is part of sbios image */ 181 if (adev->flags & AMD_IS_APU) 182 return false; 183 184 dw_ptr = (u32 *)bios; 185 length_dw = ALIGN(length_bytes, 4) / 4; 186 187 /* set rom index to 0 */ 188 WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX), 0); 189 /* read out the rom data */ 190 for (i = 0; i < length_dw; i++) 191 dw_ptr[i] = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA)); 192 193 return true; 194 } 195 196 static struct soc15_allowed_register_entry nv_allowed_read_registers[] = { 197 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)}, 198 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)}, 199 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)}, 200 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)}, 201 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)}, 202 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)}, 203 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)}, 204 { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)}, 205 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)}, 206 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)}, 207 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)}, 208 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)}, 209 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)}, 210 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)}, 211 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)}, 212 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)}, 213 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)}, 214 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)}, 215 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)}, 216 }; 217 218 static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num, 219 u32 sh_num, u32 reg_offset) 220 { 221 uint32_t val; 222 223 mutex_lock(&adev->grbm_idx_mutex); 224 if (se_num != 0xffffffff || sh_num != 0xffffffff) 225 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); 226 227 val = RREG32(reg_offset); 228 229 if (se_num != 0xffffffff || sh_num != 0xffffffff) 230 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 231 mutex_unlock(&adev->grbm_idx_mutex); 232 return val; 233 } 234 235 static uint32_t nv_get_register_value(struct amdgpu_device *adev, 236 bool indexed, u32 se_num, 237 u32 sh_num, u32 reg_offset) 238 { 239 if (indexed) { 240 return nv_read_indexed_register(adev, se_num, sh_num, reg_offset); 241 } else { 242 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) 243 return adev->gfx.config.gb_addr_config; 244 return RREG32(reg_offset); 245 } 246 } 247 248 static int nv_read_register(struct amdgpu_device *adev, u32 se_num, 249 u32 sh_num, u32 reg_offset, u32 *value) 250 { 251 uint32_t i; 252 struct soc15_allowed_register_entry *en; 253 254 *value = 0; 255 for (i = 0; i < ARRAY_SIZE(nv_allowed_read_registers); i++) { 256 en = &nv_allowed_read_registers[i]; 257 if (reg_offset != 258 (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset)) 259 continue; 260 261 *value = nv_get_register_value(adev, 262 nv_allowed_read_registers[i].grbm_indexed, 263 se_num, sh_num, reg_offset); 264 return 0; 265 } 266 return -EINVAL; 267 } 268 269 static int nv_asic_mode1_reset(struct amdgpu_device *adev) 270 { 271 u32 i; 272 int ret = 0; 273 274 amdgpu_atombios_scratch_regs_engine_hung(adev, true); 275 276 /* disable BM */ 277 pci_clear_master(adev->pdev); 278 279 amdgpu_device_cache_pci_state(adev->pdev); 280 281 if (amdgpu_dpm_is_mode1_reset_supported(adev)) { 282 dev_info(adev->dev, "GPU smu mode1 reset\n"); 283 ret = amdgpu_dpm_mode1_reset(adev); 284 } else { 285 dev_info(adev->dev, "GPU psp mode1 reset\n"); 286 ret = psp_gpu_reset(adev); 287 } 288 289 if (ret) 290 dev_err(adev->dev, "GPU mode1 reset failed\n"); 291 amdgpu_device_load_pci_state(adev->pdev); 292 293 /* wait for asic to come out of reset */ 294 for (i = 0; i < adev->usec_timeout; i++) { 295 u32 memsize = adev->nbio.funcs->get_memsize(adev); 296 297 if (memsize != 0xffffffff) 298 break; 299 udelay(1); 300 } 301 302 amdgpu_atombios_scratch_regs_engine_hung(adev, false); 303 304 return ret; 305 } 306 307 static bool nv_asic_supports_baco(struct amdgpu_device *adev) 308 { 309 struct smu_context *smu = &adev->smu; 310 311 if (smu_baco_is_support(smu)) 312 return true; 313 else 314 return false; 315 } 316 317 static enum amd_reset_method 318 nv_asic_reset_method(struct amdgpu_device *adev) 319 { 320 struct smu_context *smu = &adev->smu; 321 322 if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 || 323 amdgpu_reset_method == AMD_RESET_METHOD_BACO) 324 return amdgpu_reset_method; 325 326 if (amdgpu_reset_method != -1) 327 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", 328 amdgpu_reset_method); 329 330 switch (adev->asic_type) { 331 case CHIP_SIENNA_CICHLID: 332 case CHIP_NAVY_FLOUNDER: 333 return AMD_RESET_METHOD_MODE1; 334 default: 335 if (smu_baco_is_support(smu)) 336 return AMD_RESET_METHOD_BACO; 337 else 338 return AMD_RESET_METHOD_MODE1; 339 } 340 } 341 342 static int nv_asic_reset(struct amdgpu_device *adev) 343 { 344 int ret = 0; 345 struct smu_context *smu = &adev->smu; 346 347 if (nv_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) { 348 dev_info(adev->dev, "BACO reset\n"); 349 350 ret = smu_baco_enter(smu); 351 if (ret) 352 return ret; 353 ret = smu_baco_exit(smu); 354 if (ret) 355 return ret; 356 } else { 357 dev_info(adev->dev, "MODE1 reset\n"); 358 ret = nv_asic_mode1_reset(adev); 359 } 360 361 return ret; 362 } 363 364 static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 365 { 366 /* todo */ 367 return 0; 368 } 369 370 static int nv_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 371 { 372 /* todo */ 373 return 0; 374 } 375 376 static void nv_pcie_gen3_enable(struct amdgpu_device *adev) 377 { 378 if (pci_is_root_bus(adev->pdev->bus)) 379 return; 380 381 if (amdgpu_pcie_gen2 == 0) 382 return; 383 384 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | 385 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3))) 386 return; 387 388 /* todo */ 389 } 390 391 static void nv_program_aspm(struct amdgpu_device *adev) 392 { 393 394 if (amdgpu_aspm == 0) 395 return; 396 397 /* todo */ 398 } 399 400 static void nv_enable_doorbell_aperture(struct amdgpu_device *adev, 401 bool enable) 402 { 403 adev->nbio.funcs->enable_doorbell_aperture(adev, enable); 404 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable); 405 } 406 407 static const struct amdgpu_ip_block_version nv_common_ip_block = 408 { 409 .type = AMD_IP_BLOCK_TYPE_COMMON, 410 .major = 1, 411 .minor = 0, 412 .rev = 0, 413 .funcs = &nv_common_ip_funcs, 414 }; 415 416 static int nv_reg_base_init(struct amdgpu_device *adev) 417 { 418 int r; 419 420 if (amdgpu_discovery) { 421 r = amdgpu_discovery_reg_base_init(adev); 422 if (r) { 423 DRM_WARN("failed to init reg base from ip discovery table, " 424 "fallback to legacy init method\n"); 425 goto legacy_init; 426 } 427 428 return 0; 429 } 430 431 legacy_init: 432 switch (adev->asic_type) { 433 case CHIP_NAVI10: 434 navi10_reg_base_init(adev); 435 break; 436 case CHIP_NAVI14: 437 navi14_reg_base_init(adev); 438 break; 439 case CHIP_NAVI12: 440 navi12_reg_base_init(adev); 441 break; 442 case CHIP_SIENNA_CICHLID: 443 case CHIP_NAVY_FLOUNDER: 444 sienna_cichlid_reg_base_init(adev); 445 break; 446 default: 447 return -EINVAL; 448 } 449 450 return 0; 451 } 452 453 void nv_set_virt_ops(struct amdgpu_device *adev) 454 { 455 adev->virt.ops = &xgpu_nv_virt_ops; 456 } 457 458 static bool nv_is_headless_sku(struct pci_dev *pdev) 459 { 460 if ((pdev->device == 0x731E && 461 (pdev->revision == 0xC6 || pdev->revision == 0xC7)) || 462 (pdev->device == 0x7340 && pdev->revision == 0xC9)) 463 return true; 464 return false; 465 } 466 467 int nv_set_ip_blocks(struct amdgpu_device *adev) 468 { 469 int r; 470 471 adev->nbio.funcs = &nbio_v2_3_funcs; 472 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg; 473 474 if (adev->asic_type == CHIP_SIENNA_CICHLID) 475 adev->gmc.xgmi.supported = true; 476 477 /* Set IP register base before any HW register access */ 478 r = nv_reg_base_init(adev); 479 if (r) 480 return r; 481 482 switch (adev->asic_type) { 483 case CHIP_NAVI10: 484 case CHIP_NAVI14: 485 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 486 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 487 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 488 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 489 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 490 !amdgpu_sriov_vf(adev)) 491 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 492 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 493 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 494 #if defined(CONFIG_DRM_AMD_DC) 495 else if (amdgpu_device_has_dc_support(adev) && 496 !nv_is_headless_sku(adev->pdev)) 497 amdgpu_device_ip_block_add(adev, &dm_ip_block); 498 #endif 499 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 500 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 501 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 502 !amdgpu_sriov_vf(adev)) 503 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 504 if (!nv_is_headless_sku(adev->pdev)) 505 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 506 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 507 if (adev->enable_mes) 508 amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block); 509 break; 510 case CHIP_NAVI12: 511 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 512 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 513 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 514 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 515 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 516 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 517 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 518 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 519 #if defined(CONFIG_DRM_AMD_DC) 520 else if (amdgpu_device_has_dc_support(adev)) 521 amdgpu_device_ip_block_add(adev, &dm_ip_block); 522 #endif 523 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 524 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 525 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 526 !amdgpu_sriov_vf(adev)) 527 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 528 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 529 if (!amdgpu_sriov_vf(adev)) 530 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 531 break; 532 case CHIP_SIENNA_CICHLID: 533 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 534 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 535 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 536 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 537 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 538 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 539 is_support_sw_smu(adev) && !amdgpu_sriov_vf(adev)) 540 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 541 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 542 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 543 #if defined(CONFIG_DRM_AMD_DC) 544 else if (amdgpu_device_has_dc_support(adev)) 545 amdgpu_device_ip_block_add(adev, &dm_ip_block); 546 #endif 547 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 548 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 549 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 550 if (!amdgpu_sriov_vf(adev)) 551 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 552 553 if (adev->enable_mes) 554 amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block); 555 break; 556 case CHIP_NAVY_FLOUNDER: 557 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 558 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 559 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 560 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 561 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 562 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 563 is_support_sw_smu(adev)) 564 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 565 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 566 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 567 #if defined(CONFIG_DRM_AMD_DC) 568 else if (amdgpu_device_has_dc_support(adev)) 569 amdgpu_device_ip_block_add(adev, &dm_ip_block); 570 #endif 571 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 572 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 573 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 574 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 575 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 576 is_support_sw_smu(adev)) 577 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 578 break; 579 default: 580 return -EINVAL; 581 } 582 583 return 0; 584 } 585 586 static uint32_t nv_get_rev_id(struct amdgpu_device *adev) 587 { 588 return adev->nbio.funcs->get_rev_id(adev); 589 } 590 591 static void nv_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring) 592 { 593 adev->nbio.funcs->hdp_flush(adev, ring); 594 } 595 596 static void nv_invalidate_hdp(struct amdgpu_device *adev, 597 struct amdgpu_ring *ring) 598 { 599 if (!ring || !ring->funcs->emit_wreg) { 600 WREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE, 1); 601 } else { 602 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET( 603 HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1); 604 } 605 } 606 607 static bool nv_need_full_reset(struct amdgpu_device *adev) 608 { 609 return true; 610 } 611 612 static bool nv_need_reset_on_init(struct amdgpu_device *adev) 613 { 614 u32 sol_reg; 615 616 if (adev->flags & AMD_IS_APU) 617 return false; 618 619 /* Check sOS sign of life register to confirm sys driver and sOS 620 * are already been loaded. 621 */ 622 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 623 if (sol_reg) 624 return true; 625 626 return false; 627 } 628 629 static uint64_t nv_get_pcie_replay_count(struct amdgpu_device *adev) 630 { 631 632 /* TODO 633 * dummy implement for pcie_replay_count sysfs interface 634 * */ 635 636 return 0; 637 } 638 639 static void nv_init_doorbell_index(struct amdgpu_device *adev) 640 { 641 adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ; 642 adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0; 643 adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1; 644 adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2; 645 adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3; 646 adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4; 647 adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5; 648 adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6; 649 adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7; 650 adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START; 651 adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END; 652 adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0; 653 adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1; 654 adev->doorbell_index.mes_ring = AMDGPU_NAVI10_DOORBELL_MES_RING; 655 adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0; 656 adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1; 657 adev->doorbell_index.sdma_engine[2] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2; 658 adev->doorbell_index.sdma_engine[3] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3; 659 adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH; 660 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1; 661 adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3; 662 adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5; 663 adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7; 664 adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP; 665 adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP; 666 667 adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1; 668 adev->doorbell_index.sdma_doorbell_range = 20; 669 } 670 671 static void nv_pre_asic_init(struct amdgpu_device *adev) 672 { 673 } 674 675 static const struct amdgpu_asic_funcs nv_asic_funcs = 676 { 677 .read_disabled_bios = &nv_read_disabled_bios, 678 .read_bios_from_rom = &nv_read_bios_from_rom, 679 .read_register = &nv_read_register, 680 .reset = &nv_asic_reset, 681 .reset_method = &nv_asic_reset_method, 682 .set_vga_state = &nv_vga_set_state, 683 .get_xclk = &nv_get_xclk, 684 .set_uvd_clocks = &nv_set_uvd_clocks, 685 .set_vce_clocks = &nv_set_vce_clocks, 686 .get_config_memsize = &nv_get_config_memsize, 687 .flush_hdp = &nv_flush_hdp, 688 .invalidate_hdp = &nv_invalidate_hdp, 689 .init_doorbell_index = &nv_init_doorbell_index, 690 .need_full_reset = &nv_need_full_reset, 691 .need_reset_on_init = &nv_need_reset_on_init, 692 .get_pcie_replay_count = &nv_get_pcie_replay_count, 693 .supports_baco = &nv_asic_supports_baco, 694 .pre_asic_init = &nv_pre_asic_init, 695 }; 696 697 static int nv_common_early_init(void *handle) 698 { 699 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE) 700 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 701 702 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; 703 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; 704 adev->smc_rreg = NULL; 705 adev->smc_wreg = NULL; 706 adev->pcie_rreg = &nv_pcie_rreg; 707 adev->pcie_wreg = &nv_pcie_wreg; 708 adev->pcie_rreg64 = &nv_pcie_rreg64; 709 adev->pcie_wreg64 = &nv_pcie_wreg64; 710 711 /* TODO: will add them during VCN v2 implementation */ 712 adev->uvd_ctx_rreg = NULL; 713 adev->uvd_ctx_wreg = NULL; 714 715 adev->didt_rreg = &nv_didt_rreg; 716 adev->didt_wreg = &nv_didt_wreg; 717 718 adev->asic_funcs = &nv_asic_funcs; 719 720 adev->rev_id = nv_get_rev_id(adev); 721 adev->external_rev_id = 0xff; 722 switch (adev->asic_type) { 723 case CHIP_NAVI10: 724 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 725 AMD_CG_SUPPORT_GFX_CGCG | 726 AMD_CG_SUPPORT_IH_CG | 727 AMD_CG_SUPPORT_HDP_MGCG | 728 AMD_CG_SUPPORT_HDP_LS | 729 AMD_CG_SUPPORT_SDMA_MGCG | 730 AMD_CG_SUPPORT_SDMA_LS | 731 AMD_CG_SUPPORT_MC_MGCG | 732 AMD_CG_SUPPORT_MC_LS | 733 AMD_CG_SUPPORT_ATHUB_MGCG | 734 AMD_CG_SUPPORT_ATHUB_LS | 735 AMD_CG_SUPPORT_VCN_MGCG | 736 AMD_CG_SUPPORT_JPEG_MGCG | 737 AMD_CG_SUPPORT_BIF_MGCG | 738 AMD_CG_SUPPORT_BIF_LS; 739 adev->pg_flags = AMD_PG_SUPPORT_VCN | 740 AMD_PG_SUPPORT_VCN_DPG | 741 AMD_PG_SUPPORT_JPEG | 742 AMD_PG_SUPPORT_ATHUB; 743 adev->external_rev_id = adev->rev_id + 0x1; 744 break; 745 case CHIP_NAVI14: 746 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 747 AMD_CG_SUPPORT_GFX_CGCG | 748 AMD_CG_SUPPORT_IH_CG | 749 AMD_CG_SUPPORT_HDP_MGCG | 750 AMD_CG_SUPPORT_HDP_LS | 751 AMD_CG_SUPPORT_SDMA_MGCG | 752 AMD_CG_SUPPORT_SDMA_LS | 753 AMD_CG_SUPPORT_MC_MGCG | 754 AMD_CG_SUPPORT_MC_LS | 755 AMD_CG_SUPPORT_ATHUB_MGCG | 756 AMD_CG_SUPPORT_ATHUB_LS | 757 AMD_CG_SUPPORT_VCN_MGCG | 758 AMD_CG_SUPPORT_JPEG_MGCG | 759 AMD_CG_SUPPORT_BIF_MGCG | 760 AMD_CG_SUPPORT_BIF_LS; 761 adev->pg_flags = AMD_PG_SUPPORT_VCN | 762 AMD_PG_SUPPORT_JPEG | 763 AMD_PG_SUPPORT_VCN_DPG; 764 adev->external_rev_id = adev->rev_id + 20; 765 break; 766 case CHIP_NAVI12: 767 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 768 AMD_CG_SUPPORT_GFX_MGLS | 769 AMD_CG_SUPPORT_GFX_CGCG | 770 AMD_CG_SUPPORT_GFX_CP_LS | 771 AMD_CG_SUPPORT_GFX_RLC_LS | 772 AMD_CG_SUPPORT_IH_CG | 773 AMD_CG_SUPPORT_HDP_MGCG | 774 AMD_CG_SUPPORT_HDP_LS | 775 AMD_CG_SUPPORT_SDMA_MGCG | 776 AMD_CG_SUPPORT_SDMA_LS | 777 AMD_CG_SUPPORT_MC_MGCG | 778 AMD_CG_SUPPORT_MC_LS | 779 AMD_CG_SUPPORT_ATHUB_MGCG | 780 AMD_CG_SUPPORT_ATHUB_LS | 781 AMD_CG_SUPPORT_VCN_MGCG | 782 AMD_CG_SUPPORT_JPEG_MGCG; 783 adev->pg_flags = AMD_PG_SUPPORT_VCN | 784 AMD_PG_SUPPORT_VCN_DPG | 785 AMD_PG_SUPPORT_JPEG | 786 AMD_PG_SUPPORT_ATHUB; 787 /* guest vm gets 0xffffffff when reading RCC_DEV0_EPF0_STRAP0, 788 * as a consequence, the rev_id and external_rev_id are wrong. 789 * workaround it by hardcoding rev_id to 0 (default value). 790 */ 791 if (amdgpu_sriov_vf(adev)) 792 adev->rev_id = 0; 793 adev->external_rev_id = adev->rev_id + 0xa; 794 break; 795 case CHIP_SIENNA_CICHLID: 796 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 797 AMD_CG_SUPPORT_GFX_CGCG | 798 AMD_CG_SUPPORT_GFX_3D_CGCG | 799 AMD_CG_SUPPORT_MC_MGCG | 800 AMD_CG_SUPPORT_VCN_MGCG | 801 AMD_CG_SUPPORT_JPEG_MGCG | 802 AMD_CG_SUPPORT_HDP_MGCG | 803 AMD_CG_SUPPORT_HDP_LS | 804 AMD_CG_SUPPORT_IH_CG | 805 AMD_CG_SUPPORT_MC_LS; 806 adev->pg_flags = AMD_PG_SUPPORT_VCN | 807 AMD_PG_SUPPORT_VCN_DPG | 808 AMD_PG_SUPPORT_JPEG | 809 AMD_PG_SUPPORT_ATHUB | 810 AMD_PG_SUPPORT_MMHUB; 811 if (amdgpu_sriov_vf(adev)) { 812 /* hypervisor control CG and PG enablement */ 813 adev->cg_flags = 0; 814 adev->pg_flags = 0; 815 } 816 adev->external_rev_id = adev->rev_id + 0x28; 817 break; 818 case CHIP_NAVY_FLOUNDER: 819 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 820 AMD_CG_SUPPORT_GFX_CGCG | 821 AMD_CG_SUPPORT_GFX_3D_CGCG | 822 AMD_CG_SUPPORT_VCN_MGCG | 823 AMD_CG_SUPPORT_JPEG_MGCG | 824 AMD_CG_SUPPORT_MC_MGCG | 825 AMD_CG_SUPPORT_MC_LS | 826 AMD_CG_SUPPORT_HDP_MGCG | 827 AMD_CG_SUPPORT_HDP_LS | 828 AMD_CG_SUPPORT_IH_CG; 829 adev->pg_flags = AMD_PG_SUPPORT_VCN | 830 AMD_PG_SUPPORT_VCN_DPG | 831 AMD_PG_SUPPORT_JPEG | 832 AMD_PG_SUPPORT_ATHUB | 833 AMD_PG_SUPPORT_MMHUB; 834 adev->external_rev_id = adev->rev_id + 0x32; 835 break; 836 837 default: 838 /* FIXME: not supported yet */ 839 return -EINVAL; 840 } 841 842 if (amdgpu_sriov_vf(adev)) { 843 amdgpu_virt_init_setting(adev); 844 xgpu_nv_mailbox_set_irq_funcs(adev); 845 } 846 847 return 0; 848 } 849 850 static int nv_common_late_init(void *handle) 851 { 852 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 853 854 if (amdgpu_sriov_vf(adev)) 855 xgpu_nv_mailbox_get_irq(adev); 856 857 return 0; 858 } 859 860 static int nv_common_sw_init(void *handle) 861 { 862 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 863 864 if (amdgpu_sriov_vf(adev)) 865 xgpu_nv_mailbox_add_irq_id(adev); 866 867 return 0; 868 } 869 870 static int nv_common_sw_fini(void *handle) 871 { 872 return 0; 873 } 874 875 static int nv_common_hw_init(void *handle) 876 { 877 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 878 879 /* enable pcie gen2/3 link */ 880 nv_pcie_gen3_enable(adev); 881 /* enable aspm */ 882 nv_program_aspm(adev); 883 /* setup nbio registers */ 884 adev->nbio.funcs->init_registers(adev); 885 /* remap HDP registers to a hole in mmio space, 886 * for the purpose of expose those registers 887 * to process space 888 */ 889 if (adev->nbio.funcs->remap_hdp_registers) 890 adev->nbio.funcs->remap_hdp_registers(adev); 891 /* enable the doorbell aperture */ 892 nv_enable_doorbell_aperture(adev, true); 893 894 return 0; 895 } 896 897 static int nv_common_hw_fini(void *handle) 898 { 899 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 900 901 /* disable the doorbell aperture */ 902 nv_enable_doorbell_aperture(adev, false); 903 904 return 0; 905 } 906 907 static int nv_common_suspend(void *handle) 908 { 909 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 910 911 return nv_common_hw_fini(adev); 912 } 913 914 static int nv_common_resume(void *handle) 915 { 916 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 917 918 return nv_common_hw_init(adev); 919 } 920 921 static bool nv_common_is_idle(void *handle) 922 { 923 return true; 924 } 925 926 static int nv_common_wait_for_idle(void *handle) 927 { 928 return 0; 929 } 930 931 static int nv_common_soft_reset(void *handle) 932 { 933 return 0; 934 } 935 936 static void nv_update_hdp_mem_power_gating(struct amdgpu_device *adev, 937 bool enable) 938 { 939 uint32_t hdp_clk_cntl, hdp_clk_cntl1; 940 uint32_t hdp_mem_pwr_cntl; 941 942 if (!(adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | 943 AMD_CG_SUPPORT_HDP_DS | 944 AMD_CG_SUPPORT_HDP_SD))) 945 return; 946 947 hdp_clk_cntl = hdp_clk_cntl1 = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); 948 hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL); 949 950 /* Before doing clock/power mode switch, 951 * forced on IPH & RC clock */ 952 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL, 953 IPH_MEM_CLK_SOFT_OVERRIDE, 1); 954 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL, 955 RC_MEM_CLK_SOFT_OVERRIDE, 1); 956 WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl); 957 958 /* HDP 5.0 doesn't support dynamic power mode switch, 959 * disable clock and power gating before any changing */ 960 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 961 IPH_MEM_POWER_CTRL_EN, 0); 962 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 963 IPH_MEM_POWER_LS_EN, 0); 964 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 965 IPH_MEM_POWER_DS_EN, 0); 966 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 967 IPH_MEM_POWER_SD_EN, 0); 968 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 969 RC_MEM_POWER_CTRL_EN, 0); 970 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 971 RC_MEM_POWER_LS_EN, 0); 972 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 973 RC_MEM_POWER_DS_EN, 0); 974 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 975 RC_MEM_POWER_SD_EN, 0); 976 WREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); 977 978 /* only one clock gating mode (LS/DS/SD) can be enabled */ 979 if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) { 980 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 981 HDP_MEM_POWER_CTRL, 982 IPH_MEM_POWER_LS_EN, enable); 983 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 984 HDP_MEM_POWER_CTRL, 985 RC_MEM_POWER_LS_EN, enable); 986 } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_DS) { 987 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 988 HDP_MEM_POWER_CTRL, 989 IPH_MEM_POWER_DS_EN, enable); 990 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 991 HDP_MEM_POWER_CTRL, 992 RC_MEM_POWER_DS_EN, enable); 993 } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_SD) { 994 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 995 HDP_MEM_POWER_CTRL, 996 IPH_MEM_POWER_SD_EN, enable); 997 /* RC should not use shut down mode, fallback to ds */ 998 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 999 HDP_MEM_POWER_CTRL, 1000 RC_MEM_POWER_DS_EN, enable); 1001 } 1002 1003 /* confirmed that IPH_MEM_POWER_CTRL_EN and RC_MEM_POWER_CTRL_EN have to 1004 * be set for SRAM LS/DS/SD */ 1005 if (adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_DS | 1006 AMD_CG_SUPPORT_HDP_SD)) { 1007 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 1008 IPH_MEM_POWER_CTRL_EN, 1); 1009 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 1010 RC_MEM_POWER_CTRL_EN, 1); 1011 } 1012 1013 WREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); 1014 1015 /* restore IPH & RC clock override after clock/power mode changing */ 1016 WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl1); 1017 } 1018 1019 static void nv_update_hdp_clock_gating(struct amdgpu_device *adev, 1020 bool enable) 1021 { 1022 uint32_t hdp_clk_cntl; 1023 1024 if (!(adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG)) 1025 return; 1026 1027 hdp_clk_cntl = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); 1028 1029 if (enable) { 1030 hdp_clk_cntl &= 1031 ~(uint32_t) 1032 (HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK | 1033 HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK | 1034 HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK | 1035 HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK | 1036 HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK | 1037 HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK); 1038 } else { 1039 hdp_clk_cntl |= HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK | 1040 HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK | 1041 HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK | 1042 HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK | 1043 HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK | 1044 HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK; 1045 } 1046 1047 WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl); 1048 } 1049 1050 static int nv_common_set_clockgating_state(void *handle, 1051 enum amd_clockgating_state state) 1052 { 1053 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1054 1055 if (amdgpu_sriov_vf(adev)) 1056 return 0; 1057 1058 switch (adev->asic_type) { 1059 case CHIP_NAVI10: 1060 case CHIP_NAVI14: 1061 case CHIP_NAVI12: 1062 case CHIP_SIENNA_CICHLID: 1063 case CHIP_NAVY_FLOUNDER: 1064 adev->nbio.funcs->update_medium_grain_clock_gating(adev, 1065 state == AMD_CG_STATE_GATE); 1066 adev->nbio.funcs->update_medium_grain_light_sleep(adev, 1067 state == AMD_CG_STATE_GATE); 1068 nv_update_hdp_mem_power_gating(adev, 1069 state == AMD_CG_STATE_GATE); 1070 nv_update_hdp_clock_gating(adev, 1071 state == AMD_CG_STATE_GATE); 1072 break; 1073 default: 1074 break; 1075 } 1076 return 0; 1077 } 1078 1079 static int nv_common_set_powergating_state(void *handle, 1080 enum amd_powergating_state state) 1081 { 1082 /* TODO */ 1083 return 0; 1084 } 1085 1086 static void nv_common_get_clockgating_state(void *handle, u32 *flags) 1087 { 1088 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1089 uint32_t tmp; 1090 1091 if (amdgpu_sriov_vf(adev)) 1092 *flags = 0; 1093 1094 adev->nbio.funcs->get_clockgating_state(adev, flags); 1095 1096 /* AMD_CG_SUPPORT_HDP_MGCG */ 1097 tmp = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); 1098 if (!(tmp & (HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK | 1099 HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK | 1100 HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK | 1101 HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK | 1102 HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK | 1103 HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK))) 1104 *flags |= AMD_CG_SUPPORT_HDP_MGCG; 1105 1106 /* AMD_CG_SUPPORT_HDP_LS/DS/SD */ 1107 tmp = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL); 1108 if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK) 1109 *flags |= AMD_CG_SUPPORT_HDP_LS; 1110 else if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_DS_EN_MASK) 1111 *flags |= AMD_CG_SUPPORT_HDP_DS; 1112 else if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_SD_EN_MASK) 1113 *flags |= AMD_CG_SUPPORT_HDP_SD; 1114 1115 return; 1116 } 1117 1118 static const struct amd_ip_funcs nv_common_ip_funcs = { 1119 .name = "nv_common", 1120 .early_init = nv_common_early_init, 1121 .late_init = nv_common_late_init, 1122 .sw_init = nv_common_sw_init, 1123 .sw_fini = nv_common_sw_fini, 1124 .hw_init = nv_common_hw_init, 1125 .hw_fini = nv_common_hw_fini, 1126 .suspend = nv_common_suspend, 1127 .resume = nv_common_resume, 1128 .is_idle = nv_common_is_idle, 1129 .wait_for_idle = nv_common_wait_for_idle, 1130 .soft_reset = nv_common_soft_reset, 1131 .set_clockgating_state = nv_common_set_clockgating_state, 1132 .set_powergating_state = nv_common_set_powergating_state, 1133 .get_clockgating_state = nv_common_get_clockgating_state, 1134 }; 1135