1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/slab.h> 25 #include <linux/module.h> 26 #include <linux/pci.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_atombios.h" 30 #include "amdgpu_ih.h" 31 #include "amdgpu_uvd.h" 32 #include "amdgpu_vce.h" 33 #include "amdgpu_ucode.h" 34 #include "amdgpu_psp.h" 35 #include "amdgpu_smu.h" 36 #include "atom.h" 37 #include "amd_pcie.h" 38 39 #include "gc/gc_10_1_0_offset.h" 40 #include "gc/gc_10_1_0_sh_mask.h" 41 #include "hdp/hdp_5_0_0_offset.h" 42 #include "hdp/hdp_5_0_0_sh_mask.h" 43 44 #include "soc15.h" 45 #include "soc15_common.h" 46 #include "gmc_v10_0.h" 47 #include "gfxhub_v2_0.h" 48 #include "mmhub_v2_0.h" 49 #include "nbio_v2_3.h" 50 #include "nv.h" 51 #include "navi10_ih.h" 52 #include "gfx_v10_0.h" 53 #include "sdma_v5_0.h" 54 #include "vcn_v2_0.h" 55 #include "dce_virtual.h" 56 #include "mes_v10_1.h" 57 #include "mxgpu_nv.h" 58 59 static const struct amd_ip_funcs nv_common_ip_funcs; 60 61 /* 62 * Indirect registers accessor 63 */ 64 static u32 nv_pcie_rreg(struct amdgpu_device *adev, u32 reg) 65 { 66 unsigned long flags, address, data; 67 u32 r; 68 address = adev->nbio.funcs->get_pcie_index_offset(adev); 69 data = adev->nbio.funcs->get_pcie_data_offset(adev); 70 71 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 72 WREG32(address, reg); 73 (void)RREG32(address); 74 r = RREG32(data); 75 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 76 return r; 77 } 78 79 static void nv_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 80 { 81 unsigned long flags, address, data; 82 83 address = adev->nbio.funcs->get_pcie_index_offset(adev); 84 data = adev->nbio.funcs->get_pcie_data_offset(adev); 85 86 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 87 WREG32(address, reg); 88 (void)RREG32(address); 89 WREG32(data, v); 90 (void)RREG32(data); 91 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 92 } 93 94 static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg) 95 { 96 unsigned long flags, address, data; 97 u32 r; 98 99 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 100 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 101 102 spin_lock_irqsave(&adev->didt_idx_lock, flags); 103 WREG32(address, (reg)); 104 r = RREG32(data); 105 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 106 return r; 107 } 108 109 static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 110 { 111 unsigned long flags, address, data; 112 113 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 114 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 115 116 spin_lock_irqsave(&adev->didt_idx_lock, flags); 117 WREG32(address, (reg)); 118 WREG32(data, (v)); 119 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 120 } 121 122 static u32 nv_get_config_memsize(struct amdgpu_device *adev) 123 { 124 return adev->nbio.funcs->get_memsize(adev); 125 } 126 127 static u32 nv_get_xclk(struct amdgpu_device *adev) 128 { 129 return adev->clock.spll.reference_freq; 130 } 131 132 133 void nv_grbm_select(struct amdgpu_device *adev, 134 u32 me, u32 pipe, u32 queue, u32 vmid) 135 { 136 u32 grbm_gfx_cntl = 0; 137 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); 138 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); 139 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); 140 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); 141 142 WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL), grbm_gfx_cntl); 143 } 144 145 static void nv_vga_set_state(struct amdgpu_device *adev, bool state) 146 { 147 /* todo */ 148 } 149 150 static bool nv_read_disabled_bios(struct amdgpu_device *adev) 151 { 152 /* todo */ 153 return false; 154 } 155 156 static bool nv_read_bios_from_rom(struct amdgpu_device *adev, 157 u8 *bios, u32 length_bytes) 158 { 159 /* TODO: will implement it when SMU header is available */ 160 return false; 161 } 162 163 static struct soc15_allowed_register_entry nv_allowed_read_registers[] = { 164 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)}, 165 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)}, 166 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)}, 167 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)}, 168 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)}, 169 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)}, 170 #if 0 /* TODO: will set it when SDMA header is available */ 171 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)}, 172 { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)}, 173 #endif 174 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)}, 175 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)}, 176 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)}, 177 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)}, 178 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)}, 179 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)}, 180 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)}, 181 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)}, 182 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)}, 183 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)}, 184 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)}, 185 }; 186 187 static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num, 188 u32 sh_num, u32 reg_offset) 189 { 190 uint32_t val; 191 192 mutex_lock(&adev->grbm_idx_mutex); 193 if (se_num != 0xffffffff || sh_num != 0xffffffff) 194 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); 195 196 val = RREG32(reg_offset); 197 198 if (se_num != 0xffffffff || sh_num != 0xffffffff) 199 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 200 mutex_unlock(&adev->grbm_idx_mutex); 201 return val; 202 } 203 204 static uint32_t nv_get_register_value(struct amdgpu_device *adev, 205 bool indexed, u32 se_num, 206 u32 sh_num, u32 reg_offset) 207 { 208 if (indexed) { 209 return nv_read_indexed_register(adev, se_num, sh_num, reg_offset); 210 } else { 211 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) 212 return adev->gfx.config.gb_addr_config; 213 return RREG32(reg_offset); 214 } 215 } 216 217 static int nv_read_register(struct amdgpu_device *adev, u32 se_num, 218 u32 sh_num, u32 reg_offset, u32 *value) 219 { 220 uint32_t i; 221 struct soc15_allowed_register_entry *en; 222 223 *value = 0; 224 for (i = 0; i < ARRAY_SIZE(nv_allowed_read_registers); i++) { 225 en = &nv_allowed_read_registers[i]; 226 if (reg_offset != 227 (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset)) 228 continue; 229 230 *value = nv_get_register_value(adev, 231 nv_allowed_read_registers[i].grbm_indexed, 232 se_num, sh_num, reg_offset); 233 return 0; 234 } 235 return -EINVAL; 236 } 237 238 #if 0 239 static void nv_gpu_pci_config_reset(struct amdgpu_device *adev) 240 { 241 u32 i; 242 243 dev_info(adev->dev, "GPU pci config reset\n"); 244 245 /* disable BM */ 246 pci_clear_master(adev->pdev); 247 /* reset */ 248 amdgpu_pci_config_reset(adev); 249 250 udelay(100); 251 252 /* wait for asic to come out of reset */ 253 for (i = 0; i < adev->usec_timeout; i++) { 254 u32 memsize = nbio_v2_3_get_memsize(adev); 255 if (memsize != 0xffffffff) 256 break; 257 udelay(1); 258 } 259 260 } 261 #endif 262 263 static int nv_asic_mode1_reset(struct amdgpu_device *adev) 264 { 265 u32 i; 266 int ret = 0; 267 268 amdgpu_atombios_scratch_regs_engine_hung(adev, true); 269 270 dev_info(adev->dev, "GPU mode1 reset\n"); 271 272 /* disable BM */ 273 pci_clear_master(adev->pdev); 274 275 pci_save_state(adev->pdev); 276 277 ret = psp_gpu_reset(adev); 278 if (ret) 279 dev_err(adev->dev, "GPU mode1 reset failed\n"); 280 281 pci_restore_state(adev->pdev); 282 283 /* wait for asic to come out of reset */ 284 for (i = 0; i < adev->usec_timeout; i++) { 285 u32 memsize = adev->nbio.funcs->get_memsize(adev); 286 287 if (memsize != 0xffffffff) 288 break; 289 udelay(1); 290 } 291 292 amdgpu_atombios_scratch_regs_engine_hung(adev, false); 293 294 return ret; 295 } 296 297 static enum amd_reset_method 298 nv_asic_reset_method(struct amdgpu_device *adev) 299 { 300 struct smu_context *smu = &adev->smu; 301 302 if (!amdgpu_sriov_vf(adev) && smu_baco_is_support(smu)) 303 return AMD_RESET_METHOD_BACO; 304 else 305 return AMD_RESET_METHOD_MODE1; 306 } 307 308 static int nv_asic_reset(struct amdgpu_device *adev) 309 { 310 311 /* FIXME: it doesn't work since vega10 */ 312 #if 0 313 amdgpu_atombios_scratch_regs_engine_hung(adev, true); 314 315 nv_gpu_pci_config_reset(adev); 316 317 amdgpu_atombios_scratch_regs_engine_hung(adev, false); 318 #endif 319 int ret = 0; 320 struct smu_context *smu = &adev->smu; 321 322 if (nv_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) { 323 if (!adev->in_suspend) 324 amdgpu_inc_vram_lost(adev); 325 ret = smu_baco_reset(smu); 326 } else { 327 if (!adev->in_suspend) 328 amdgpu_inc_vram_lost(adev); 329 ret = nv_asic_mode1_reset(adev); 330 } 331 332 return ret; 333 } 334 335 static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 336 { 337 /* todo */ 338 return 0; 339 } 340 341 static int nv_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 342 { 343 /* todo */ 344 return 0; 345 } 346 347 static void nv_pcie_gen3_enable(struct amdgpu_device *adev) 348 { 349 if (pci_is_root_bus(adev->pdev->bus)) 350 return; 351 352 if (amdgpu_pcie_gen2 == 0) 353 return; 354 355 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | 356 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3))) 357 return; 358 359 /* todo */ 360 } 361 362 static void nv_program_aspm(struct amdgpu_device *adev) 363 { 364 365 if (amdgpu_aspm == 0) 366 return; 367 368 /* todo */ 369 } 370 371 static void nv_enable_doorbell_aperture(struct amdgpu_device *adev, 372 bool enable) 373 { 374 adev->nbio.funcs->enable_doorbell_aperture(adev, enable); 375 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable); 376 } 377 378 static const struct amdgpu_ip_block_version nv_common_ip_block = 379 { 380 .type = AMD_IP_BLOCK_TYPE_COMMON, 381 .major = 1, 382 .minor = 0, 383 .rev = 0, 384 .funcs = &nv_common_ip_funcs, 385 }; 386 387 static int nv_reg_base_init(struct amdgpu_device *adev) 388 { 389 int r; 390 391 if (amdgpu_discovery) { 392 r = amdgpu_discovery_reg_base_init(adev); 393 if (r) { 394 DRM_WARN("failed to init reg base from ip discovery table, " 395 "fallback to legacy init method\n"); 396 goto legacy_init; 397 } 398 399 return 0; 400 } 401 402 legacy_init: 403 switch (adev->asic_type) { 404 case CHIP_NAVI10: 405 navi10_reg_base_init(adev); 406 break; 407 case CHIP_NAVI14: 408 navi14_reg_base_init(adev); 409 break; 410 case CHIP_NAVI12: 411 navi12_reg_base_init(adev); 412 break; 413 default: 414 return -EINVAL; 415 } 416 417 return 0; 418 } 419 420 int nv_set_ip_blocks(struct amdgpu_device *adev) 421 { 422 int r; 423 424 /* Set IP register base before any HW register access */ 425 r = nv_reg_base_init(adev); 426 if (r) 427 return r; 428 429 adev->nbio.funcs = &nbio_v2_3_funcs; 430 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg; 431 432 adev->nbio.funcs->detect_hw_virt(adev); 433 434 if (amdgpu_sriov_vf(adev)) 435 adev->virt.ops = &xgpu_nv_virt_ops; 436 437 switch (adev->asic_type) { 438 case CHIP_NAVI10: 439 case CHIP_NAVI14: 440 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 441 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 442 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 443 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 444 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 445 is_support_sw_smu(adev) && !amdgpu_sriov_vf(adev)) 446 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 447 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 448 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 449 #if defined(CONFIG_DRM_AMD_DC) 450 else if (amdgpu_device_has_dc_support(adev)) 451 amdgpu_device_ip_block_add(adev, &dm_ip_block); 452 #endif 453 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 454 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 455 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 456 is_support_sw_smu(adev) && !amdgpu_sriov_vf(adev)) 457 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 458 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 459 if (adev->enable_mes) 460 amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block); 461 break; 462 case CHIP_NAVI12: 463 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 464 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 465 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 466 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 467 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 468 is_support_sw_smu(adev) && !amdgpu_sriov_vf(adev)) 469 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 470 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 471 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 472 #if defined(CONFIG_DRM_AMD_DC) 473 else if (amdgpu_device_has_dc_support(adev)) 474 amdgpu_device_ip_block_add(adev, &dm_ip_block); 475 #endif 476 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 477 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 478 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 479 is_support_sw_smu(adev) && !amdgpu_sriov_vf(adev)) 480 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 481 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 482 break; 483 default: 484 return -EINVAL; 485 } 486 487 return 0; 488 } 489 490 static uint32_t nv_get_rev_id(struct amdgpu_device *adev) 491 { 492 return adev->nbio.funcs->get_rev_id(adev); 493 } 494 495 static void nv_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring) 496 { 497 adev->nbio.funcs->hdp_flush(adev, ring); 498 } 499 500 static void nv_invalidate_hdp(struct amdgpu_device *adev, 501 struct amdgpu_ring *ring) 502 { 503 if (!ring || !ring->funcs->emit_wreg) { 504 WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_READ_CACHE_INVALIDATE, 1); 505 } else { 506 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET( 507 HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1); 508 } 509 } 510 511 static bool nv_need_full_reset(struct amdgpu_device *adev) 512 { 513 return true; 514 } 515 516 static void nv_get_pcie_usage(struct amdgpu_device *adev, 517 uint64_t *count0, 518 uint64_t *count1) 519 { 520 /*TODO*/ 521 } 522 523 static bool nv_need_reset_on_init(struct amdgpu_device *adev) 524 { 525 #if 0 526 u32 sol_reg; 527 528 if (adev->flags & AMD_IS_APU) 529 return false; 530 531 /* Check sOS sign of life register to confirm sys driver and sOS 532 * are already been loaded. 533 */ 534 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 535 if (sol_reg) 536 return true; 537 #endif 538 /* TODO: re-enable it when mode1 reset is functional */ 539 return false; 540 } 541 542 static uint64_t nv_get_pcie_replay_count(struct amdgpu_device *adev) 543 { 544 545 /* TODO 546 * dummy implement for pcie_replay_count sysfs interface 547 * */ 548 549 return 0; 550 } 551 552 static void nv_init_doorbell_index(struct amdgpu_device *adev) 553 { 554 adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ; 555 adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0; 556 adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1; 557 adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2; 558 adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3; 559 adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4; 560 adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5; 561 adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6; 562 adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7; 563 adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START; 564 adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END; 565 adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0; 566 adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1; 567 adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0; 568 adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1; 569 adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH; 570 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1; 571 adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3; 572 adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5; 573 adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7; 574 adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP; 575 adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP; 576 577 adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1; 578 adev->doorbell_index.sdma_doorbell_range = 20; 579 } 580 581 static const struct amdgpu_asic_funcs nv_asic_funcs = 582 { 583 .read_disabled_bios = &nv_read_disabled_bios, 584 .read_bios_from_rom = &nv_read_bios_from_rom, 585 .read_register = &nv_read_register, 586 .reset = &nv_asic_reset, 587 .reset_method = &nv_asic_reset_method, 588 .set_vga_state = &nv_vga_set_state, 589 .get_xclk = &nv_get_xclk, 590 .set_uvd_clocks = &nv_set_uvd_clocks, 591 .set_vce_clocks = &nv_set_vce_clocks, 592 .get_config_memsize = &nv_get_config_memsize, 593 .flush_hdp = &nv_flush_hdp, 594 .invalidate_hdp = &nv_invalidate_hdp, 595 .init_doorbell_index = &nv_init_doorbell_index, 596 .need_full_reset = &nv_need_full_reset, 597 .get_pcie_usage = &nv_get_pcie_usage, 598 .need_reset_on_init = &nv_need_reset_on_init, 599 .get_pcie_replay_count = &nv_get_pcie_replay_count, 600 }; 601 602 static int nv_common_early_init(void *handle) 603 { 604 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE) 605 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 606 607 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; 608 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; 609 adev->smc_rreg = NULL; 610 adev->smc_wreg = NULL; 611 adev->pcie_rreg = &nv_pcie_rreg; 612 adev->pcie_wreg = &nv_pcie_wreg; 613 614 /* TODO: will add them during VCN v2 implementation */ 615 adev->uvd_ctx_rreg = NULL; 616 adev->uvd_ctx_wreg = NULL; 617 618 adev->didt_rreg = &nv_didt_rreg; 619 adev->didt_wreg = &nv_didt_wreg; 620 621 adev->asic_funcs = &nv_asic_funcs; 622 623 adev->rev_id = nv_get_rev_id(adev); 624 adev->external_rev_id = 0xff; 625 switch (adev->asic_type) { 626 case CHIP_NAVI10: 627 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 628 AMD_CG_SUPPORT_GFX_CGCG | 629 AMD_CG_SUPPORT_IH_CG | 630 AMD_CG_SUPPORT_HDP_MGCG | 631 AMD_CG_SUPPORT_HDP_LS | 632 AMD_CG_SUPPORT_SDMA_MGCG | 633 AMD_CG_SUPPORT_SDMA_LS | 634 AMD_CG_SUPPORT_MC_MGCG | 635 AMD_CG_SUPPORT_MC_LS | 636 AMD_CG_SUPPORT_ATHUB_MGCG | 637 AMD_CG_SUPPORT_ATHUB_LS | 638 AMD_CG_SUPPORT_VCN_MGCG | 639 AMD_CG_SUPPORT_BIF_MGCG | 640 AMD_CG_SUPPORT_BIF_LS; 641 adev->pg_flags = AMD_PG_SUPPORT_VCN | 642 AMD_PG_SUPPORT_VCN_DPG | 643 AMD_PG_SUPPORT_ATHUB; 644 adev->external_rev_id = adev->rev_id + 0x1; 645 break; 646 case CHIP_NAVI14: 647 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 648 AMD_CG_SUPPORT_GFX_CGCG | 649 AMD_CG_SUPPORT_IH_CG | 650 AMD_CG_SUPPORT_HDP_MGCG | 651 AMD_CG_SUPPORT_HDP_LS | 652 AMD_CG_SUPPORT_SDMA_MGCG | 653 AMD_CG_SUPPORT_SDMA_LS | 654 AMD_CG_SUPPORT_MC_MGCG | 655 AMD_CG_SUPPORT_MC_LS | 656 AMD_CG_SUPPORT_ATHUB_MGCG | 657 AMD_CG_SUPPORT_ATHUB_LS | 658 AMD_CG_SUPPORT_VCN_MGCG | 659 AMD_CG_SUPPORT_BIF_MGCG | 660 AMD_CG_SUPPORT_BIF_LS; 661 adev->pg_flags = AMD_PG_SUPPORT_VCN | 662 AMD_PG_SUPPORT_VCN_DPG; 663 adev->external_rev_id = adev->rev_id + 20; 664 break; 665 case CHIP_NAVI12: 666 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 667 AMD_CG_SUPPORT_GFX_MGLS | 668 AMD_CG_SUPPORT_GFX_CGCG | 669 AMD_CG_SUPPORT_GFX_CP_LS | 670 AMD_CG_SUPPORT_GFX_RLC_LS | 671 AMD_CG_SUPPORT_IH_CG | 672 AMD_CG_SUPPORT_HDP_MGCG | 673 AMD_CG_SUPPORT_HDP_LS | 674 AMD_CG_SUPPORT_SDMA_MGCG | 675 AMD_CG_SUPPORT_SDMA_LS | 676 AMD_CG_SUPPORT_MC_MGCG | 677 AMD_CG_SUPPORT_MC_LS | 678 AMD_CG_SUPPORT_ATHUB_MGCG | 679 AMD_CG_SUPPORT_ATHUB_LS | 680 AMD_CG_SUPPORT_VCN_MGCG; 681 adev->pg_flags = AMD_PG_SUPPORT_VCN | 682 AMD_PG_SUPPORT_VCN_DPG | 683 AMD_PG_SUPPORT_ATHUB; 684 adev->external_rev_id = adev->rev_id + 0xa; 685 break; 686 default: 687 /* FIXME: not supported yet */ 688 return -EINVAL; 689 } 690 691 if (amdgpu_sriov_vf(adev)) { 692 amdgpu_virt_init_setting(adev); 693 xgpu_nv_mailbox_set_irq_funcs(adev); 694 } 695 696 return 0; 697 } 698 699 static int nv_common_late_init(void *handle) 700 { 701 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 702 703 if (amdgpu_sriov_vf(adev)) 704 xgpu_nv_mailbox_get_irq(adev); 705 706 return 0; 707 } 708 709 static int nv_common_sw_init(void *handle) 710 { 711 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 712 713 if (amdgpu_sriov_vf(adev)) 714 xgpu_nv_mailbox_add_irq_id(adev); 715 716 return 0; 717 } 718 719 static int nv_common_sw_fini(void *handle) 720 { 721 return 0; 722 } 723 724 static int nv_common_hw_init(void *handle) 725 { 726 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 727 728 /* enable pcie gen2/3 link */ 729 nv_pcie_gen3_enable(adev); 730 /* enable aspm */ 731 nv_program_aspm(adev); 732 /* setup nbio registers */ 733 adev->nbio.funcs->init_registers(adev); 734 /* remap HDP registers to a hole in mmio space, 735 * for the purpose of expose those registers 736 * to process space 737 */ 738 if (adev->nbio.funcs->remap_hdp_registers) 739 adev->nbio.funcs->remap_hdp_registers(adev); 740 /* enable the doorbell aperture */ 741 nv_enable_doorbell_aperture(adev, true); 742 743 return 0; 744 } 745 746 static int nv_common_hw_fini(void *handle) 747 { 748 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 749 750 /* disable the doorbell aperture */ 751 nv_enable_doorbell_aperture(adev, false); 752 753 return 0; 754 } 755 756 static int nv_common_suspend(void *handle) 757 { 758 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 759 760 return nv_common_hw_fini(adev); 761 } 762 763 static int nv_common_resume(void *handle) 764 { 765 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 766 767 return nv_common_hw_init(adev); 768 } 769 770 static bool nv_common_is_idle(void *handle) 771 { 772 return true; 773 } 774 775 static int nv_common_wait_for_idle(void *handle) 776 { 777 return 0; 778 } 779 780 static int nv_common_soft_reset(void *handle) 781 { 782 return 0; 783 } 784 785 static void nv_update_hdp_mem_power_gating(struct amdgpu_device *adev, 786 bool enable) 787 { 788 uint32_t hdp_clk_cntl, hdp_clk_cntl1; 789 uint32_t hdp_mem_pwr_cntl; 790 791 if (!(adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | 792 AMD_CG_SUPPORT_HDP_DS | 793 AMD_CG_SUPPORT_HDP_SD))) 794 return; 795 796 hdp_clk_cntl = hdp_clk_cntl1 = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); 797 hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL); 798 799 /* Before doing clock/power mode switch, 800 * forced on IPH & RC clock */ 801 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL, 802 IPH_MEM_CLK_SOFT_OVERRIDE, 1); 803 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL, 804 RC_MEM_CLK_SOFT_OVERRIDE, 1); 805 WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl); 806 807 /* HDP 5.0 doesn't support dynamic power mode switch, 808 * disable clock and power gating before any changing */ 809 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 810 IPH_MEM_POWER_CTRL_EN, 0); 811 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 812 IPH_MEM_POWER_LS_EN, 0); 813 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 814 IPH_MEM_POWER_DS_EN, 0); 815 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 816 IPH_MEM_POWER_SD_EN, 0); 817 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 818 RC_MEM_POWER_CTRL_EN, 0); 819 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 820 RC_MEM_POWER_LS_EN, 0); 821 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 822 RC_MEM_POWER_DS_EN, 0); 823 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 824 RC_MEM_POWER_SD_EN, 0); 825 WREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); 826 827 /* only one clock gating mode (LS/DS/SD) can be enabled */ 828 if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) { 829 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 830 HDP_MEM_POWER_CTRL, 831 IPH_MEM_POWER_LS_EN, enable); 832 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 833 HDP_MEM_POWER_CTRL, 834 RC_MEM_POWER_LS_EN, enable); 835 } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_DS) { 836 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 837 HDP_MEM_POWER_CTRL, 838 IPH_MEM_POWER_DS_EN, enable); 839 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 840 HDP_MEM_POWER_CTRL, 841 RC_MEM_POWER_DS_EN, enable); 842 } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_SD) { 843 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 844 HDP_MEM_POWER_CTRL, 845 IPH_MEM_POWER_SD_EN, enable); 846 /* RC should not use shut down mode, fallback to ds */ 847 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 848 HDP_MEM_POWER_CTRL, 849 RC_MEM_POWER_DS_EN, enable); 850 } 851 852 WREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); 853 854 /* restore IPH & RC clock override after clock/power mode changing */ 855 WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl1); 856 } 857 858 static void nv_update_hdp_clock_gating(struct amdgpu_device *adev, 859 bool enable) 860 { 861 uint32_t hdp_clk_cntl; 862 863 if (!(adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG)) 864 return; 865 866 hdp_clk_cntl = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); 867 868 if (enable) { 869 hdp_clk_cntl &= 870 ~(uint32_t) 871 (HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK | 872 HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK | 873 HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK | 874 HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK | 875 HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK | 876 HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK); 877 } else { 878 hdp_clk_cntl |= HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK | 879 HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK | 880 HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK | 881 HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK | 882 HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK | 883 HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK; 884 } 885 886 WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl); 887 } 888 889 static int nv_common_set_clockgating_state(void *handle, 890 enum amd_clockgating_state state) 891 { 892 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 893 894 if (amdgpu_sriov_vf(adev)) 895 return 0; 896 897 switch (adev->asic_type) { 898 case CHIP_NAVI10: 899 case CHIP_NAVI14: 900 case CHIP_NAVI12: 901 adev->nbio.funcs->update_medium_grain_clock_gating(adev, 902 state == AMD_CG_STATE_GATE ? true : false); 903 adev->nbio.funcs->update_medium_grain_light_sleep(adev, 904 state == AMD_CG_STATE_GATE ? true : false); 905 nv_update_hdp_mem_power_gating(adev, 906 state == AMD_CG_STATE_GATE ? true : false); 907 nv_update_hdp_clock_gating(adev, 908 state == AMD_CG_STATE_GATE ? true : false); 909 break; 910 default: 911 break; 912 } 913 return 0; 914 } 915 916 static int nv_common_set_powergating_state(void *handle, 917 enum amd_powergating_state state) 918 { 919 /* TODO */ 920 return 0; 921 } 922 923 static void nv_common_get_clockgating_state(void *handle, u32 *flags) 924 { 925 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 926 uint32_t tmp; 927 928 if (amdgpu_sriov_vf(adev)) 929 *flags = 0; 930 931 adev->nbio.funcs->get_clockgating_state(adev, flags); 932 933 /* AMD_CG_SUPPORT_HDP_MGCG */ 934 tmp = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); 935 if (!(tmp & (HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK | 936 HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK | 937 HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK | 938 HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK | 939 HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK | 940 HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK))) 941 *flags |= AMD_CG_SUPPORT_HDP_MGCG; 942 943 /* AMD_CG_SUPPORT_HDP_LS/DS/SD */ 944 tmp = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL); 945 if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK) 946 *flags |= AMD_CG_SUPPORT_HDP_LS; 947 else if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_DS_EN_MASK) 948 *flags |= AMD_CG_SUPPORT_HDP_DS; 949 else if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_SD_EN_MASK) 950 *flags |= AMD_CG_SUPPORT_HDP_SD; 951 952 return; 953 } 954 955 static const struct amd_ip_funcs nv_common_ip_funcs = { 956 .name = "nv_common", 957 .early_init = nv_common_early_init, 958 .late_init = nv_common_late_init, 959 .sw_init = nv_common_sw_init, 960 .sw_fini = nv_common_sw_fini, 961 .hw_init = nv_common_hw_init, 962 .hw_fini = nv_common_hw_fini, 963 .suspend = nv_common_suspend, 964 .resume = nv_common_resume, 965 .is_idle = nv_common_is_idle, 966 .wait_for_idle = nv_common_wait_for_idle, 967 .soft_reset = nv_common_soft_reset, 968 .set_clockgating_state = nv_common_set_clockgating_state, 969 .set_powergating_state = nv_common_set_powergating_state, 970 .get_clockgating_state = nv_common_get_clockgating_state, 971 }; 972