1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/slab.h> 25 #include <linux/module.h> 26 #include <linux/pci.h> 27 28 #include <drm/amdgpu_drm.h> 29 30 #include "amdgpu.h" 31 #include "amdgpu_atombios.h" 32 #include "amdgpu_ih.h" 33 #include "amdgpu_uvd.h" 34 #include "amdgpu_vce.h" 35 #include "amdgpu_ucode.h" 36 #include "amdgpu_psp.h" 37 #include "atom.h" 38 #include "amd_pcie.h" 39 40 #include "gc/gc_10_1_0_offset.h" 41 #include "gc/gc_10_1_0_sh_mask.h" 42 #include "mp/mp_11_0_offset.h" 43 44 #include "soc15.h" 45 #include "soc15_common.h" 46 #include "gmc_v10_0.h" 47 #include "gfxhub_v2_0.h" 48 #include "mmhub_v2_0.h" 49 #include "nbio_v2_3.h" 50 #include "nbio_v7_2.h" 51 #include "hdp_v5_0.h" 52 #include "nv.h" 53 #include "navi10_ih.h" 54 #include "gfx_v10_0.h" 55 #include "sdma_v5_0.h" 56 #include "sdma_v5_2.h" 57 #include "vcn_v2_0.h" 58 #include "jpeg_v2_0.h" 59 #include "vcn_v3_0.h" 60 #include "jpeg_v3_0.h" 61 #include "amdgpu_vkms.h" 62 #include "mxgpu_nv.h" 63 #include "smuio_v11_0.h" 64 #include "smuio_v11_0_6.h" 65 66 static const struct amd_ip_funcs nv_common_ip_funcs; 67 68 /* Navi */ 69 static const struct amdgpu_video_codec_info nv_video_codecs_encode_array[] = { 70 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)}, 71 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 4096, 0)}, 72 }; 73 74 static const struct amdgpu_video_codecs nv_video_codecs_encode = { 75 .codec_count = ARRAY_SIZE(nv_video_codecs_encode_array), 76 .codec_array = nv_video_codecs_encode_array, 77 }; 78 79 /* Navi1x */ 80 static const struct amdgpu_video_codec_info nv_video_codecs_decode_array[] = { 81 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 1920, 1088, 3)}, 82 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 1920, 1088, 5)}, 83 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 84 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 1920, 1088, 4)}, 85 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 86 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 8192, 8192, 0)}, 87 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 88 }; 89 90 static const struct amdgpu_video_codecs nv_video_codecs_decode = { 91 .codec_count = ARRAY_SIZE(nv_video_codecs_decode_array), 92 .codec_array = nv_video_codecs_decode_array, 93 }; 94 95 /* Sienna Cichlid */ 96 static const struct amdgpu_video_codec_info sc_video_codecs_encode_array[] = { 97 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)}, 98 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)}, 99 }; 100 101 static const struct amdgpu_video_codecs sc_video_codecs_encode = { 102 .codec_count = ARRAY_SIZE(sc_video_codecs_encode_array), 103 .codec_array = sc_video_codecs_encode_array, 104 }; 105 106 static const struct amdgpu_video_codec_info sc_video_codecs_decode_array_vcn0[] = { 107 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 1920, 1088, 3)}, 108 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 1920, 1088, 5)}, 109 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 110 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 1920, 1088, 4)}, 111 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 112 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)}, 113 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 114 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 115 }; 116 117 static const struct amdgpu_video_codec_info sc_video_codecs_decode_array_vcn1[] = { 118 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 1920, 1088, 3)}, 119 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 1920, 1088, 5)}, 120 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 121 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 1920, 1088, 4)}, 122 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 123 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)}, 124 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 125 }; 126 127 static const struct amdgpu_video_codecs sc_video_codecs_decode_vcn0 = { 128 .codec_count = ARRAY_SIZE(sc_video_codecs_decode_array_vcn0), 129 .codec_array = sc_video_codecs_decode_array_vcn0, 130 }; 131 132 static const struct amdgpu_video_codecs sc_video_codecs_decode_vcn1 = { 133 .codec_count = ARRAY_SIZE(sc_video_codecs_decode_array_vcn1), 134 .codec_array = sc_video_codecs_decode_array_vcn1, 135 }; 136 137 /* SRIOV Sienna Cichlid, not const since data is controlled by host */ 138 static struct amdgpu_video_codec_info sriov_sc_video_codecs_encode_array[] = { 139 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)}, 140 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)}, 141 }; 142 143 static struct amdgpu_video_codec_info sriov_sc_video_codecs_decode_array_vcn0[] = { 144 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 1920, 1088, 3)}, 145 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 1920, 1088, 5)}, 146 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 147 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 1920, 1088, 4)}, 148 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 149 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)}, 150 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 151 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 152 }; 153 154 static struct amdgpu_video_codec_info sriov_sc_video_codecs_decode_array_vcn1[] = { 155 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 1920, 1088, 3)}, 156 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 1920, 1088, 5)}, 157 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 158 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 1920, 1088, 4)}, 159 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 160 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)}, 161 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 162 }; 163 164 static struct amdgpu_video_codecs sriov_sc_video_codecs_encode = { 165 .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_encode_array), 166 .codec_array = sriov_sc_video_codecs_encode_array, 167 }; 168 169 static struct amdgpu_video_codecs sriov_sc_video_codecs_decode_vcn0 = { 170 .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_decode_array_vcn0), 171 .codec_array = sriov_sc_video_codecs_decode_array_vcn0, 172 }; 173 174 static struct amdgpu_video_codecs sriov_sc_video_codecs_decode_vcn1 = { 175 .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_decode_array_vcn1), 176 .codec_array = sriov_sc_video_codecs_decode_array_vcn1, 177 }; 178 179 /* Beige Goby*/ 180 static const struct amdgpu_video_codec_info bg_video_codecs_decode_array[] = { 181 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 182 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 183 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 184 }; 185 186 static const struct amdgpu_video_codecs bg_video_codecs_decode = { 187 .codec_count = ARRAY_SIZE(bg_video_codecs_decode_array), 188 .codec_array = bg_video_codecs_decode_array, 189 }; 190 191 static const struct amdgpu_video_codecs bg_video_codecs_encode = { 192 .codec_count = 0, 193 .codec_array = NULL, 194 }; 195 196 /* Yellow Carp*/ 197 static const struct amdgpu_video_codec_info yc_video_codecs_decode_array[] = { 198 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 199 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 200 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 201 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)}, 202 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 203 }; 204 205 static const struct amdgpu_video_codecs yc_video_codecs_decode = { 206 .codec_count = ARRAY_SIZE(yc_video_codecs_decode_array), 207 .codec_array = yc_video_codecs_decode_array, 208 }; 209 210 static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode, 211 const struct amdgpu_video_codecs **codecs) 212 { 213 if (adev->vcn.num_vcn_inst == hweight8(adev->vcn.harvest_config)) 214 return -EINVAL; 215 216 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) { 217 case IP_VERSION(3, 0, 0): 218 case IP_VERSION(3, 0, 64): 219 case IP_VERSION(3, 0, 192): 220 if (amdgpu_sriov_vf(adev)) { 221 if (adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) { 222 if (encode) 223 *codecs = &sriov_sc_video_codecs_encode; 224 else 225 *codecs = &sriov_sc_video_codecs_decode_vcn1; 226 } else { 227 if (encode) 228 *codecs = &sriov_sc_video_codecs_encode; 229 else 230 *codecs = &sriov_sc_video_codecs_decode_vcn0; 231 } 232 } else { 233 if (adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) { 234 if (encode) 235 *codecs = &sc_video_codecs_encode; 236 else 237 *codecs = &sc_video_codecs_decode_vcn1; 238 } else { 239 if (encode) 240 *codecs = &sc_video_codecs_encode; 241 else 242 *codecs = &sc_video_codecs_decode_vcn0; 243 } 244 } 245 return 0; 246 case IP_VERSION(3, 0, 16): 247 case IP_VERSION(3, 0, 2): 248 if (encode) 249 *codecs = &sc_video_codecs_encode; 250 else 251 *codecs = &sc_video_codecs_decode_vcn0; 252 return 0; 253 case IP_VERSION(3, 1, 1): 254 case IP_VERSION(3, 1, 2): 255 if (encode) 256 *codecs = &sc_video_codecs_encode; 257 else 258 *codecs = &yc_video_codecs_decode; 259 return 0; 260 case IP_VERSION(3, 0, 33): 261 if (encode) 262 *codecs = &bg_video_codecs_encode; 263 else 264 *codecs = &bg_video_codecs_decode; 265 return 0; 266 case IP_VERSION(2, 0, 0): 267 case IP_VERSION(2, 0, 2): 268 if (encode) 269 *codecs = &nv_video_codecs_encode; 270 else 271 *codecs = &nv_video_codecs_decode; 272 return 0; 273 default: 274 return -EINVAL; 275 } 276 } 277 278 static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg) 279 { 280 unsigned long flags, address, data; 281 u32 r; 282 283 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 284 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 285 286 spin_lock_irqsave(&adev->reg.didt.lock, flags); 287 WREG32(address, (reg)); 288 r = RREG32(data); 289 spin_unlock_irqrestore(&adev->reg.didt.lock, flags); 290 return r; 291 } 292 293 static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 294 { 295 unsigned long flags, address, data; 296 297 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 298 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 299 300 spin_lock_irqsave(&adev->reg.didt.lock, flags); 301 WREG32(address, (reg)); 302 WREG32(data, (v)); 303 spin_unlock_irqrestore(&adev->reg.didt.lock, flags); 304 } 305 306 static u32 nv_get_config_memsize(struct amdgpu_device *adev) 307 { 308 return adev->nbio.funcs->get_memsize(adev); 309 } 310 311 static u32 nv_get_xclk(struct amdgpu_device *adev) 312 { 313 return adev->clock.spll.reference_freq; 314 } 315 316 317 void nv_grbm_select(struct amdgpu_device *adev, 318 u32 me, u32 pipe, u32 queue, u32 vmid) 319 { 320 u32 grbm_gfx_cntl = 0; 321 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); 322 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); 323 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); 324 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); 325 326 WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl); 327 } 328 329 static bool nv_read_disabled_bios(struct amdgpu_device *adev) 330 { 331 /* todo */ 332 return false; 333 } 334 335 static struct soc15_allowed_register_entry nv_allowed_read_registers[] = { 336 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)}, 337 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)}, 338 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)}, 339 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)}, 340 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)}, 341 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)}, 342 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)}, 343 { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)}, 344 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)}, 345 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)}, 346 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)}, 347 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)}, 348 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)}, 349 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)}, 350 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)}, 351 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)}, 352 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)}, 353 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)}, 354 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)}, 355 }; 356 357 static uint32_t nv_get_register_value(struct amdgpu_device *adev, 358 bool indexed, u32 se_num, 359 u32 sh_num, u32 reg_offset) 360 { 361 if (indexed) { 362 return amdgpu_read_indexed_register(adev, se_num, sh_num, reg_offset); 363 } else { 364 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) 365 return adev->gfx.config.gb_addr_config; 366 return RREG32(reg_offset); 367 } 368 } 369 370 static int nv_read_register(struct amdgpu_device *adev, u32 se_num, 371 u32 sh_num, u32 reg_offset, u32 *value) 372 { 373 uint32_t i; 374 struct soc15_allowed_register_entry *en; 375 376 *value = 0; 377 for (i = 0; i < ARRAY_SIZE(nv_allowed_read_registers); i++) { 378 en = &nv_allowed_read_registers[i]; 379 if (!adev->reg_offset[en->hwip][en->inst]) 380 continue; 381 else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg] 382 + en->reg_offset)) 383 continue; 384 385 *value = nv_get_register_value(adev, 386 nv_allowed_read_registers[i].grbm_indexed, 387 se_num, sh_num, reg_offset); 388 return 0; 389 } 390 return -EINVAL; 391 } 392 393 static int nv_asic_mode2_reset(struct amdgpu_device *adev) 394 { 395 u32 i; 396 int ret = 0; 397 398 amdgpu_atombios_scratch_regs_engine_hung(adev, true); 399 400 /* disable BM */ 401 pci_clear_master(adev->pdev); 402 403 amdgpu_device_cache_pci_state(adev->pdev); 404 405 ret = amdgpu_dpm_mode2_reset(adev); 406 if (ret) 407 dev_err(adev->dev, "GPU mode2 reset failed\n"); 408 409 amdgpu_device_load_pci_state(adev->pdev); 410 411 /* wait for asic to come out of reset */ 412 for (i = 0; i < adev->usec_timeout; i++) { 413 u32 memsize = adev->nbio.funcs->get_memsize(adev); 414 415 if (memsize != 0xffffffff) 416 break; 417 udelay(1); 418 } 419 420 amdgpu_atombios_scratch_regs_engine_hung(adev, false); 421 422 return ret; 423 } 424 425 static enum amd_reset_method 426 nv_asic_reset_method(struct amdgpu_device *adev) 427 { 428 if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 || 429 amdgpu_reset_method == AMD_RESET_METHOD_MODE2 || 430 amdgpu_reset_method == AMD_RESET_METHOD_BACO || 431 amdgpu_reset_method == AMD_RESET_METHOD_PCI) 432 return amdgpu_reset_method; 433 434 if (amdgpu_reset_method != -1) 435 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", 436 amdgpu_reset_method); 437 438 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 439 case IP_VERSION(11, 5, 0): 440 case IP_VERSION(11, 5, 2): 441 case IP_VERSION(13, 0, 1): 442 case IP_VERSION(13, 0, 3): 443 case IP_VERSION(13, 0, 5): 444 case IP_VERSION(13, 0, 8): 445 return AMD_RESET_METHOD_MODE2; 446 case IP_VERSION(11, 0, 7): 447 case IP_VERSION(11, 0, 11): 448 case IP_VERSION(11, 0, 12): 449 case IP_VERSION(11, 0, 13): 450 return AMD_RESET_METHOD_MODE1; 451 default: 452 if (amdgpu_dpm_is_baco_supported(adev)) 453 return AMD_RESET_METHOD_BACO; 454 else 455 return AMD_RESET_METHOD_MODE1; 456 } 457 } 458 459 static int nv_asic_reset(struct amdgpu_device *adev) 460 { 461 int ret = 0; 462 463 switch (nv_asic_reset_method(adev)) { 464 case AMD_RESET_METHOD_PCI: 465 dev_info(adev->dev, "PCI reset\n"); 466 ret = amdgpu_device_pci_reset(adev); 467 break; 468 case AMD_RESET_METHOD_BACO: 469 dev_info(adev->dev, "BACO reset\n"); 470 ret = amdgpu_dpm_baco_reset(adev); 471 break; 472 case AMD_RESET_METHOD_MODE2: 473 dev_info(adev->dev, "MODE2 reset\n"); 474 ret = nv_asic_mode2_reset(adev); 475 break; 476 default: 477 dev_info(adev->dev, "MODE1 reset\n"); 478 ret = amdgpu_device_mode1_reset(adev); 479 break; 480 } 481 482 return ret; 483 } 484 485 static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 486 { 487 /* todo */ 488 return 0; 489 } 490 491 static int nv_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 492 { 493 /* todo */ 494 return 0; 495 } 496 497 const struct amdgpu_ip_block_version nv_common_ip_block = { 498 .type = AMD_IP_BLOCK_TYPE_COMMON, 499 .major = 1, 500 .minor = 0, 501 .rev = 0, 502 .funcs = &nv_common_ip_funcs, 503 }; 504 505 void nv_set_virt_ops(struct amdgpu_device *adev) 506 { 507 adev->virt.ops = &xgpu_nv_virt_ops; 508 } 509 510 static bool nv_need_full_reset(struct amdgpu_device *adev) 511 { 512 return true; 513 } 514 515 static bool nv_need_reset_on_init(struct amdgpu_device *adev) 516 { 517 u32 sol_reg; 518 519 if (adev->flags & AMD_IS_APU) 520 return false; 521 522 /* Check sOS sign of life register to confirm sys driver and sOS 523 * are already been loaded. 524 */ 525 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 526 if (sol_reg) 527 return true; 528 529 return false; 530 } 531 532 static void nv_init_doorbell_index(struct amdgpu_device *adev) 533 { 534 adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ; 535 adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0; 536 adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1; 537 adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2; 538 adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3; 539 adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4; 540 adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5; 541 adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6; 542 adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7; 543 adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START; 544 adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END; 545 adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0; 546 adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1; 547 adev->doorbell_index.gfx_userqueue_start = 548 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_START; 549 adev->doorbell_index.gfx_userqueue_end = 550 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_END; 551 adev->doorbell_index.mes_ring0 = AMDGPU_NAVI10_DOORBELL_MES_RING0; 552 adev->doorbell_index.mes_ring1 = AMDGPU_NAVI10_DOORBELL_MES_RING1; 553 adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0; 554 adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1; 555 adev->doorbell_index.sdma_engine[2] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2; 556 adev->doorbell_index.sdma_engine[3] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3; 557 adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH; 558 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1; 559 adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3; 560 adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5; 561 adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7; 562 adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP; 563 adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP; 564 565 adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1; 566 adev->doorbell_index.sdma_doorbell_range = 20; 567 } 568 569 static int nv_update_umd_stable_pstate(struct amdgpu_device *adev, 570 bool enter) 571 { 572 if (enter) 573 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 574 else 575 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 576 577 if (adev->gfx.funcs->update_perfmon_mgcg) 578 adev->gfx.funcs->update_perfmon_mgcg(adev, !enter); 579 580 if (adev->nbio.funcs->enable_aspm && 581 amdgpu_device_should_use_aspm(adev)) 582 adev->nbio.funcs->enable_aspm(adev, !enter); 583 584 return 0; 585 } 586 587 static const struct amdgpu_asic_funcs nv_asic_funcs = { 588 .read_disabled_bios = &nv_read_disabled_bios, 589 .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom, 590 .read_register = &nv_read_register, 591 .reset = &nv_asic_reset, 592 .reset_method = &nv_asic_reset_method, 593 .get_xclk = &nv_get_xclk, 594 .set_uvd_clocks = &nv_set_uvd_clocks, 595 .set_vce_clocks = &nv_set_vce_clocks, 596 .get_config_memsize = &nv_get_config_memsize, 597 .init_doorbell_index = &nv_init_doorbell_index, 598 .need_full_reset = &nv_need_full_reset, 599 .need_reset_on_init = &nv_need_reset_on_init, 600 .get_pcie_replay_count = &amdgpu_nbio_get_pcie_replay_count, 601 .supports_baco = &amdgpu_dpm_is_baco_supported, 602 .update_umd_stable_pstate = &nv_update_umd_stable_pstate, 603 .query_video_codecs = &nv_query_video_codecs, 604 }; 605 606 static int nv_common_early_init(struct amdgpu_ip_block *ip_block) 607 { 608 struct amdgpu_device *adev = ip_block->adev; 609 610 adev->nbio.funcs->set_reg_remap(adev); 611 adev->reg.pcie.rreg = &amdgpu_device_indirect_rreg; 612 adev->reg.pcie.wreg = &amdgpu_device_indirect_wreg; 613 adev->reg.pcie.rreg64 = &amdgpu_device_indirect_rreg64; 614 adev->reg.pcie.wreg64 = &amdgpu_device_indirect_wreg64; 615 adev->reg.pcie.port_rreg = &amdgpu_device_pcie_port_rreg; 616 adev->reg.pcie.port_wreg = &amdgpu_device_pcie_port_wreg; 617 618 adev->reg.didt.rreg = &nv_didt_rreg; 619 adev->reg.didt.wreg = &nv_didt_wreg; 620 621 adev->asic_funcs = &nv_asic_funcs; 622 623 adev->rev_id = amdgpu_device_get_rev_id(adev); 624 adev->external_rev_id = 0xff; 625 /* TODO: split the GC and PG flags based on the relevant IP version for which 626 * they are relevant. 627 */ 628 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 629 case IP_VERSION(10, 1, 10): 630 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 631 AMD_CG_SUPPORT_GFX_CGCG | 632 AMD_CG_SUPPORT_IH_CG | 633 AMD_CG_SUPPORT_HDP_MGCG | 634 AMD_CG_SUPPORT_HDP_LS | 635 AMD_CG_SUPPORT_SDMA_MGCG | 636 AMD_CG_SUPPORT_SDMA_LS | 637 AMD_CG_SUPPORT_MC_MGCG | 638 AMD_CG_SUPPORT_MC_LS | 639 AMD_CG_SUPPORT_ATHUB_MGCG | 640 AMD_CG_SUPPORT_ATHUB_LS | 641 AMD_CG_SUPPORT_VCN_MGCG | 642 AMD_CG_SUPPORT_JPEG_MGCG | 643 AMD_CG_SUPPORT_BIF_MGCG | 644 AMD_CG_SUPPORT_BIF_LS; 645 adev->pg_flags = AMD_PG_SUPPORT_VCN | 646 AMD_PG_SUPPORT_VCN_DPG | 647 AMD_PG_SUPPORT_JPEG | 648 AMD_PG_SUPPORT_ATHUB; 649 adev->external_rev_id = adev->rev_id + 0x1; 650 break; 651 case IP_VERSION(10, 1, 1): 652 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 653 AMD_CG_SUPPORT_GFX_CGCG | 654 AMD_CG_SUPPORT_IH_CG | 655 AMD_CG_SUPPORT_HDP_MGCG | 656 AMD_CG_SUPPORT_HDP_LS | 657 AMD_CG_SUPPORT_SDMA_MGCG | 658 AMD_CG_SUPPORT_SDMA_LS | 659 AMD_CG_SUPPORT_MC_MGCG | 660 AMD_CG_SUPPORT_MC_LS | 661 AMD_CG_SUPPORT_ATHUB_MGCG | 662 AMD_CG_SUPPORT_ATHUB_LS | 663 AMD_CG_SUPPORT_VCN_MGCG | 664 AMD_CG_SUPPORT_JPEG_MGCG | 665 AMD_CG_SUPPORT_BIF_MGCG | 666 AMD_CG_SUPPORT_BIF_LS; 667 adev->pg_flags = AMD_PG_SUPPORT_VCN | 668 AMD_PG_SUPPORT_JPEG | 669 AMD_PG_SUPPORT_VCN_DPG; 670 adev->external_rev_id = adev->rev_id + 20; 671 break; 672 case IP_VERSION(10, 1, 2): 673 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 674 AMD_CG_SUPPORT_GFX_MGLS | 675 AMD_CG_SUPPORT_GFX_CGCG | 676 AMD_CG_SUPPORT_GFX_CP_LS | 677 AMD_CG_SUPPORT_GFX_RLC_LS | 678 AMD_CG_SUPPORT_IH_CG | 679 AMD_CG_SUPPORT_HDP_MGCG | 680 AMD_CG_SUPPORT_HDP_LS | 681 AMD_CG_SUPPORT_SDMA_MGCG | 682 AMD_CG_SUPPORT_SDMA_LS | 683 AMD_CG_SUPPORT_MC_MGCG | 684 AMD_CG_SUPPORT_MC_LS | 685 AMD_CG_SUPPORT_ATHUB_MGCG | 686 AMD_CG_SUPPORT_ATHUB_LS | 687 AMD_CG_SUPPORT_VCN_MGCG | 688 AMD_CG_SUPPORT_JPEG_MGCG; 689 adev->pg_flags = AMD_PG_SUPPORT_VCN | 690 AMD_PG_SUPPORT_VCN_DPG | 691 AMD_PG_SUPPORT_JPEG | 692 AMD_PG_SUPPORT_ATHUB; 693 /* guest vm gets 0xffffffff when reading RCC_DEV0_EPF0_STRAP0, 694 * as a consequence, the rev_id and external_rev_id are wrong. 695 * workaround it by hardcoding rev_id to 0 (default value). 696 */ 697 if (amdgpu_sriov_vf(adev)) 698 adev->rev_id = 0; 699 adev->external_rev_id = adev->rev_id + 0xa; 700 break; 701 case IP_VERSION(10, 3, 0): 702 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 703 AMD_CG_SUPPORT_GFX_CGCG | 704 AMD_CG_SUPPORT_GFX_CGLS | 705 AMD_CG_SUPPORT_GFX_3D_CGCG | 706 AMD_CG_SUPPORT_MC_MGCG | 707 AMD_CG_SUPPORT_VCN_MGCG | 708 AMD_CG_SUPPORT_JPEG_MGCG | 709 AMD_CG_SUPPORT_HDP_MGCG | 710 AMD_CG_SUPPORT_HDP_LS | 711 AMD_CG_SUPPORT_IH_CG | 712 AMD_CG_SUPPORT_MC_LS; 713 adev->pg_flags = AMD_PG_SUPPORT_VCN | 714 AMD_PG_SUPPORT_VCN_DPG | 715 AMD_PG_SUPPORT_JPEG | 716 AMD_PG_SUPPORT_ATHUB | 717 AMD_PG_SUPPORT_MMHUB; 718 if (amdgpu_sriov_vf(adev)) { 719 /* hypervisor control CG and PG enablement */ 720 adev->cg_flags = 0; 721 adev->pg_flags = 0; 722 } 723 adev->external_rev_id = adev->rev_id + 0x28; 724 break; 725 case IP_VERSION(10, 3, 2): 726 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 727 AMD_CG_SUPPORT_GFX_CGCG | 728 AMD_CG_SUPPORT_GFX_CGLS | 729 AMD_CG_SUPPORT_GFX_3D_CGCG | 730 AMD_CG_SUPPORT_VCN_MGCG | 731 AMD_CG_SUPPORT_JPEG_MGCG | 732 AMD_CG_SUPPORT_MC_MGCG | 733 AMD_CG_SUPPORT_MC_LS | 734 AMD_CG_SUPPORT_HDP_MGCG | 735 AMD_CG_SUPPORT_HDP_LS | 736 AMD_CG_SUPPORT_IH_CG; 737 adev->pg_flags = AMD_PG_SUPPORT_VCN | 738 AMD_PG_SUPPORT_VCN_DPG | 739 AMD_PG_SUPPORT_JPEG | 740 AMD_PG_SUPPORT_ATHUB | 741 AMD_PG_SUPPORT_MMHUB; 742 adev->external_rev_id = adev->rev_id + 0x32; 743 break; 744 case IP_VERSION(10, 3, 1): 745 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 746 AMD_CG_SUPPORT_GFX_MGLS | 747 AMD_CG_SUPPORT_GFX_CP_LS | 748 AMD_CG_SUPPORT_GFX_RLC_LS | 749 AMD_CG_SUPPORT_GFX_CGCG | 750 AMD_CG_SUPPORT_GFX_CGLS | 751 AMD_CG_SUPPORT_GFX_3D_CGCG | 752 AMD_CG_SUPPORT_GFX_3D_CGLS | 753 AMD_CG_SUPPORT_MC_MGCG | 754 AMD_CG_SUPPORT_MC_LS | 755 AMD_CG_SUPPORT_GFX_FGCG | 756 AMD_CG_SUPPORT_VCN_MGCG | 757 AMD_CG_SUPPORT_SDMA_MGCG | 758 AMD_CG_SUPPORT_SDMA_LS | 759 AMD_CG_SUPPORT_JPEG_MGCG; 760 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | 761 AMD_PG_SUPPORT_VCN | 762 AMD_PG_SUPPORT_VCN_DPG | 763 AMD_PG_SUPPORT_JPEG; 764 if (adev->apu_flags & AMD_APU_IS_VANGOGH) 765 adev->external_rev_id = adev->rev_id + 0x01; 766 break; 767 case IP_VERSION(10, 3, 4): 768 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 769 AMD_CG_SUPPORT_GFX_CGCG | 770 AMD_CG_SUPPORT_GFX_CGLS | 771 AMD_CG_SUPPORT_GFX_3D_CGCG | 772 AMD_CG_SUPPORT_VCN_MGCG | 773 AMD_CG_SUPPORT_JPEG_MGCG | 774 AMD_CG_SUPPORT_MC_MGCG | 775 AMD_CG_SUPPORT_MC_LS | 776 AMD_CG_SUPPORT_HDP_MGCG | 777 AMD_CG_SUPPORT_HDP_LS | 778 AMD_CG_SUPPORT_IH_CG; 779 adev->pg_flags = AMD_PG_SUPPORT_VCN | 780 AMD_PG_SUPPORT_VCN_DPG | 781 AMD_PG_SUPPORT_JPEG | 782 AMD_PG_SUPPORT_ATHUB | 783 AMD_PG_SUPPORT_MMHUB; 784 adev->external_rev_id = adev->rev_id + 0x3c; 785 break; 786 case IP_VERSION(10, 3, 5): 787 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 788 AMD_CG_SUPPORT_GFX_CGCG | 789 AMD_CG_SUPPORT_GFX_CGLS | 790 AMD_CG_SUPPORT_GFX_3D_CGCG | 791 AMD_CG_SUPPORT_MC_MGCG | 792 AMD_CG_SUPPORT_MC_LS | 793 AMD_CG_SUPPORT_HDP_MGCG | 794 AMD_CG_SUPPORT_HDP_LS | 795 AMD_CG_SUPPORT_IH_CG | 796 AMD_CG_SUPPORT_VCN_MGCG; 797 adev->pg_flags = AMD_PG_SUPPORT_VCN | 798 AMD_PG_SUPPORT_VCN_DPG | 799 AMD_PG_SUPPORT_ATHUB | 800 AMD_PG_SUPPORT_MMHUB; 801 adev->external_rev_id = adev->rev_id + 0x46; 802 break; 803 case IP_VERSION(10, 3, 3): 804 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 805 AMD_CG_SUPPORT_GFX_MGLS | 806 AMD_CG_SUPPORT_GFX_CGCG | 807 AMD_CG_SUPPORT_GFX_CGLS | 808 AMD_CG_SUPPORT_GFX_3D_CGCG | 809 AMD_CG_SUPPORT_GFX_3D_CGLS | 810 AMD_CG_SUPPORT_GFX_RLC_LS | 811 AMD_CG_SUPPORT_GFX_CP_LS | 812 AMD_CG_SUPPORT_GFX_FGCG | 813 AMD_CG_SUPPORT_MC_MGCG | 814 AMD_CG_SUPPORT_MC_LS | 815 AMD_CG_SUPPORT_SDMA_LS | 816 AMD_CG_SUPPORT_HDP_MGCG | 817 AMD_CG_SUPPORT_HDP_LS | 818 AMD_CG_SUPPORT_ATHUB_MGCG | 819 AMD_CG_SUPPORT_ATHUB_LS | 820 AMD_CG_SUPPORT_IH_CG | 821 AMD_CG_SUPPORT_VCN_MGCG | 822 AMD_CG_SUPPORT_JPEG_MGCG | 823 AMD_CG_SUPPORT_SDMA_MGCG; 824 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | 825 AMD_PG_SUPPORT_VCN | 826 AMD_PG_SUPPORT_VCN_DPG | 827 AMD_PG_SUPPORT_JPEG; 828 if (adev->pdev->device == 0x1681) 829 adev->external_rev_id = 0x20; 830 else 831 adev->external_rev_id = adev->rev_id + 0x01; 832 break; 833 case IP_VERSION(10, 1, 3): 834 case IP_VERSION(10, 1, 4): 835 adev->cg_flags = 0; 836 adev->pg_flags = 0; 837 adev->external_rev_id = adev->rev_id + 0x82; 838 break; 839 case IP_VERSION(10, 3, 6): 840 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 841 AMD_CG_SUPPORT_GFX_MGLS | 842 AMD_CG_SUPPORT_GFX_CGCG | 843 AMD_CG_SUPPORT_GFX_CGLS | 844 AMD_CG_SUPPORT_GFX_3D_CGCG | 845 AMD_CG_SUPPORT_GFX_3D_CGLS | 846 AMD_CG_SUPPORT_GFX_RLC_LS | 847 AMD_CG_SUPPORT_GFX_CP_LS | 848 AMD_CG_SUPPORT_GFX_FGCG | 849 AMD_CG_SUPPORT_MC_MGCG | 850 AMD_CG_SUPPORT_MC_LS | 851 AMD_CG_SUPPORT_SDMA_LS | 852 AMD_CG_SUPPORT_HDP_MGCG | 853 AMD_CG_SUPPORT_HDP_LS | 854 AMD_CG_SUPPORT_ATHUB_MGCG | 855 AMD_CG_SUPPORT_ATHUB_LS | 856 AMD_CG_SUPPORT_IH_CG | 857 AMD_CG_SUPPORT_VCN_MGCG | 858 AMD_CG_SUPPORT_JPEG_MGCG; 859 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | 860 AMD_PG_SUPPORT_VCN | 861 AMD_PG_SUPPORT_VCN_DPG | 862 AMD_PG_SUPPORT_JPEG; 863 adev->external_rev_id = adev->rev_id + 0x01; 864 break; 865 case IP_VERSION(10, 3, 7): 866 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 867 AMD_CG_SUPPORT_GFX_MGLS | 868 AMD_CG_SUPPORT_GFX_CGCG | 869 AMD_CG_SUPPORT_GFX_CGLS | 870 AMD_CG_SUPPORT_GFX_3D_CGCG | 871 AMD_CG_SUPPORT_GFX_3D_CGLS | 872 AMD_CG_SUPPORT_GFX_RLC_LS | 873 AMD_CG_SUPPORT_GFX_CP_LS | 874 AMD_CG_SUPPORT_GFX_FGCG | 875 AMD_CG_SUPPORT_MC_MGCG | 876 AMD_CG_SUPPORT_MC_LS | 877 AMD_CG_SUPPORT_SDMA_LS | 878 AMD_CG_SUPPORT_HDP_MGCG | 879 AMD_CG_SUPPORT_HDP_LS | 880 AMD_CG_SUPPORT_ATHUB_MGCG | 881 AMD_CG_SUPPORT_ATHUB_LS | 882 AMD_CG_SUPPORT_IH_CG | 883 AMD_CG_SUPPORT_VCN_MGCG | 884 AMD_CG_SUPPORT_JPEG_MGCG | 885 AMD_CG_SUPPORT_SDMA_MGCG; 886 adev->pg_flags = AMD_PG_SUPPORT_VCN | 887 AMD_PG_SUPPORT_VCN_DPG | 888 AMD_PG_SUPPORT_JPEG | 889 AMD_PG_SUPPORT_GFX_PG; 890 adev->external_rev_id = adev->rev_id + 0x01; 891 break; 892 default: 893 /* FIXME: not supported yet */ 894 return -EINVAL; 895 } 896 897 if (adev->harvest_ip_mask & AMD_HARVEST_IP_VCN_MASK) 898 adev->pg_flags &= ~(AMD_PG_SUPPORT_VCN | 899 AMD_PG_SUPPORT_VCN_DPG | 900 AMD_PG_SUPPORT_JPEG); 901 902 if (amdgpu_sriov_vf(adev)) { 903 amdgpu_virt_init_setting(adev); 904 xgpu_nv_mailbox_set_irq_funcs(adev); 905 } 906 907 return 0; 908 } 909 910 static int nv_common_late_init(struct amdgpu_ip_block *ip_block) 911 { 912 struct amdgpu_device *adev = ip_block->adev; 913 914 if (amdgpu_sriov_vf(adev)) { 915 xgpu_nv_mailbox_get_irq(adev); 916 if (adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) { 917 amdgpu_virt_update_sriov_video_codec(adev, 918 sriov_sc_video_codecs_encode_array, 919 ARRAY_SIZE(sriov_sc_video_codecs_encode_array), 920 sriov_sc_video_codecs_decode_array_vcn1, 921 ARRAY_SIZE(sriov_sc_video_codecs_decode_array_vcn1)); 922 } else { 923 amdgpu_virt_update_sriov_video_codec(adev, 924 sriov_sc_video_codecs_encode_array, 925 ARRAY_SIZE(sriov_sc_video_codecs_encode_array), 926 sriov_sc_video_codecs_decode_array_vcn0, 927 ARRAY_SIZE(sriov_sc_video_codecs_decode_array_vcn0)); 928 } 929 } 930 931 /* Enable selfring doorbell aperture late because doorbell BAR 932 * aperture will change if resize BAR successfully in gmc sw_init. 933 */ 934 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, true); 935 936 return 0; 937 } 938 939 static int nv_common_sw_init(struct amdgpu_ip_block *ip_block) 940 { 941 struct amdgpu_device *adev = ip_block->adev; 942 943 if (amdgpu_sriov_vf(adev)) 944 xgpu_nv_mailbox_add_irq_id(adev); 945 946 return 0; 947 } 948 949 static int nv_common_hw_init(struct amdgpu_ip_block *ip_block) 950 { 951 struct amdgpu_device *adev = ip_block->adev; 952 953 if (adev->nbio.funcs->apply_lc_spc_mode_wa) 954 adev->nbio.funcs->apply_lc_spc_mode_wa(adev); 955 956 if (adev->nbio.funcs->apply_l1_link_width_reconfig_wa) 957 adev->nbio.funcs->apply_l1_link_width_reconfig_wa(adev); 958 959 /* enable aspm */ 960 amdgpu_nbio_program_aspm(adev); 961 /* setup nbio registers */ 962 adev->nbio.funcs->init_registers(adev); 963 /* remap HDP registers to a hole in mmio space, 964 * for the purpose of expose those registers 965 * to process space 966 */ 967 if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev)) 968 adev->nbio.funcs->remap_hdp_registers(adev); 969 /* enable the doorbell aperture */ 970 adev->nbio.funcs->enable_doorbell_aperture(adev, true); 971 972 return 0; 973 } 974 975 static int nv_common_hw_fini(struct amdgpu_ip_block *ip_block) 976 { 977 struct amdgpu_device *adev = ip_block->adev; 978 979 /* Disable the doorbell aperture and selfring doorbell aperture 980 * separately in hw_fini because nv_enable_doorbell_aperture 981 * has been removed and there is no need to delay disabling 982 * selfring doorbell. 983 */ 984 adev->nbio.funcs->enable_doorbell_aperture(adev, false); 985 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, false); 986 987 return 0; 988 } 989 990 static int nv_common_suspend(struct amdgpu_ip_block *ip_block) 991 { 992 return nv_common_hw_fini(ip_block); 993 } 994 995 static int nv_common_resume(struct amdgpu_ip_block *ip_block) 996 { 997 return nv_common_hw_init(ip_block); 998 } 999 1000 static bool nv_common_is_idle(struct amdgpu_ip_block *ip_block) 1001 { 1002 return true; 1003 } 1004 1005 static int nv_common_set_clockgating_state(struct amdgpu_ip_block *ip_block, 1006 enum amd_clockgating_state state) 1007 { 1008 struct amdgpu_device *adev = ip_block->adev; 1009 1010 if (amdgpu_sriov_vf(adev)) 1011 return 0; 1012 1013 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) { 1014 case IP_VERSION(2, 3, 0): 1015 case IP_VERSION(2, 3, 1): 1016 case IP_VERSION(2, 3, 2): 1017 case IP_VERSION(3, 3, 0): 1018 case IP_VERSION(3, 3, 1): 1019 case IP_VERSION(3, 3, 2): 1020 case IP_VERSION(3, 3, 3): 1021 adev->nbio.funcs->update_medium_grain_clock_gating(adev, 1022 state == AMD_CG_STATE_GATE); 1023 adev->nbio.funcs->update_medium_grain_light_sleep(adev, 1024 state == AMD_CG_STATE_GATE); 1025 adev->hdp.funcs->update_clock_gating(adev, 1026 state == AMD_CG_STATE_GATE); 1027 adev->smuio.funcs->update_rom_clock_gating(adev, 1028 state == AMD_CG_STATE_GATE); 1029 break; 1030 default: 1031 break; 1032 } 1033 return 0; 1034 } 1035 1036 static int nv_common_set_powergating_state(struct amdgpu_ip_block *ip_block, 1037 enum amd_powergating_state state) 1038 { 1039 /* TODO */ 1040 return 0; 1041 } 1042 1043 static void nv_common_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags) 1044 { 1045 struct amdgpu_device *adev = ip_block->adev; 1046 1047 if (amdgpu_sriov_vf(adev)) 1048 *flags = 0; 1049 1050 adev->nbio.funcs->get_clockgating_state(adev, flags); 1051 1052 adev->hdp.funcs->get_clock_gating_state(adev, flags); 1053 1054 adev->smuio.funcs->get_clock_gating_state(adev, flags); 1055 } 1056 1057 static const struct amd_ip_funcs nv_common_ip_funcs = { 1058 .name = "nv_common", 1059 .early_init = nv_common_early_init, 1060 .late_init = nv_common_late_init, 1061 .sw_init = nv_common_sw_init, 1062 .hw_init = nv_common_hw_init, 1063 .hw_fini = nv_common_hw_fini, 1064 .suspend = nv_common_suspend, 1065 .resume = nv_common_resume, 1066 .is_idle = nv_common_is_idle, 1067 .set_clockgating_state = nv_common_set_clockgating_state, 1068 .set_powergating_state = nv_common_set_powergating_state, 1069 .get_clockgating_state = nv_common_get_clockgating_state, 1070 }; 1071