1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/slab.h> 25 #include <linux/module.h> 26 #include <linux/pci.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_atombios.h" 30 #include "amdgpu_ih.h" 31 #include "amdgpu_uvd.h" 32 #include "amdgpu_vce.h" 33 #include "amdgpu_ucode.h" 34 #include "amdgpu_psp.h" 35 #include "amdgpu_smu.h" 36 #include "atom.h" 37 #include "amd_pcie.h" 38 39 #include "gc/gc_10_1_0_offset.h" 40 #include "gc/gc_10_1_0_sh_mask.h" 41 #include "hdp/hdp_5_0_0_offset.h" 42 #include "hdp/hdp_5_0_0_sh_mask.h" 43 44 #include "soc15.h" 45 #include "soc15_common.h" 46 #include "gmc_v10_0.h" 47 #include "gfxhub_v2_0.h" 48 #include "mmhub_v2_0.h" 49 #include "nv.h" 50 #include "navi10_ih.h" 51 #include "gfx_v10_0.h" 52 #include "sdma_v5_0.h" 53 #include "vcn_v2_0.h" 54 #include "dce_virtual.h" 55 #include "mes_v10_1.h" 56 57 static const struct amd_ip_funcs nv_common_ip_funcs; 58 59 /* 60 * Indirect registers accessor 61 */ 62 static u32 nv_pcie_rreg(struct amdgpu_device *adev, u32 reg) 63 { 64 unsigned long flags, address, data; 65 u32 r; 66 address = adev->nbio_funcs->get_pcie_index_offset(adev); 67 data = adev->nbio_funcs->get_pcie_data_offset(adev); 68 69 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 70 WREG32(address, reg); 71 (void)RREG32(address); 72 r = RREG32(data); 73 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 74 return r; 75 } 76 77 static void nv_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 78 { 79 unsigned long flags, address, data; 80 81 address = adev->nbio_funcs->get_pcie_index_offset(adev); 82 data = adev->nbio_funcs->get_pcie_data_offset(adev); 83 84 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 85 WREG32(address, reg); 86 (void)RREG32(address); 87 WREG32(data, v); 88 (void)RREG32(data); 89 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 90 } 91 92 static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg) 93 { 94 unsigned long flags, address, data; 95 u32 r; 96 97 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 98 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 99 100 spin_lock_irqsave(&adev->didt_idx_lock, flags); 101 WREG32(address, (reg)); 102 r = RREG32(data); 103 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 104 return r; 105 } 106 107 static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 108 { 109 unsigned long flags, address, data; 110 111 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 112 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 113 114 spin_lock_irqsave(&adev->didt_idx_lock, flags); 115 WREG32(address, (reg)); 116 WREG32(data, (v)); 117 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 118 } 119 120 static u32 nv_get_config_memsize(struct amdgpu_device *adev) 121 { 122 return adev->nbio_funcs->get_memsize(adev); 123 } 124 125 static u32 nv_get_xclk(struct amdgpu_device *adev) 126 { 127 return adev->clock.spll.reference_freq; 128 } 129 130 131 void nv_grbm_select(struct amdgpu_device *adev, 132 u32 me, u32 pipe, u32 queue, u32 vmid) 133 { 134 u32 grbm_gfx_cntl = 0; 135 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); 136 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); 137 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); 138 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); 139 140 WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL), grbm_gfx_cntl); 141 } 142 143 static void nv_vga_set_state(struct amdgpu_device *adev, bool state) 144 { 145 /* todo */ 146 } 147 148 static bool nv_read_disabled_bios(struct amdgpu_device *adev) 149 { 150 /* todo */ 151 return false; 152 } 153 154 static bool nv_read_bios_from_rom(struct amdgpu_device *adev, 155 u8 *bios, u32 length_bytes) 156 { 157 /* TODO: will implement it when SMU header is available */ 158 return false; 159 } 160 161 static struct soc15_allowed_register_entry nv_allowed_read_registers[] = { 162 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)}, 163 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)}, 164 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)}, 165 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)}, 166 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)}, 167 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)}, 168 #if 0 /* TODO: will set it when SDMA header is available */ 169 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)}, 170 { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)}, 171 #endif 172 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)}, 173 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)}, 174 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)}, 175 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)}, 176 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)}, 177 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)}, 178 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)}, 179 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)}, 180 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)}, 181 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)}, 182 }; 183 184 static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num, 185 u32 sh_num, u32 reg_offset) 186 { 187 uint32_t val; 188 189 mutex_lock(&adev->grbm_idx_mutex); 190 if (se_num != 0xffffffff || sh_num != 0xffffffff) 191 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); 192 193 val = RREG32(reg_offset); 194 195 if (se_num != 0xffffffff || sh_num != 0xffffffff) 196 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 197 mutex_unlock(&adev->grbm_idx_mutex); 198 return val; 199 } 200 201 static uint32_t nv_get_register_value(struct amdgpu_device *adev, 202 bool indexed, u32 se_num, 203 u32 sh_num, u32 reg_offset) 204 { 205 if (indexed) { 206 return nv_read_indexed_register(adev, se_num, sh_num, reg_offset); 207 } else { 208 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) 209 return adev->gfx.config.gb_addr_config; 210 return RREG32(reg_offset); 211 } 212 } 213 214 static int nv_read_register(struct amdgpu_device *adev, u32 se_num, 215 u32 sh_num, u32 reg_offset, u32 *value) 216 { 217 uint32_t i; 218 struct soc15_allowed_register_entry *en; 219 220 *value = 0; 221 for (i = 0; i < ARRAY_SIZE(nv_allowed_read_registers); i++) { 222 en = &nv_allowed_read_registers[i]; 223 if (reg_offset != 224 (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset)) 225 continue; 226 227 *value = nv_get_register_value(adev, 228 nv_allowed_read_registers[i].grbm_indexed, 229 se_num, sh_num, reg_offset); 230 return 0; 231 } 232 return -EINVAL; 233 } 234 235 #if 0 236 static void nv_gpu_pci_config_reset(struct amdgpu_device *adev) 237 { 238 u32 i; 239 240 dev_info(adev->dev, "GPU pci config reset\n"); 241 242 /* disable BM */ 243 pci_clear_master(adev->pdev); 244 /* reset */ 245 amdgpu_pci_config_reset(adev); 246 247 udelay(100); 248 249 /* wait for asic to come out of reset */ 250 for (i = 0; i < adev->usec_timeout; i++) { 251 u32 memsize = nbio_v2_3_get_memsize(adev); 252 if (memsize != 0xffffffff) 253 break; 254 udelay(1); 255 } 256 257 } 258 #endif 259 260 static int nv_asic_mode1_reset(struct amdgpu_device *adev) 261 { 262 u32 i; 263 int ret = 0; 264 265 amdgpu_atombios_scratch_regs_engine_hung(adev, true); 266 267 dev_info(adev->dev, "GPU mode1 reset\n"); 268 269 /* disable BM */ 270 pci_clear_master(adev->pdev); 271 272 pci_save_state(adev->pdev); 273 274 ret = psp_gpu_reset(adev); 275 if (ret) 276 dev_err(adev->dev, "GPU mode1 reset failed\n"); 277 278 pci_restore_state(adev->pdev); 279 280 /* wait for asic to come out of reset */ 281 for (i = 0; i < adev->usec_timeout; i++) { 282 u32 memsize = adev->nbio_funcs->get_memsize(adev); 283 284 if (memsize != 0xffffffff) 285 break; 286 udelay(1); 287 } 288 289 amdgpu_atombios_scratch_regs_engine_hung(adev, false); 290 291 return ret; 292 } 293 294 static enum amd_reset_method 295 nv_asic_reset_method(struct amdgpu_device *adev) 296 { 297 struct smu_context *smu = &adev->smu; 298 299 if (smu_baco_is_support(smu)) 300 return AMD_RESET_METHOD_BACO; 301 else 302 return AMD_RESET_METHOD_MODE1; 303 } 304 305 static int nv_asic_reset(struct amdgpu_device *adev) 306 { 307 308 /* FIXME: it doesn't work since vega10 */ 309 #if 0 310 amdgpu_atombios_scratch_regs_engine_hung(adev, true); 311 312 nv_gpu_pci_config_reset(adev); 313 314 amdgpu_atombios_scratch_regs_engine_hung(adev, false); 315 #endif 316 int ret = 0; 317 struct smu_context *smu = &adev->smu; 318 319 if (nv_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) 320 ret = smu_baco_reset(smu); 321 else 322 ret = nv_asic_mode1_reset(adev); 323 324 return ret; 325 } 326 327 static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 328 { 329 /* todo */ 330 return 0; 331 } 332 333 static int nv_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 334 { 335 /* todo */ 336 return 0; 337 } 338 339 static void nv_pcie_gen3_enable(struct amdgpu_device *adev) 340 { 341 if (pci_is_root_bus(adev->pdev->bus)) 342 return; 343 344 if (amdgpu_pcie_gen2 == 0) 345 return; 346 347 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | 348 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3))) 349 return; 350 351 /* todo */ 352 } 353 354 static void nv_program_aspm(struct amdgpu_device *adev) 355 { 356 357 if (amdgpu_aspm == 0) 358 return; 359 360 /* todo */ 361 } 362 363 static void nv_enable_doorbell_aperture(struct amdgpu_device *adev, 364 bool enable) 365 { 366 adev->nbio_funcs->enable_doorbell_aperture(adev, enable); 367 adev->nbio_funcs->enable_doorbell_selfring_aperture(adev, enable); 368 } 369 370 static const struct amdgpu_ip_block_version nv_common_ip_block = 371 { 372 .type = AMD_IP_BLOCK_TYPE_COMMON, 373 .major = 1, 374 .minor = 0, 375 .rev = 0, 376 .funcs = &nv_common_ip_funcs, 377 }; 378 379 static int nv_reg_base_init(struct amdgpu_device *adev) 380 { 381 int r; 382 383 if (amdgpu_discovery) { 384 r = amdgpu_discovery_reg_base_init(adev); 385 if (r) { 386 DRM_WARN("failed to init reg base from ip discovery table, " 387 "fallback to legacy init method\n"); 388 goto legacy_init; 389 } 390 391 return 0; 392 } 393 394 legacy_init: 395 switch (adev->asic_type) { 396 case CHIP_NAVI10: 397 navi10_reg_base_init(adev); 398 break; 399 case CHIP_NAVI14: 400 navi14_reg_base_init(adev); 401 break; 402 case CHIP_NAVI12: 403 navi12_reg_base_init(adev); 404 break; 405 default: 406 return -EINVAL; 407 } 408 409 return 0; 410 } 411 412 int nv_set_ip_blocks(struct amdgpu_device *adev) 413 { 414 int r; 415 416 /* Set IP register base before any HW register access */ 417 r = nv_reg_base_init(adev); 418 if (r) 419 return r; 420 421 adev->nbio_funcs = &nbio_v2_3_funcs; 422 423 adev->nbio_funcs->detect_hw_virt(adev); 424 425 switch (adev->asic_type) { 426 case CHIP_NAVI10: 427 case CHIP_NAVI14: 428 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 429 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 430 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 431 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 432 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 433 is_support_sw_smu(adev)) 434 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 435 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 436 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 437 #if defined(CONFIG_DRM_AMD_DC) 438 else if (amdgpu_device_has_dc_support(adev)) 439 amdgpu_device_ip_block_add(adev, &dm_ip_block); 440 #endif 441 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 442 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 443 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 444 is_support_sw_smu(adev)) 445 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 446 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 447 if (adev->enable_mes) 448 amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block); 449 break; 450 case CHIP_NAVI12: 451 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 452 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 453 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 454 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 455 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 456 is_support_sw_smu(adev)) 457 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 458 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 459 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 460 else if (amdgpu_device_has_dc_support(adev)) 461 amdgpu_device_ip_block_add(adev, &dm_ip_block); 462 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 463 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 464 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 465 is_support_sw_smu(adev)) 466 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 467 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 468 break; 469 default: 470 return -EINVAL; 471 } 472 473 return 0; 474 } 475 476 static uint32_t nv_get_rev_id(struct amdgpu_device *adev) 477 { 478 return adev->nbio_funcs->get_rev_id(adev); 479 } 480 481 static void nv_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring) 482 { 483 adev->nbio_funcs->hdp_flush(adev, ring); 484 } 485 486 static void nv_invalidate_hdp(struct amdgpu_device *adev, 487 struct amdgpu_ring *ring) 488 { 489 if (!ring || !ring->funcs->emit_wreg) { 490 WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_READ_CACHE_INVALIDATE, 1); 491 } else { 492 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET( 493 HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1); 494 } 495 } 496 497 static bool nv_need_full_reset(struct amdgpu_device *adev) 498 { 499 return true; 500 } 501 502 static void nv_get_pcie_usage(struct amdgpu_device *adev, 503 uint64_t *count0, 504 uint64_t *count1) 505 { 506 /*TODO*/ 507 } 508 509 static bool nv_need_reset_on_init(struct amdgpu_device *adev) 510 { 511 #if 0 512 u32 sol_reg; 513 514 if (adev->flags & AMD_IS_APU) 515 return false; 516 517 /* Check sOS sign of life register to confirm sys driver and sOS 518 * are already been loaded. 519 */ 520 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 521 if (sol_reg) 522 return true; 523 #endif 524 /* TODO: re-enable it when mode1 reset is functional */ 525 return false; 526 } 527 528 static void nv_init_doorbell_index(struct amdgpu_device *adev) 529 { 530 adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ; 531 adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0; 532 adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1; 533 adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2; 534 adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3; 535 adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4; 536 adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5; 537 adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6; 538 adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7; 539 adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START; 540 adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END; 541 adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0; 542 adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1; 543 adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0; 544 adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1; 545 adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH; 546 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1; 547 adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3; 548 adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5; 549 adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7; 550 adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP; 551 adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP; 552 553 adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1; 554 adev->doorbell_index.sdma_doorbell_range = 20; 555 } 556 557 static const struct amdgpu_asic_funcs nv_asic_funcs = 558 { 559 .read_disabled_bios = &nv_read_disabled_bios, 560 .read_bios_from_rom = &nv_read_bios_from_rom, 561 .read_register = &nv_read_register, 562 .reset = &nv_asic_reset, 563 .reset_method = &nv_asic_reset_method, 564 .set_vga_state = &nv_vga_set_state, 565 .get_xclk = &nv_get_xclk, 566 .set_uvd_clocks = &nv_set_uvd_clocks, 567 .set_vce_clocks = &nv_set_vce_clocks, 568 .get_config_memsize = &nv_get_config_memsize, 569 .flush_hdp = &nv_flush_hdp, 570 .invalidate_hdp = &nv_invalidate_hdp, 571 .init_doorbell_index = &nv_init_doorbell_index, 572 .need_full_reset = &nv_need_full_reset, 573 .get_pcie_usage = &nv_get_pcie_usage, 574 .need_reset_on_init = &nv_need_reset_on_init, 575 }; 576 577 static int nv_common_early_init(void *handle) 578 { 579 bool psp_enabled = false; 580 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 581 582 adev->smc_rreg = NULL; 583 adev->smc_wreg = NULL; 584 adev->pcie_rreg = &nv_pcie_rreg; 585 adev->pcie_wreg = &nv_pcie_wreg; 586 587 /* TODO: will add them during VCN v2 implementation */ 588 adev->uvd_ctx_rreg = NULL; 589 adev->uvd_ctx_wreg = NULL; 590 591 adev->didt_rreg = &nv_didt_rreg; 592 adev->didt_wreg = &nv_didt_wreg; 593 594 adev->asic_funcs = &nv_asic_funcs; 595 596 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP) && 597 (amdgpu_ip_block_mask & (1 << AMD_IP_BLOCK_TYPE_PSP))) 598 psp_enabled = true; 599 600 adev->rev_id = nv_get_rev_id(adev); 601 adev->external_rev_id = 0xff; 602 switch (adev->asic_type) { 603 case CHIP_NAVI10: 604 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 605 AMD_CG_SUPPORT_GFX_CGCG | 606 AMD_CG_SUPPORT_IH_CG | 607 AMD_CG_SUPPORT_HDP_MGCG | 608 AMD_CG_SUPPORT_HDP_LS | 609 AMD_CG_SUPPORT_SDMA_MGCG | 610 AMD_CG_SUPPORT_SDMA_LS | 611 AMD_CG_SUPPORT_MC_MGCG | 612 AMD_CG_SUPPORT_MC_LS | 613 AMD_CG_SUPPORT_ATHUB_MGCG | 614 AMD_CG_SUPPORT_ATHUB_LS | 615 AMD_CG_SUPPORT_VCN_MGCG | 616 AMD_CG_SUPPORT_BIF_MGCG | 617 AMD_CG_SUPPORT_BIF_LS; 618 adev->pg_flags = AMD_PG_SUPPORT_VCN | 619 AMD_PG_SUPPORT_VCN_DPG | 620 AMD_PG_SUPPORT_MMHUB | 621 AMD_PG_SUPPORT_ATHUB; 622 adev->external_rev_id = adev->rev_id + 0x1; 623 break; 624 case CHIP_NAVI14: 625 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 626 AMD_CG_SUPPORT_GFX_CGCG | 627 AMD_CG_SUPPORT_IH_CG | 628 AMD_CG_SUPPORT_HDP_MGCG | 629 AMD_CG_SUPPORT_HDP_LS | 630 AMD_CG_SUPPORT_SDMA_MGCG | 631 AMD_CG_SUPPORT_SDMA_LS | 632 AMD_CG_SUPPORT_MC_MGCG | 633 AMD_CG_SUPPORT_MC_LS | 634 AMD_CG_SUPPORT_ATHUB_MGCG | 635 AMD_CG_SUPPORT_ATHUB_LS | 636 AMD_CG_SUPPORT_VCN_MGCG | 637 AMD_CG_SUPPORT_BIF_MGCG | 638 AMD_CG_SUPPORT_BIF_LS; 639 adev->pg_flags = AMD_PG_SUPPORT_VCN | 640 AMD_PG_SUPPORT_VCN_DPG; 641 adev->external_rev_id = adev->rev_id + 20; 642 break; 643 case CHIP_NAVI12: 644 adev->cg_flags = 0; 645 adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG; 646 adev->external_rev_id = adev->rev_id + 0xa; 647 break; 648 default: 649 /* FIXME: not supported yet */ 650 return -EINVAL; 651 } 652 653 return 0; 654 } 655 656 static int nv_common_late_init(void *handle) 657 { 658 return 0; 659 } 660 661 static int nv_common_sw_init(void *handle) 662 { 663 return 0; 664 } 665 666 static int nv_common_sw_fini(void *handle) 667 { 668 return 0; 669 } 670 671 static int nv_common_hw_init(void *handle) 672 { 673 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 674 675 /* enable pcie gen2/3 link */ 676 nv_pcie_gen3_enable(adev); 677 /* enable aspm */ 678 nv_program_aspm(adev); 679 /* setup nbio registers */ 680 adev->nbio_funcs->init_registers(adev); 681 /* enable the doorbell aperture */ 682 nv_enable_doorbell_aperture(adev, true); 683 684 return 0; 685 } 686 687 static int nv_common_hw_fini(void *handle) 688 { 689 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 690 691 /* disable the doorbell aperture */ 692 nv_enable_doorbell_aperture(adev, false); 693 694 return 0; 695 } 696 697 static int nv_common_suspend(void *handle) 698 { 699 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 700 701 return nv_common_hw_fini(adev); 702 } 703 704 static int nv_common_resume(void *handle) 705 { 706 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 707 708 return nv_common_hw_init(adev); 709 } 710 711 static bool nv_common_is_idle(void *handle) 712 { 713 return true; 714 } 715 716 static int nv_common_wait_for_idle(void *handle) 717 { 718 return 0; 719 } 720 721 static int nv_common_soft_reset(void *handle) 722 { 723 return 0; 724 } 725 726 static void nv_update_hdp_mem_power_gating(struct amdgpu_device *adev, 727 bool enable) 728 { 729 uint32_t hdp_clk_cntl, hdp_clk_cntl1; 730 uint32_t hdp_mem_pwr_cntl; 731 732 if (!(adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | 733 AMD_CG_SUPPORT_HDP_DS | 734 AMD_CG_SUPPORT_HDP_SD))) 735 return; 736 737 hdp_clk_cntl = hdp_clk_cntl1 = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); 738 hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL); 739 740 /* Before doing clock/power mode switch, 741 * forced on IPH & RC clock */ 742 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL, 743 IPH_MEM_CLK_SOFT_OVERRIDE, 1); 744 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL, 745 RC_MEM_CLK_SOFT_OVERRIDE, 1); 746 WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl); 747 748 /* HDP 5.0 doesn't support dynamic power mode switch, 749 * disable clock and power gating before any changing */ 750 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 751 IPH_MEM_POWER_CTRL_EN, 0); 752 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 753 IPH_MEM_POWER_LS_EN, 0); 754 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 755 IPH_MEM_POWER_DS_EN, 0); 756 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 757 IPH_MEM_POWER_SD_EN, 0); 758 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 759 RC_MEM_POWER_CTRL_EN, 0); 760 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 761 RC_MEM_POWER_LS_EN, 0); 762 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 763 RC_MEM_POWER_DS_EN, 0); 764 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL, 765 RC_MEM_POWER_SD_EN, 0); 766 WREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); 767 768 /* only one clock gating mode (LS/DS/SD) can be enabled */ 769 if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) { 770 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 771 HDP_MEM_POWER_CTRL, 772 IPH_MEM_POWER_LS_EN, enable); 773 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 774 HDP_MEM_POWER_CTRL, 775 RC_MEM_POWER_LS_EN, enable); 776 } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_DS) { 777 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 778 HDP_MEM_POWER_CTRL, 779 IPH_MEM_POWER_DS_EN, enable); 780 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 781 HDP_MEM_POWER_CTRL, 782 RC_MEM_POWER_DS_EN, enable); 783 } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_SD) { 784 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 785 HDP_MEM_POWER_CTRL, 786 IPH_MEM_POWER_SD_EN, enable); 787 /* RC should not use shut down mode, fallback to ds */ 788 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, 789 HDP_MEM_POWER_CTRL, 790 RC_MEM_POWER_DS_EN, enable); 791 } 792 793 WREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); 794 795 /* restore IPH & RC clock override after clock/power mode changing */ 796 WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl1); 797 } 798 799 static void nv_update_hdp_clock_gating(struct amdgpu_device *adev, 800 bool enable) 801 { 802 uint32_t hdp_clk_cntl; 803 804 if (!(adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG)) 805 return; 806 807 hdp_clk_cntl = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); 808 809 if (enable) { 810 hdp_clk_cntl &= 811 ~(uint32_t) 812 (HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK | 813 HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK | 814 HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK | 815 HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK | 816 HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK | 817 HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK); 818 } else { 819 hdp_clk_cntl |= HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK | 820 HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK | 821 HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK | 822 HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK | 823 HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK | 824 HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK; 825 } 826 827 WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl); 828 } 829 830 static int nv_common_set_clockgating_state(void *handle, 831 enum amd_clockgating_state state) 832 { 833 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 834 835 if (amdgpu_sriov_vf(adev)) 836 return 0; 837 838 switch (adev->asic_type) { 839 case CHIP_NAVI10: 840 case CHIP_NAVI14: 841 case CHIP_NAVI12: 842 adev->nbio_funcs->update_medium_grain_clock_gating(adev, 843 state == AMD_CG_STATE_GATE ? true : false); 844 adev->nbio_funcs->update_medium_grain_light_sleep(adev, 845 state == AMD_CG_STATE_GATE ? true : false); 846 nv_update_hdp_mem_power_gating(adev, 847 state == AMD_CG_STATE_GATE ? true : false); 848 nv_update_hdp_clock_gating(adev, 849 state == AMD_CG_STATE_GATE ? true : false); 850 break; 851 default: 852 break; 853 } 854 return 0; 855 } 856 857 static int nv_common_set_powergating_state(void *handle, 858 enum amd_powergating_state state) 859 { 860 /* TODO */ 861 return 0; 862 } 863 864 static void nv_common_get_clockgating_state(void *handle, u32 *flags) 865 { 866 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 867 uint32_t tmp; 868 869 if (amdgpu_sriov_vf(adev)) 870 *flags = 0; 871 872 adev->nbio_funcs->get_clockgating_state(adev, flags); 873 874 /* AMD_CG_SUPPORT_HDP_MGCG */ 875 tmp = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); 876 if (!(tmp & (HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK | 877 HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK | 878 HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK | 879 HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK | 880 HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK | 881 HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK))) 882 *flags |= AMD_CG_SUPPORT_HDP_MGCG; 883 884 /* AMD_CG_SUPPORT_HDP_LS/DS/SD */ 885 tmp = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL); 886 if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK) 887 *flags |= AMD_CG_SUPPORT_HDP_LS; 888 else if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_DS_EN_MASK) 889 *flags |= AMD_CG_SUPPORT_HDP_DS; 890 else if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_SD_EN_MASK) 891 *flags |= AMD_CG_SUPPORT_HDP_SD; 892 893 return; 894 } 895 896 static const struct amd_ip_funcs nv_common_ip_funcs = { 897 .name = "nv_common", 898 .early_init = nv_common_early_init, 899 .late_init = nv_common_late_init, 900 .sw_init = nv_common_sw_init, 901 .sw_fini = nv_common_sw_fini, 902 .hw_init = nv_common_hw_init, 903 .hw_fini = nv_common_hw_fini, 904 .suspend = nv_common_suspend, 905 .resume = nv_common_resume, 906 .is_idle = nv_common_is_idle, 907 .wait_for_idle = nv_common_wait_for_idle, 908 .soft_reset = nv_common_soft_reset, 909 .set_clockgating_state = nv_common_set_clockgating_state, 910 .set_powergating_state = nv_common_set_powergating_state, 911 .get_clockgating_state = nv_common_get_clockgating_state, 912 }; 913