1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/slab.h> 25 #include <linux/module.h> 26 #include <linux/pci.h> 27 28 #include <drm/amdgpu_drm.h> 29 30 #include "amdgpu.h" 31 #include "amdgpu_atombios.h" 32 #include "amdgpu_ih.h" 33 #include "amdgpu_uvd.h" 34 #include "amdgpu_vce.h" 35 #include "amdgpu_ucode.h" 36 #include "amdgpu_psp.h" 37 #include "atom.h" 38 #include "amd_pcie.h" 39 #include "amdgpu_video_codecs.h" 40 41 #include "gc/gc_10_1_0_offset.h" 42 #include "gc/gc_10_1_0_sh_mask.h" 43 #include "mp/mp_11_0_offset.h" 44 45 #include "soc15.h" 46 #include "soc15_common.h" 47 #include "gmc_v10_0.h" 48 #include "gfxhub_v2_0.h" 49 #include "mmhub_v2_0.h" 50 #include "nbio_v2_3.h" 51 #include "nbio_v7_2.h" 52 #include "hdp_v5_0.h" 53 #include "nv.h" 54 #include "navi10_ih.h" 55 #include "gfx_v10_0.h" 56 #include "sdma_v5_0.h" 57 #include "sdma_v5_2.h" 58 #include "vcn_v2_0.h" 59 #include "jpeg_v2_0.h" 60 #include "vcn_v3_0.h" 61 #include "jpeg_v3_0.h" 62 #include "amdgpu_vkms.h" 63 #include "mxgpu_nv.h" 64 #include "smuio_v11_0.h" 65 #include "smuio_v11_0_6.h" 66 67 static const struct amd_ip_funcs nv_common_ip_funcs; 68 69 /* Navi */ 70 static const struct amdgpu_video_codec_info nv_video_codecs_encode_array[] = { 71 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)}, 72 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 4096, 0)}, 73 }; 74 75 static const struct amdgpu_video_codecs nv_video_codecs_encode = { 76 .codec_count = ARRAY_SIZE(nv_video_codecs_encode_array), 77 .codec_array = nv_video_codecs_encode_array, 78 }; 79 80 /* Navi1x */ 81 static const struct amdgpu_video_codec_info nv_video_codecs_decode_array[] = { 82 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 1920, 1088, 3)}, 83 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 1920, 1088, 5)}, 84 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 85 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 1920, 1088, 4)}, 86 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 87 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 8192, 8192, 0)}, 88 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 89 }; 90 91 static const struct amdgpu_video_codecs nv_video_codecs_decode = { 92 .codec_count = ARRAY_SIZE(nv_video_codecs_decode_array), 93 .codec_array = nv_video_codecs_decode_array, 94 }; 95 96 /* Sienna Cichlid */ 97 static const struct amdgpu_video_codec_info sc_video_codecs_encode_array[] = { 98 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)}, 99 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)}, 100 }; 101 102 static const struct amdgpu_video_codecs sc_video_codecs_encode = { 103 .codec_count = ARRAY_SIZE(sc_video_codecs_encode_array), 104 .codec_array = sc_video_codecs_encode_array, 105 }; 106 107 static const struct amdgpu_video_codec_info sc_video_codecs_decode_array_vcn0[] = { 108 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 1920, 1088, 3)}, 109 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 1920, 1088, 5)}, 110 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 111 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 1920, 1088, 4)}, 112 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 113 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)}, 114 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 115 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 116 }; 117 118 static const struct amdgpu_video_codec_info sc_video_codecs_decode_array_vcn1[] = { 119 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 1920, 1088, 3)}, 120 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 1920, 1088, 5)}, 121 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 122 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 1920, 1088, 4)}, 123 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 124 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)}, 125 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 126 }; 127 128 static const struct amdgpu_video_codecs sc_video_codecs_decode_vcn0 = { 129 .codec_count = ARRAY_SIZE(sc_video_codecs_decode_array_vcn0), 130 .codec_array = sc_video_codecs_decode_array_vcn0, 131 }; 132 133 static const struct amdgpu_video_codecs sc_video_codecs_decode_vcn1 = { 134 .codec_count = ARRAY_SIZE(sc_video_codecs_decode_array_vcn1), 135 .codec_array = sc_video_codecs_decode_array_vcn1, 136 }; 137 138 /* SRIOV Sienna Cichlid, not const since data is controlled by host */ 139 static struct amdgpu_video_codec_info sriov_sc_video_codecs_encode_array[] = { 140 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 0)}, 141 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)}, 142 }; 143 144 static struct amdgpu_video_codec_info sriov_sc_video_codecs_decode_array_vcn0[] = { 145 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 1920, 1088, 3)}, 146 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 1920, 1088, 5)}, 147 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 148 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 1920, 1088, 4)}, 149 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 150 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)}, 151 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 152 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 153 }; 154 155 static struct amdgpu_video_codec_info sriov_sc_video_codecs_decode_array_vcn1[] = { 156 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 1920, 1088, 3)}, 157 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 1920, 1088, 5)}, 158 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 159 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 1920, 1088, 4)}, 160 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 161 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)}, 162 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 163 }; 164 165 static struct amdgpu_video_codecs sriov_sc_video_codecs_encode = { 166 .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_encode_array), 167 .codec_array = sriov_sc_video_codecs_encode_array, 168 }; 169 170 static struct amdgpu_video_codecs sriov_sc_video_codecs_decode_vcn0 = { 171 .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_decode_array_vcn0), 172 .codec_array = sriov_sc_video_codecs_decode_array_vcn0, 173 }; 174 175 static struct amdgpu_video_codecs sriov_sc_video_codecs_decode_vcn1 = { 176 .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_decode_array_vcn1), 177 .codec_array = sriov_sc_video_codecs_decode_array_vcn1, 178 }; 179 180 /* Beige Goby*/ 181 static const struct amdgpu_video_codec_info bg_video_codecs_decode_array[] = { 182 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 183 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 184 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 185 }; 186 187 static const struct amdgpu_video_codecs bg_video_codecs_decode = { 188 .codec_count = ARRAY_SIZE(bg_video_codecs_decode_array), 189 .codec_array = bg_video_codecs_decode_array, 190 }; 191 192 static const struct amdgpu_video_codecs bg_video_codecs_encode = { 193 .codec_count = 0, 194 .codec_array = NULL, 195 }; 196 197 /* Yellow Carp*/ 198 static const struct amdgpu_video_codec_info yc_video_codecs_decode_array[] = { 199 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 200 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 201 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 202 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)}, 203 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 204 }; 205 206 static const struct amdgpu_video_codecs yc_video_codecs_decode = { 207 .codec_count = ARRAY_SIZE(yc_video_codecs_decode_array), 208 .codec_array = yc_video_codecs_decode_array, 209 }; 210 211 static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode, 212 const struct amdgpu_video_codecs **codecs) 213 { 214 if (adev->vcn.num_vcn_inst == hweight8(adev->vcn.harvest_config)) 215 return -EINVAL; 216 217 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) { 218 case IP_VERSION(3, 0, 0): 219 case IP_VERSION(3, 0, 64): 220 case IP_VERSION(3, 0, 192): 221 if (amdgpu_sriov_vf(adev)) { 222 if (adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) { 223 if (encode) 224 *codecs = &sriov_sc_video_codecs_encode; 225 else 226 *codecs = &sriov_sc_video_codecs_decode_vcn1; 227 } else { 228 if (encode) 229 *codecs = &sriov_sc_video_codecs_encode; 230 else 231 *codecs = &sriov_sc_video_codecs_decode_vcn0; 232 } 233 } else { 234 if (adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) { 235 if (encode) 236 *codecs = &sc_video_codecs_encode; 237 else 238 *codecs = &sc_video_codecs_decode_vcn1; 239 } else { 240 if (encode) 241 *codecs = &sc_video_codecs_encode; 242 else 243 *codecs = &sc_video_codecs_decode_vcn0; 244 } 245 } 246 return 0; 247 case IP_VERSION(3, 0, 16): 248 case IP_VERSION(3, 0, 2): 249 if (encode) 250 *codecs = &sc_video_codecs_encode; 251 else 252 *codecs = &sc_video_codecs_decode_vcn0; 253 return 0; 254 case IP_VERSION(3, 1, 1): 255 case IP_VERSION(3, 1, 2): 256 if (encode) 257 *codecs = &sc_video_codecs_encode; 258 else 259 *codecs = &yc_video_codecs_decode; 260 return 0; 261 case IP_VERSION(3, 0, 33): 262 if (encode) 263 *codecs = &bg_video_codecs_encode; 264 else 265 *codecs = &bg_video_codecs_decode; 266 return 0; 267 case IP_VERSION(2, 0, 0): 268 case IP_VERSION(2, 0, 2): 269 if (encode) 270 *codecs = &nv_video_codecs_encode; 271 else 272 *codecs = &nv_video_codecs_decode; 273 return 0; 274 default: 275 return -EINVAL; 276 } 277 } 278 279 static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg) 280 { 281 unsigned long flags, address, data; 282 u32 r; 283 284 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 285 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 286 287 spin_lock_irqsave(&adev->reg.didt.lock, flags); 288 WREG32(address, (reg)); 289 r = RREG32(data); 290 spin_unlock_irqrestore(&adev->reg.didt.lock, flags); 291 return r; 292 } 293 294 static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 295 { 296 unsigned long flags, address, data; 297 298 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 299 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 300 301 spin_lock_irqsave(&adev->reg.didt.lock, flags); 302 WREG32(address, (reg)); 303 WREG32(data, (v)); 304 spin_unlock_irqrestore(&adev->reg.didt.lock, flags); 305 } 306 307 static u32 nv_get_config_memsize(struct amdgpu_device *adev) 308 { 309 return adev->nbio.funcs->get_memsize(adev); 310 } 311 312 static u32 nv_get_xclk(struct amdgpu_device *adev) 313 { 314 return adev->clock.spll.reference_freq; 315 } 316 317 318 void nv_grbm_select(struct amdgpu_device *adev, 319 u32 me, u32 pipe, u32 queue, u32 vmid) 320 { 321 u32 grbm_gfx_cntl = 0; 322 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); 323 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); 324 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); 325 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); 326 327 WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl); 328 } 329 330 static bool nv_read_disabled_bios(struct amdgpu_device *adev) 331 { 332 /* todo */ 333 return false; 334 } 335 336 static struct soc15_allowed_register_entry nv_allowed_read_registers[] = { 337 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)}, 338 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)}, 339 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)}, 340 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)}, 341 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)}, 342 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)}, 343 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)}, 344 { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)}, 345 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)}, 346 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)}, 347 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)}, 348 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)}, 349 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)}, 350 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)}, 351 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)}, 352 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)}, 353 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)}, 354 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)}, 355 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)}, 356 }; 357 358 static uint32_t nv_get_register_value(struct amdgpu_device *adev, 359 bool indexed, u32 se_num, 360 u32 sh_num, u32 reg_offset) 361 { 362 if (indexed) { 363 return amdgpu_read_indexed_register(adev, se_num, sh_num, reg_offset); 364 } else { 365 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) 366 return adev->gfx.config.gb_addr_config; 367 return RREG32(reg_offset); 368 } 369 } 370 371 static int nv_read_register(struct amdgpu_device *adev, u32 se_num, 372 u32 sh_num, u32 reg_offset, u32 *value) 373 { 374 uint32_t i; 375 struct soc15_allowed_register_entry *en; 376 377 *value = 0; 378 for (i = 0; i < ARRAY_SIZE(nv_allowed_read_registers); i++) { 379 en = &nv_allowed_read_registers[i]; 380 if (!adev->reg_offset[en->hwip][en->inst]) 381 continue; 382 else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg] 383 + en->reg_offset)) 384 continue; 385 386 *value = nv_get_register_value(adev, 387 nv_allowed_read_registers[i].grbm_indexed, 388 se_num, sh_num, reg_offset); 389 return 0; 390 } 391 return -EINVAL; 392 } 393 394 static int nv_asic_mode2_reset(struct amdgpu_device *adev) 395 { 396 u32 i; 397 int ret = 0; 398 399 amdgpu_atombios_scratch_regs_engine_hung(adev, true); 400 401 /* disable BM */ 402 pci_clear_master(adev->pdev); 403 404 amdgpu_device_cache_pci_state(adev->pdev); 405 406 ret = amdgpu_dpm_mode2_reset(adev); 407 if (ret) 408 dev_err(adev->dev, "GPU mode2 reset failed\n"); 409 410 amdgpu_device_load_pci_state(adev->pdev); 411 412 /* wait for asic to come out of reset */ 413 for (i = 0; i < adev->usec_timeout; i++) { 414 u32 memsize = adev->nbio.funcs->get_memsize(adev); 415 416 if (memsize != 0xffffffff) 417 break; 418 udelay(1); 419 } 420 421 amdgpu_atombios_scratch_regs_engine_hung(adev, false); 422 423 return ret; 424 } 425 426 static enum amd_reset_method 427 nv_asic_reset_method(struct amdgpu_device *adev) 428 { 429 if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 || 430 amdgpu_reset_method == AMD_RESET_METHOD_MODE2 || 431 amdgpu_reset_method == AMD_RESET_METHOD_BACO || 432 amdgpu_reset_method == AMD_RESET_METHOD_PCI) 433 return amdgpu_reset_method; 434 435 if (amdgpu_reset_method != -1) 436 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", 437 amdgpu_reset_method); 438 439 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 440 case IP_VERSION(11, 5, 0): 441 case IP_VERSION(11, 5, 2): 442 case IP_VERSION(13, 0, 1): 443 case IP_VERSION(13, 0, 3): 444 case IP_VERSION(13, 0, 5): 445 case IP_VERSION(13, 0, 8): 446 return AMD_RESET_METHOD_MODE2; 447 case IP_VERSION(11, 0, 7): 448 case IP_VERSION(11, 0, 11): 449 case IP_VERSION(11, 0, 12): 450 case IP_VERSION(11, 0, 13): 451 return AMD_RESET_METHOD_MODE1; 452 default: 453 if (amdgpu_dpm_is_baco_supported(adev)) 454 return AMD_RESET_METHOD_BACO; 455 else 456 return AMD_RESET_METHOD_MODE1; 457 } 458 } 459 460 static int nv_asic_reset(struct amdgpu_device *adev) 461 { 462 int ret = 0; 463 464 switch (nv_asic_reset_method(adev)) { 465 case AMD_RESET_METHOD_PCI: 466 dev_info(adev->dev, "PCI reset\n"); 467 ret = amdgpu_device_pci_reset(adev); 468 break; 469 case AMD_RESET_METHOD_BACO: 470 dev_info(adev->dev, "BACO reset\n"); 471 ret = amdgpu_dpm_baco_reset(adev); 472 break; 473 case AMD_RESET_METHOD_MODE2: 474 dev_info(adev->dev, "MODE2 reset\n"); 475 ret = nv_asic_mode2_reset(adev); 476 break; 477 default: 478 dev_info(adev->dev, "MODE1 reset\n"); 479 ret = amdgpu_device_mode1_reset(adev); 480 break; 481 } 482 483 return ret; 484 } 485 486 static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 487 { 488 /* todo */ 489 return 0; 490 } 491 492 static int nv_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 493 { 494 /* todo */ 495 return 0; 496 } 497 498 const struct amdgpu_ip_block_version nv_common_ip_block = { 499 .type = AMD_IP_BLOCK_TYPE_COMMON, 500 .major = 1, 501 .minor = 0, 502 .rev = 0, 503 .funcs = &nv_common_ip_funcs, 504 }; 505 506 void nv_set_virt_ops(struct amdgpu_device *adev) 507 { 508 adev->virt.ops = &xgpu_nv_virt_ops; 509 } 510 511 static bool nv_need_reset_on_init(struct amdgpu_device *adev) 512 { 513 u32 sol_reg; 514 515 if (adev->flags & AMD_IS_APU) 516 return false; 517 518 /* Check sOS sign of life register to confirm sys driver and sOS 519 * are already been loaded. 520 */ 521 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 522 if (sol_reg) 523 return true; 524 525 return false; 526 } 527 528 static void nv_init_doorbell_index(struct amdgpu_device *adev) 529 { 530 adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ; 531 adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0; 532 adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1; 533 adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2; 534 adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3; 535 adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4; 536 adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5; 537 adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6; 538 adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7; 539 adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START; 540 adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END; 541 adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0; 542 adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1; 543 adev->doorbell_index.gfx_userqueue_start = 544 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_START; 545 adev->doorbell_index.gfx_userqueue_end = 546 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_END; 547 adev->doorbell_index.mes_ring0 = AMDGPU_NAVI10_DOORBELL_MES_RING0; 548 adev->doorbell_index.mes_ring1 = AMDGPU_NAVI10_DOORBELL_MES_RING1; 549 adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0; 550 adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1; 551 adev->doorbell_index.sdma_engine[2] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2; 552 adev->doorbell_index.sdma_engine[3] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3; 553 adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH; 554 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1; 555 adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3; 556 adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5; 557 adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7; 558 adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP; 559 adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP; 560 561 adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1; 562 adev->doorbell_index.sdma_doorbell_range = 20; 563 } 564 565 static int nv_update_umd_stable_pstate(struct amdgpu_device *adev, 566 bool enter) 567 { 568 if (enter) 569 amdgpu_gfx_rlc_enter_safe_mode(adev, 0); 570 else 571 amdgpu_gfx_rlc_exit_safe_mode(adev, 0); 572 573 if (adev->gfx.funcs->update_perfmon_mgcg) 574 adev->gfx.funcs->update_perfmon_mgcg(adev, !enter); 575 576 if (adev->nbio.funcs->enable_aspm && 577 amdgpu_device_should_use_aspm(adev)) 578 adev->nbio.funcs->enable_aspm(adev, !enter); 579 580 return 0; 581 } 582 583 static const struct amdgpu_asic_funcs nv_asic_funcs = { 584 .read_disabled_bios = &nv_read_disabled_bios, 585 .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom, 586 .read_register = &nv_read_register, 587 .reset = &nv_asic_reset, 588 .reset_method = &nv_asic_reset_method, 589 .get_xclk = &nv_get_xclk, 590 .set_uvd_clocks = &nv_set_uvd_clocks, 591 .set_vce_clocks = &nv_set_vce_clocks, 592 .get_config_memsize = &nv_get_config_memsize, 593 .init_doorbell_index = &nv_init_doorbell_index, 594 .need_reset_on_init = &nv_need_reset_on_init, 595 .get_pcie_replay_count = &amdgpu_nbio_get_pcie_replay_count, 596 .supports_baco = &amdgpu_dpm_is_baco_supported, 597 .update_umd_stable_pstate = &nv_update_umd_stable_pstate, 598 .query_video_codecs = &nv_query_video_codecs, 599 }; 600 601 static int nv_common_early_init(struct amdgpu_ip_block *ip_block) 602 { 603 struct amdgpu_device *adev = ip_block->adev; 604 605 adev->nbio.funcs->set_reg_remap(adev); 606 adev->reg.pcie.rreg = &amdgpu_device_indirect_rreg; 607 adev->reg.pcie.wreg = &amdgpu_device_indirect_wreg; 608 adev->reg.pcie.rreg64 = &amdgpu_device_indirect_rreg64; 609 adev->reg.pcie.wreg64 = &amdgpu_device_indirect_wreg64; 610 adev->reg.pcie.port_rreg = &amdgpu_device_pcie_port_rreg; 611 adev->reg.pcie.port_wreg = &amdgpu_device_pcie_port_wreg; 612 613 adev->reg.didt.rreg = &nv_didt_rreg; 614 adev->reg.didt.wreg = &nv_didt_wreg; 615 616 adev->asic_funcs = &nv_asic_funcs; 617 618 adev->rev_id = amdgpu_device_get_rev_id(adev); 619 adev->external_rev_id = 0xff; 620 /* TODO: split the GC and PG flags based on the relevant IP version for which 621 * they are relevant. 622 */ 623 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 624 case IP_VERSION(10, 1, 10): 625 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 626 AMD_CG_SUPPORT_GFX_CGCG | 627 AMD_CG_SUPPORT_IH_CG | 628 AMD_CG_SUPPORT_HDP_MGCG | 629 AMD_CG_SUPPORT_HDP_LS | 630 AMD_CG_SUPPORT_SDMA_MGCG | 631 AMD_CG_SUPPORT_SDMA_LS | 632 AMD_CG_SUPPORT_MC_MGCG | 633 AMD_CG_SUPPORT_MC_LS | 634 AMD_CG_SUPPORT_ATHUB_MGCG | 635 AMD_CG_SUPPORT_ATHUB_LS | 636 AMD_CG_SUPPORT_VCN_MGCG | 637 AMD_CG_SUPPORT_JPEG_MGCG | 638 AMD_CG_SUPPORT_BIF_MGCG | 639 AMD_CG_SUPPORT_BIF_LS; 640 adev->pg_flags = AMD_PG_SUPPORT_VCN | 641 AMD_PG_SUPPORT_VCN_DPG | 642 AMD_PG_SUPPORT_JPEG | 643 AMD_PG_SUPPORT_ATHUB; 644 adev->external_rev_id = adev->rev_id + 0x1; 645 break; 646 case IP_VERSION(10, 1, 1): 647 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 648 AMD_CG_SUPPORT_GFX_CGCG | 649 AMD_CG_SUPPORT_IH_CG | 650 AMD_CG_SUPPORT_HDP_MGCG | 651 AMD_CG_SUPPORT_HDP_LS | 652 AMD_CG_SUPPORT_SDMA_MGCG | 653 AMD_CG_SUPPORT_SDMA_LS | 654 AMD_CG_SUPPORT_MC_MGCG | 655 AMD_CG_SUPPORT_MC_LS | 656 AMD_CG_SUPPORT_ATHUB_MGCG | 657 AMD_CG_SUPPORT_ATHUB_LS | 658 AMD_CG_SUPPORT_VCN_MGCG | 659 AMD_CG_SUPPORT_JPEG_MGCG | 660 AMD_CG_SUPPORT_BIF_MGCG | 661 AMD_CG_SUPPORT_BIF_LS; 662 adev->pg_flags = AMD_PG_SUPPORT_VCN | 663 AMD_PG_SUPPORT_JPEG | 664 AMD_PG_SUPPORT_VCN_DPG; 665 adev->external_rev_id = adev->rev_id + 20; 666 break; 667 case IP_VERSION(10, 1, 2): 668 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 669 AMD_CG_SUPPORT_GFX_MGLS | 670 AMD_CG_SUPPORT_GFX_CGCG | 671 AMD_CG_SUPPORT_GFX_CP_LS | 672 AMD_CG_SUPPORT_GFX_RLC_LS | 673 AMD_CG_SUPPORT_IH_CG | 674 AMD_CG_SUPPORT_HDP_MGCG | 675 AMD_CG_SUPPORT_HDP_LS | 676 AMD_CG_SUPPORT_SDMA_MGCG | 677 AMD_CG_SUPPORT_SDMA_LS | 678 AMD_CG_SUPPORT_MC_MGCG | 679 AMD_CG_SUPPORT_MC_LS | 680 AMD_CG_SUPPORT_ATHUB_MGCG | 681 AMD_CG_SUPPORT_ATHUB_LS | 682 AMD_CG_SUPPORT_VCN_MGCG | 683 AMD_CG_SUPPORT_JPEG_MGCG; 684 adev->pg_flags = AMD_PG_SUPPORT_VCN | 685 AMD_PG_SUPPORT_VCN_DPG | 686 AMD_PG_SUPPORT_JPEG | 687 AMD_PG_SUPPORT_ATHUB; 688 /* guest vm gets 0xffffffff when reading RCC_DEV0_EPF0_STRAP0, 689 * as a consequence, the rev_id and external_rev_id are wrong. 690 * workaround it by hardcoding rev_id to 0 (default value). 691 */ 692 if (amdgpu_sriov_vf(adev)) 693 adev->rev_id = 0; 694 adev->external_rev_id = adev->rev_id + 0xa; 695 break; 696 case IP_VERSION(10, 3, 0): 697 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 698 AMD_CG_SUPPORT_GFX_CGCG | 699 AMD_CG_SUPPORT_GFX_CGLS | 700 AMD_CG_SUPPORT_GFX_3D_CGCG | 701 AMD_CG_SUPPORT_MC_MGCG | 702 AMD_CG_SUPPORT_VCN_MGCG | 703 AMD_CG_SUPPORT_JPEG_MGCG | 704 AMD_CG_SUPPORT_HDP_MGCG | 705 AMD_CG_SUPPORT_HDP_LS | 706 AMD_CG_SUPPORT_IH_CG | 707 AMD_CG_SUPPORT_MC_LS; 708 adev->pg_flags = AMD_PG_SUPPORT_VCN | 709 AMD_PG_SUPPORT_VCN_DPG | 710 AMD_PG_SUPPORT_JPEG | 711 AMD_PG_SUPPORT_ATHUB | 712 AMD_PG_SUPPORT_MMHUB; 713 if (amdgpu_sriov_vf(adev)) { 714 /* hypervisor control CG and PG enablement */ 715 adev->cg_flags = 0; 716 adev->pg_flags = 0; 717 } 718 adev->external_rev_id = adev->rev_id + 0x28; 719 break; 720 case IP_VERSION(10, 3, 2): 721 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 722 AMD_CG_SUPPORT_GFX_CGCG | 723 AMD_CG_SUPPORT_GFX_CGLS | 724 AMD_CG_SUPPORT_GFX_3D_CGCG | 725 AMD_CG_SUPPORT_VCN_MGCG | 726 AMD_CG_SUPPORT_JPEG_MGCG | 727 AMD_CG_SUPPORT_MC_MGCG | 728 AMD_CG_SUPPORT_MC_LS | 729 AMD_CG_SUPPORT_HDP_MGCG | 730 AMD_CG_SUPPORT_HDP_LS | 731 AMD_CG_SUPPORT_IH_CG; 732 adev->pg_flags = AMD_PG_SUPPORT_VCN | 733 AMD_PG_SUPPORT_VCN_DPG | 734 AMD_PG_SUPPORT_JPEG | 735 AMD_PG_SUPPORT_ATHUB | 736 AMD_PG_SUPPORT_MMHUB; 737 adev->external_rev_id = adev->rev_id + 0x32; 738 break; 739 case IP_VERSION(10, 3, 1): 740 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 741 AMD_CG_SUPPORT_GFX_MGLS | 742 AMD_CG_SUPPORT_GFX_CP_LS | 743 AMD_CG_SUPPORT_GFX_RLC_LS | 744 AMD_CG_SUPPORT_GFX_CGCG | 745 AMD_CG_SUPPORT_GFX_CGLS | 746 AMD_CG_SUPPORT_GFX_3D_CGCG | 747 AMD_CG_SUPPORT_GFX_3D_CGLS | 748 AMD_CG_SUPPORT_MC_MGCG | 749 AMD_CG_SUPPORT_MC_LS | 750 AMD_CG_SUPPORT_GFX_FGCG | 751 AMD_CG_SUPPORT_VCN_MGCG | 752 AMD_CG_SUPPORT_SDMA_MGCG | 753 AMD_CG_SUPPORT_SDMA_LS | 754 AMD_CG_SUPPORT_JPEG_MGCG; 755 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | 756 AMD_PG_SUPPORT_VCN | 757 AMD_PG_SUPPORT_VCN_DPG | 758 AMD_PG_SUPPORT_JPEG; 759 if (adev->apu_flags & AMD_APU_IS_VANGOGH) 760 adev->external_rev_id = adev->rev_id + 0x01; 761 break; 762 case IP_VERSION(10, 3, 4): 763 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 764 AMD_CG_SUPPORT_GFX_CGCG | 765 AMD_CG_SUPPORT_GFX_CGLS | 766 AMD_CG_SUPPORT_GFX_3D_CGCG | 767 AMD_CG_SUPPORT_VCN_MGCG | 768 AMD_CG_SUPPORT_JPEG_MGCG | 769 AMD_CG_SUPPORT_MC_MGCG | 770 AMD_CG_SUPPORT_MC_LS | 771 AMD_CG_SUPPORT_HDP_MGCG | 772 AMD_CG_SUPPORT_HDP_LS | 773 AMD_CG_SUPPORT_IH_CG; 774 adev->pg_flags = AMD_PG_SUPPORT_VCN | 775 AMD_PG_SUPPORT_VCN_DPG | 776 AMD_PG_SUPPORT_JPEG | 777 AMD_PG_SUPPORT_ATHUB | 778 AMD_PG_SUPPORT_MMHUB; 779 adev->external_rev_id = adev->rev_id + 0x3c; 780 break; 781 case IP_VERSION(10, 3, 5): 782 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 783 AMD_CG_SUPPORT_GFX_CGCG | 784 AMD_CG_SUPPORT_GFX_CGLS | 785 AMD_CG_SUPPORT_GFX_3D_CGCG | 786 AMD_CG_SUPPORT_MC_MGCG | 787 AMD_CG_SUPPORT_MC_LS | 788 AMD_CG_SUPPORT_HDP_MGCG | 789 AMD_CG_SUPPORT_HDP_LS | 790 AMD_CG_SUPPORT_IH_CG | 791 AMD_CG_SUPPORT_VCN_MGCG; 792 adev->pg_flags = AMD_PG_SUPPORT_VCN | 793 AMD_PG_SUPPORT_VCN_DPG | 794 AMD_PG_SUPPORT_ATHUB | 795 AMD_PG_SUPPORT_MMHUB; 796 adev->external_rev_id = adev->rev_id + 0x46; 797 break; 798 case IP_VERSION(10, 3, 3): 799 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 800 AMD_CG_SUPPORT_GFX_MGLS | 801 AMD_CG_SUPPORT_GFX_CGCG | 802 AMD_CG_SUPPORT_GFX_CGLS | 803 AMD_CG_SUPPORT_GFX_3D_CGCG | 804 AMD_CG_SUPPORT_GFX_3D_CGLS | 805 AMD_CG_SUPPORT_GFX_RLC_LS | 806 AMD_CG_SUPPORT_GFX_CP_LS | 807 AMD_CG_SUPPORT_GFX_FGCG | 808 AMD_CG_SUPPORT_MC_MGCG | 809 AMD_CG_SUPPORT_MC_LS | 810 AMD_CG_SUPPORT_SDMA_LS | 811 AMD_CG_SUPPORT_HDP_MGCG | 812 AMD_CG_SUPPORT_HDP_LS | 813 AMD_CG_SUPPORT_ATHUB_MGCG | 814 AMD_CG_SUPPORT_ATHUB_LS | 815 AMD_CG_SUPPORT_IH_CG | 816 AMD_CG_SUPPORT_VCN_MGCG | 817 AMD_CG_SUPPORT_JPEG_MGCG | 818 AMD_CG_SUPPORT_SDMA_MGCG; 819 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | 820 AMD_PG_SUPPORT_VCN | 821 AMD_PG_SUPPORT_VCN_DPG | 822 AMD_PG_SUPPORT_JPEG; 823 if (adev->pdev->device == 0x1681) 824 adev->external_rev_id = 0x20; 825 else 826 adev->external_rev_id = adev->rev_id + 0x01; 827 break; 828 case IP_VERSION(10, 1, 3): 829 case IP_VERSION(10, 1, 4): 830 adev->cg_flags = 0; 831 adev->pg_flags = 0; 832 adev->external_rev_id = adev->rev_id + 0x82; 833 break; 834 case IP_VERSION(10, 3, 6): 835 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 836 AMD_CG_SUPPORT_GFX_MGLS | 837 AMD_CG_SUPPORT_GFX_CGCG | 838 AMD_CG_SUPPORT_GFX_CGLS | 839 AMD_CG_SUPPORT_GFX_3D_CGCG | 840 AMD_CG_SUPPORT_GFX_3D_CGLS | 841 AMD_CG_SUPPORT_GFX_RLC_LS | 842 AMD_CG_SUPPORT_GFX_CP_LS | 843 AMD_CG_SUPPORT_GFX_FGCG | 844 AMD_CG_SUPPORT_MC_MGCG | 845 AMD_CG_SUPPORT_MC_LS | 846 AMD_CG_SUPPORT_SDMA_LS | 847 AMD_CG_SUPPORT_HDP_MGCG | 848 AMD_CG_SUPPORT_HDP_LS | 849 AMD_CG_SUPPORT_ATHUB_MGCG | 850 AMD_CG_SUPPORT_ATHUB_LS | 851 AMD_CG_SUPPORT_IH_CG | 852 AMD_CG_SUPPORT_VCN_MGCG | 853 AMD_CG_SUPPORT_JPEG_MGCG; 854 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | 855 AMD_PG_SUPPORT_VCN | 856 AMD_PG_SUPPORT_VCN_DPG | 857 AMD_PG_SUPPORT_JPEG; 858 adev->external_rev_id = adev->rev_id + 0x01; 859 break; 860 case IP_VERSION(10, 3, 7): 861 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 862 AMD_CG_SUPPORT_GFX_MGLS | 863 AMD_CG_SUPPORT_GFX_CGCG | 864 AMD_CG_SUPPORT_GFX_CGLS | 865 AMD_CG_SUPPORT_GFX_3D_CGCG | 866 AMD_CG_SUPPORT_GFX_3D_CGLS | 867 AMD_CG_SUPPORT_GFX_RLC_LS | 868 AMD_CG_SUPPORT_GFX_CP_LS | 869 AMD_CG_SUPPORT_GFX_FGCG | 870 AMD_CG_SUPPORT_MC_MGCG | 871 AMD_CG_SUPPORT_MC_LS | 872 AMD_CG_SUPPORT_SDMA_LS | 873 AMD_CG_SUPPORT_HDP_MGCG | 874 AMD_CG_SUPPORT_HDP_LS | 875 AMD_CG_SUPPORT_ATHUB_MGCG | 876 AMD_CG_SUPPORT_ATHUB_LS | 877 AMD_CG_SUPPORT_IH_CG | 878 AMD_CG_SUPPORT_VCN_MGCG | 879 AMD_CG_SUPPORT_JPEG_MGCG | 880 AMD_CG_SUPPORT_SDMA_MGCG; 881 adev->pg_flags = AMD_PG_SUPPORT_VCN | 882 AMD_PG_SUPPORT_VCN_DPG | 883 AMD_PG_SUPPORT_JPEG | 884 AMD_PG_SUPPORT_GFX_PG; 885 adev->external_rev_id = adev->rev_id + 0x01; 886 break; 887 default: 888 /* FIXME: not supported yet */ 889 return -EINVAL; 890 } 891 892 if (adev->harvest_ip_mask & AMD_HARVEST_IP_VCN_MASK) 893 adev->pg_flags &= ~(AMD_PG_SUPPORT_VCN | 894 AMD_PG_SUPPORT_VCN_DPG | 895 AMD_PG_SUPPORT_JPEG); 896 897 if (amdgpu_sriov_vf(adev)) { 898 amdgpu_virt_init_setting(adev); 899 xgpu_nv_mailbox_set_irq_funcs(adev); 900 } 901 902 return 0; 903 } 904 905 static int nv_common_late_init(struct amdgpu_ip_block *ip_block) 906 { 907 struct amdgpu_device *adev = ip_block->adev; 908 909 if (amdgpu_sriov_vf(adev)) { 910 xgpu_nv_mailbox_get_irq(adev); 911 if (adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) { 912 amdgpu_virt_update_sriov_video_codec(adev, 913 sriov_sc_video_codecs_encode_array, 914 ARRAY_SIZE(sriov_sc_video_codecs_encode_array), 915 sriov_sc_video_codecs_decode_array_vcn1, 916 ARRAY_SIZE(sriov_sc_video_codecs_decode_array_vcn1)); 917 } else { 918 amdgpu_virt_update_sriov_video_codec(adev, 919 sriov_sc_video_codecs_encode_array, 920 ARRAY_SIZE(sriov_sc_video_codecs_encode_array), 921 sriov_sc_video_codecs_decode_array_vcn0, 922 ARRAY_SIZE(sriov_sc_video_codecs_decode_array_vcn0)); 923 } 924 } 925 926 /* Enable selfring doorbell aperture late because doorbell BAR 927 * aperture will change if resize BAR successfully in gmc sw_init. 928 */ 929 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, true); 930 931 return 0; 932 } 933 934 static int nv_common_sw_init(struct amdgpu_ip_block *ip_block) 935 { 936 struct amdgpu_device *adev = ip_block->adev; 937 938 if (amdgpu_sriov_vf(adev)) 939 xgpu_nv_mailbox_add_irq_id(adev); 940 941 return 0; 942 } 943 944 static int nv_common_hw_init(struct amdgpu_ip_block *ip_block) 945 { 946 struct amdgpu_device *adev = ip_block->adev; 947 948 if (adev->nbio.funcs->apply_lc_spc_mode_wa) 949 adev->nbio.funcs->apply_lc_spc_mode_wa(adev); 950 951 if (adev->nbio.funcs->apply_l1_link_width_reconfig_wa) 952 adev->nbio.funcs->apply_l1_link_width_reconfig_wa(adev); 953 954 /* enable aspm */ 955 amdgpu_nbio_program_aspm(adev); 956 /* setup nbio registers */ 957 adev->nbio.funcs->init_registers(adev); 958 /* remap HDP registers to a hole in mmio space, 959 * for the purpose of expose those registers 960 * to process space 961 */ 962 if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev)) 963 adev->nbio.funcs->remap_hdp_registers(adev); 964 /* enable the doorbell aperture */ 965 adev->nbio.funcs->enable_doorbell_aperture(adev, true); 966 967 return 0; 968 } 969 970 static int nv_common_hw_fini(struct amdgpu_ip_block *ip_block) 971 { 972 struct amdgpu_device *adev = ip_block->adev; 973 974 /* Disable the doorbell aperture and selfring doorbell aperture 975 * separately in hw_fini because nv_enable_doorbell_aperture 976 * has been removed and there is no need to delay disabling 977 * selfring doorbell. 978 */ 979 adev->nbio.funcs->enable_doorbell_aperture(adev, false); 980 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, false); 981 982 return 0; 983 } 984 985 static int nv_common_suspend(struct amdgpu_ip_block *ip_block) 986 { 987 return nv_common_hw_fini(ip_block); 988 } 989 990 static int nv_common_resume(struct amdgpu_ip_block *ip_block) 991 { 992 return nv_common_hw_init(ip_block); 993 } 994 995 static bool nv_common_is_idle(struct amdgpu_ip_block *ip_block) 996 { 997 return true; 998 } 999 1000 static int nv_common_set_clockgating_state(struct amdgpu_ip_block *ip_block, 1001 enum amd_clockgating_state state) 1002 { 1003 struct amdgpu_device *adev = ip_block->adev; 1004 1005 if (amdgpu_sriov_vf(adev)) 1006 return 0; 1007 1008 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) { 1009 case IP_VERSION(2, 3, 0): 1010 case IP_VERSION(2, 3, 1): 1011 case IP_VERSION(2, 3, 2): 1012 case IP_VERSION(3, 3, 0): 1013 case IP_VERSION(3, 3, 1): 1014 case IP_VERSION(3, 3, 2): 1015 case IP_VERSION(3, 3, 3): 1016 adev->nbio.funcs->update_medium_grain_clock_gating(adev, 1017 state == AMD_CG_STATE_GATE); 1018 adev->nbio.funcs->update_medium_grain_light_sleep(adev, 1019 state == AMD_CG_STATE_GATE); 1020 adev->hdp.funcs->update_clock_gating(adev, 1021 state == AMD_CG_STATE_GATE); 1022 adev->smuio.funcs->update_rom_clock_gating(adev, 1023 state == AMD_CG_STATE_GATE); 1024 break; 1025 default: 1026 break; 1027 } 1028 return 0; 1029 } 1030 1031 static int nv_common_set_powergating_state(struct amdgpu_ip_block *ip_block, 1032 enum amd_powergating_state state) 1033 { 1034 /* TODO */ 1035 return 0; 1036 } 1037 1038 static void nv_common_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags) 1039 { 1040 struct amdgpu_device *adev = ip_block->adev; 1041 1042 if (amdgpu_sriov_vf(adev)) 1043 *flags = 0; 1044 1045 adev->nbio.funcs->get_clockgating_state(adev, flags); 1046 1047 adev->hdp.funcs->get_clock_gating_state(adev, flags); 1048 1049 adev->smuio.funcs->get_clock_gating_state(adev, flags); 1050 } 1051 1052 static const struct amd_ip_funcs nv_common_ip_funcs = { 1053 .name = "nv_common", 1054 .early_init = nv_common_early_init, 1055 .late_init = nv_common_late_init, 1056 .sw_init = nv_common_sw_init, 1057 .hw_init = nv_common_hw_init, 1058 .hw_fini = nv_common_hw_fini, 1059 .suspend = nv_common_suspend, 1060 .resume = nv_common_resume, 1061 .is_idle = nv_common_is_idle, 1062 .set_clockgating_state = nv_common_set_clockgating_state, 1063 .set_powergating_state = nv_common_set_powergating_state, 1064 .get_clockgating_state = nv_common_get_clockgating_state, 1065 }; 1066