1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "amdgpu.h" 24 #include "nbio_v7_9.h" 25 #include "amdgpu_ras.h" 26 27 #include "nbio/nbio_7_9_0_offset.h" 28 #include "nbio/nbio_7_9_0_sh_mask.h" 29 #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h" 30 #include <uapi/linux/kfd_ioctl.h> 31 32 #define NPS_MODE_MASK 0x000000FFL 33 34 /* Core 0 Port 0 counter */ 35 #define smnPCIEP_NAK_COUNTER 0x1A340218 36 37 static void nbio_v7_9_remap_hdp_registers(struct amdgpu_device *adev) 38 { 39 WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL, 40 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL); 41 WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL, 42 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL); 43 } 44 45 static u32 nbio_v7_9_get_rev_id(struct amdgpu_device *adev) 46 { 47 u32 tmp; 48 49 tmp = IP_VERSION_SUBREV(amdgpu_ip_version_full(adev, NBIO_HWIP, 0)); 50 /* If it is VF or subrevision holds a non-zero value, that should be used */ 51 if (tmp || amdgpu_sriov_vf(adev)) 52 return tmp; 53 54 /* If discovery subrev is not updated, use register version */ 55 tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0); 56 tmp = REG_GET_FIELD(tmp, RCC_STRAP0_RCC_DEV0_EPF0_STRAP0, 57 STRAP_ATI_REV_ID_DEV0_F0); 58 59 return tmp; 60 } 61 62 static void nbio_v7_9_mc_access_enable(struct amdgpu_device *adev, bool enable) 63 { 64 if (enable) 65 WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN, 66 BIF_BX0_BIF_FB_EN__FB_READ_EN_MASK | BIF_BX0_BIF_FB_EN__FB_WRITE_EN_MASK); 67 else 68 WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN, 0); 69 } 70 71 static u32 nbio_v7_9_get_memsize(struct amdgpu_device *adev) 72 { 73 return RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE); 74 } 75 76 static void nbio_v7_9_sdma_doorbell_range(struct amdgpu_device *adev, int instance, 77 bool use_doorbell, int doorbell_index, int doorbell_size) 78 { 79 u32 doorbell_range = 0, doorbell_ctrl = 0; 80 int aid_id, dev_inst; 81 82 dev_inst = GET_INST(SDMA0, instance); 83 aid_id = adev->sdma.instance[instance].aid_id; 84 85 if (use_doorbell == false) 86 return; 87 88 doorbell_range = 89 REG_SET_FIELD(doorbell_range, DOORBELL0_CTRL_ENTRY_0, 90 BIF_DOORBELL0_RANGE_OFFSET_ENTRY, doorbell_index); 91 doorbell_range = 92 REG_SET_FIELD(doorbell_range, DOORBELL0_CTRL_ENTRY_0, 93 BIF_DOORBELL0_RANGE_SIZE_ENTRY, doorbell_size); 94 doorbell_ctrl = 95 REG_SET_FIELD(doorbell_ctrl, S2A_DOORBELL_ENTRY_1_CTRL, 96 S2A_DOORBELL_PORT1_ENABLE, 1); 97 doorbell_ctrl = 98 REG_SET_FIELD(doorbell_ctrl, S2A_DOORBELL_ENTRY_1_CTRL, 99 S2A_DOORBELL_PORT1_RANGE_SIZE, doorbell_size); 100 101 switch (dev_inst % adev->sdma.num_inst_per_aid) { 102 case 0: 103 WREG32_SOC15_OFFSET(NBIO, 0, regDOORBELL0_CTRL_ENTRY_1, 104 4 * aid_id, doorbell_range); 105 106 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, 107 S2A_DOORBELL_ENTRY_1_CTRL, 108 S2A_DOORBELL_PORT1_AWID, 0xe); 109 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, 110 S2A_DOORBELL_ENTRY_1_CTRL, 111 S2A_DOORBELL_PORT1_RANGE_OFFSET, 0xe); 112 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, 113 S2A_DOORBELL_ENTRY_1_CTRL, 114 S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE, 115 0x1); 116 WREG32_SOC15_EXT(NBIO, aid_id, regS2A_DOORBELL_ENTRY_1_CTRL, 117 aid_id, doorbell_ctrl); 118 break; 119 case 1: 120 WREG32_SOC15_OFFSET(NBIO, 0, regDOORBELL0_CTRL_ENTRY_2, 121 4 * aid_id, doorbell_range); 122 123 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, 124 S2A_DOORBELL_ENTRY_1_CTRL, 125 S2A_DOORBELL_PORT1_AWID, 0x8); 126 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, 127 S2A_DOORBELL_ENTRY_1_CTRL, 128 S2A_DOORBELL_PORT1_RANGE_OFFSET, 0x8); 129 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, 130 S2A_DOORBELL_ENTRY_1_CTRL, 131 S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE, 132 0x2); 133 WREG32_SOC15_EXT(NBIO, aid_id, regS2A_DOORBELL_ENTRY_2_CTRL, 134 aid_id, doorbell_ctrl); 135 break; 136 case 2: 137 WREG32_SOC15_OFFSET(NBIO, 0, regDOORBELL0_CTRL_ENTRY_3, 138 4 * aid_id, doorbell_range); 139 140 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, 141 S2A_DOORBELL_ENTRY_1_CTRL, 142 S2A_DOORBELL_PORT1_AWID, 0x9); 143 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, 144 S2A_DOORBELL_ENTRY_1_CTRL, 145 S2A_DOORBELL_PORT1_RANGE_OFFSET, 0x9); 146 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, 147 S2A_DOORBELL_ENTRY_1_CTRL, 148 S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE, 149 0x8); 150 WREG32_SOC15_EXT(NBIO, aid_id, regS2A_DOORBELL_ENTRY_5_CTRL, 151 aid_id, doorbell_ctrl); 152 break; 153 case 3: 154 WREG32_SOC15_OFFSET(NBIO, 0, regDOORBELL0_CTRL_ENTRY_4, 155 4 * aid_id, doorbell_range); 156 157 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, 158 S2A_DOORBELL_ENTRY_1_CTRL, 159 S2A_DOORBELL_PORT1_AWID, 0xa); 160 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, 161 S2A_DOORBELL_ENTRY_1_CTRL, 162 S2A_DOORBELL_PORT1_RANGE_OFFSET, 0xa); 163 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, 164 S2A_DOORBELL_ENTRY_1_CTRL, 165 S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE, 166 0x9); 167 WREG32_SOC15_EXT(NBIO, aid_id, regS2A_DOORBELL_ENTRY_6_CTRL, 168 aid_id, doorbell_ctrl); 169 break; 170 default: 171 break; 172 } 173 } 174 175 static void nbio_v7_9_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell, 176 int doorbell_index, int instance) 177 { 178 u32 doorbell_range = 0, doorbell_ctrl = 0; 179 u32 aid_id = instance; 180 u32 range_size; 181 182 if (use_doorbell) { 183 range_size = (amdgpu_ip_version(adev, GC_HWIP, 0) == 184 IP_VERSION(9, 5, 0)) ? 185 0xb : 0x9; 186 doorbell_range = REG_SET_FIELD(doorbell_range, 187 DOORBELL0_CTRL_ENTRY_0, 188 BIF_DOORBELL0_RANGE_OFFSET_ENTRY, 189 doorbell_index); 190 doorbell_range = REG_SET_FIELD(doorbell_range, 191 DOORBELL0_CTRL_ENTRY_0, 192 BIF_DOORBELL0_RANGE_SIZE_ENTRY, 193 range_size); 194 if (aid_id) 195 doorbell_range = REG_SET_FIELD(doorbell_range, 196 DOORBELL0_CTRL_ENTRY_0, 197 DOORBELL0_FENCE_ENABLE_ENTRY, 198 0x4); 199 200 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, 201 S2A_DOORBELL_ENTRY_1_CTRL, 202 S2A_DOORBELL_PORT1_ENABLE, 1); 203 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, 204 S2A_DOORBELL_ENTRY_1_CTRL, 205 S2A_DOORBELL_PORT1_AWID, 0x4); 206 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, 207 S2A_DOORBELL_ENTRY_1_CTRL, 208 S2A_DOORBELL_PORT1_RANGE_OFFSET, 0x4); 209 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, 210 S2A_DOORBELL_ENTRY_1_CTRL, 211 S2A_DOORBELL_PORT1_RANGE_SIZE, range_size); 212 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, 213 S2A_DOORBELL_ENTRY_1_CTRL, 214 S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE, 0x4); 215 216 WREG32_SOC15_OFFSET(NBIO, 0, regDOORBELL0_CTRL_ENTRY_17, 217 aid_id, doorbell_range); 218 WREG32_SOC15_EXT(NBIO, aid_id, regS2A_DOORBELL_ENTRY_4_CTRL, 219 aid_id, doorbell_ctrl); 220 } else { 221 doorbell_range = REG_SET_FIELD(doorbell_range, 222 DOORBELL0_CTRL_ENTRY_0, 223 BIF_DOORBELL0_RANGE_SIZE_ENTRY, 0); 224 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, 225 S2A_DOORBELL_ENTRY_1_CTRL, 226 S2A_DOORBELL_PORT1_RANGE_SIZE, 0); 227 228 WREG32_SOC15_OFFSET(NBIO, 0, regDOORBELL0_CTRL_ENTRY_17, 229 aid_id, doorbell_range); 230 WREG32_SOC15_EXT(NBIO, aid_id, regS2A_DOORBELL_ENTRY_4_CTRL, 231 aid_id, doorbell_ctrl); 232 } 233 } 234 235 static void nbio_v7_9_enable_doorbell_aperture(struct amdgpu_device *adev, 236 bool enable) 237 { 238 /* Enable to allow doorbell pass thru on pre-silicon bare-metal */ 239 WREG32_SOC15(NBIO, 0, regBIFC_DOORBELL_ACCESS_EN_PF, 0xfffff); 240 WREG32_FIELD15_PREREG(NBIO, 0, RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN, 241 BIF_DOORBELL_APER_EN, enable ? 1 : 0); 242 } 243 244 static void nbio_v7_9_enable_doorbell_selfring_aperture(struct amdgpu_device *adev, 245 bool enable) 246 { 247 u32 tmp = 0; 248 249 if (enable) { 250 tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, 251 DOORBELL_SELFRING_GPA_APER_EN, 1) | 252 REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, 253 DOORBELL_SELFRING_GPA_APER_MODE, 1) | 254 REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, 255 DOORBELL_SELFRING_GPA_APER_SIZE, 0); 256 257 WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW, 258 lower_32_bits(adev->doorbell.base)); 259 WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH, 260 upper_32_bits(adev->doorbell.base)); 261 } 262 263 WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, tmp); 264 } 265 266 static void nbio_v7_9_ih_doorbell_range(struct amdgpu_device *adev, 267 bool use_doorbell, int doorbell_index) 268 { 269 u32 ih_doorbell_range = 0, ih_doorbell_ctrl = 0; 270 271 if (use_doorbell) { 272 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 273 DOORBELL0_CTRL_ENTRY_0, 274 BIF_DOORBELL0_RANGE_OFFSET_ENTRY, 275 doorbell_index); 276 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 277 DOORBELL0_CTRL_ENTRY_0, 278 BIF_DOORBELL0_RANGE_SIZE_ENTRY, 279 0x8); 280 281 ih_doorbell_ctrl = REG_SET_FIELD(ih_doorbell_ctrl, 282 S2A_DOORBELL_ENTRY_1_CTRL, 283 S2A_DOORBELL_PORT1_ENABLE, 1); 284 ih_doorbell_ctrl = REG_SET_FIELD(ih_doorbell_ctrl, 285 S2A_DOORBELL_ENTRY_1_CTRL, 286 S2A_DOORBELL_PORT1_AWID, 0); 287 ih_doorbell_ctrl = REG_SET_FIELD(ih_doorbell_ctrl, 288 S2A_DOORBELL_ENTRY_1_CTRL, 289 S2A_DOORBELL_PORT1_RANGE_OFFSET, 0); 290 ih_doorbell_ctrl = REG_SET_FIELD(ih_doorbell_ctrl, 291 S2A_DOORBELL_ENTRY_1_CTRL, 292 S2A_DOORBELL_PORT1_RANGE_SIZE, 0x8); 293 ih_doorbell_ctrl = REG_SET_FIELD(ih_doorbell_ctrl, 294 S2A_DOORBELL_ENTRY_1_CTRL, 295 S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE, 0); 296 } else { 297 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 298 DOORBELL0_CTRL_ENTRY_0, 299 BIF_DOORBELL0_RANGE_SIZE_ENTRY, 0); 300 ih_doorbell_ctrl = REG_SET_FIELD(ih_doorbell_ctrl, 301 S2A_DOORBELL_ENTRY_1_CTRL, 302 S2A_DOORBELL_PORT1_RANGE_SIZE, 0); 303 } 304 305 WREG32_SOC15(NBIO, 0, regDOORBELL0_CTRL_ENTRY_0, ih_doorbell_range); 306 WREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_3_CTRL, ih_doorbell_ctrl); 307 } 308 309 310 static void nbio_v7_9_update_medium_grain_clock_gating(struct amdgpu_device *adev, 311 bool enable) 312 { 313 } 314 315 static void nbio_v7_9_update_medium_grain_light_sleep(struct amdgpu_device *adev, 316 bool enable) 317 { 318 } 319 320 static void nbio_v7_9_get_clockgating_state(struct amdgpu_device *adev, 321 u64 *flags) 322 { 323 } 324 325 static void nbio_v7_9_ih_control(struct amdgpu_device *adev) 326 { 327 u32 interrupt_cntl; 328 329 /* setup interrupt control */ 330 WREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL2, adev->dummy_page_addr >> 8); 331 interrupt_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL); 332 /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi 333 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN 334 */ 335 interrupt_cntl = 336 REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0); 337 /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */ 338 interrupt_cntl = 339 REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0); 340 WREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL, interrupt_cntl); 341 } 342 343 static u32 nbio_v7_9_get_hdp_flush_req_offset(struct amdgpu_device *adev) 344 { 345 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_REQ); 346 } 347 348 static u32 nbio_v7_9_get_hdp_flush_done_offset(struct amdgpu_device *adev) 349 { 350 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_DONE); 351 } 352 353 static u32 nbio_v7_9_get_pcie_index_offset(struct amdgpu_device *adev) 354 { 355 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_INDEX2); 356 } 357 358 static u32 nbio_v7_9_get_pcie_data_offset(struct amdgpu_device *adev) 359 { 360 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_DATA2); 361 } 362 363 static u32 nbio_v7_9_get_pcie_index_hi_offset(struct amdgpu_device *adev) 364 { 365 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_INDEX2_HI); 366 } 367 368 const struct nbio_hdp_flush_reg nbio_v7_9_hdp_flush_reg = { 369 .ref_and_mask_cp0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK, 370 .ref_and_mask_cp1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1_MASK, 371 .ref_and_mask_cp2 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2_MASK, 372 .ref_and_mask_cp3 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3_MASK, 373 .ref_and_mask_cp4 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4_MASK, 374 .ref_and_mask_cp5 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5_MASK, 375 .ref_and_mask_cp6 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6_MASK, 376 .ref_and_mask_cp7 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7_MASK, 377 .ref_and_mask_cp8 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8_MASK, 378 .ref_and_mask_cp9 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9_MASK, 379 .ref_and_mask_sdma0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK, 380 .ref_and_mask_sdma1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK, 381 .ref_and_mask_sdma2 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK, 382 .ref_and_mask_sdma3 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK, 383 .ref_and_mask_sdma4 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK, 384 .ref_and_mask_sdma5 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK, 385 .ref_and_mask_sdma6 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK, 386 .ref_and_mask_sdma7 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK, 387 }; 388 389 static void nbio_v7_9_enable_doorbell_interrupt(struct amdgpu_device *adev, 390 bool enable) 391 { 392 WREG32_FIELD15_PREREG(NBIO, 0, BIF_BX0_BIF_DOORBELL_INT_CNTL, 393 DOORBELL_INTERRUPT_DISABLE, enable ? 0 : 1); 394 } 395 396 static int nbio_v7_9_get_compute_partition_mode(struct amdgpu_device *adev) 397 { 398 u32 tmp, px; 399 400 tmp = RREG32_SOC15(NBIO, 0, regBIF_BX_PF0_PARTITION_COMPUTE_STATUS); 401 px = REG_GET_FIELD(tmp, BIF_BX_PF0_PARTITION_COMPUTE_STATUS, 402 PARTITION_MODE); 403 404 return px; 405 } 406 407 static bool nbio_v7_9_is_nps_switch_requested(struct amdgpu_device *adev) 408 { 409 u32 tmp; 410 411 tmp = RREG32_SOC15(NBIO, 0, regBIF_BX_PF0_PARTITION_MEM_STATUS); 412 tmp = REG_GET_FIELD(tmp, BIF_BX_PF0_PARTITION_MEM_STATUS, 413 CHANGE_STATUE); 414 415 /* 0x8 - NPS switch requested */ 416 return (tmp == 0x8); 417 } 418 static u32 nbio_v7_9_get_memory_partition_mode(struct amdgpu_device *adev, 419 u32 *supp_modes) 420 { 421 u32 tmp; 422 423 tmp = RREG32_SOC15(NBIO, 0, regBIF_BX_PF0_PARTITION_MEM_STATUS); 424 tmp = REG_GET_FIELD(tmp, BIF_BX_PF0_PARTITION_MEM_STATUS, NPS_MODE); 425 426 if (supp_modes) { 427 *supp_modes = 428 RREG32_SOC15(NBIO, 0, regBIF_BX_PF0_PARTITION_MEM_CAP); 429 } 430 431 return ffs(tmp); 432 } 433 434 static void nbio_v7_9_init_registers(struct amdgpu_device *adev) 435 { 436 u32 inst_mask; 437 int i; 438 439 WREG32_SOC15(NBIO, 0, regXCC_DOORBELL_FENCE, 440 0xff & ~(adev->gfx.xcc_mask)); 441 442 WREG32_SOC15(NBIO, 0, regBIFC_GFX_INT_MONITOR_MASK, 0x7ff); 443 444 inst_mask = adev->aid_mask & ~1U; 445 for_each_inst(i, inst_mask) { 446 WREG32_SOC15_EXT(NBIO, i, regXCC_DOORBELL_FENCE, i, 447 XCC_DOORBELL_FENCE__SHUB_SLV_MODE_MASK); 448 449 } 450 451 if (!amdgpu_sriov_vf(adev)) { 452 u32 baco_cntl; 453 for_each_inst(i, adev->aid_mask) { 454 baco_cntl = RREG32_SOC15(NBIO, i, regBIF_BX0_BACO_CNTL); 455 if (baco_cntl & (BIF_BX0_BACO_CNTL__BACO_DUMMY_EN_MASK | 456 BIF_BX0_BACO_CNTL__BACO_EN_MASK)) { 457 baco_cntl &= ~( 458 BIF_BX0_BACO_CNTL__BACO_DUMMY_EN_MASK | 459 BIF_BX0_BACO_CNTL__BACO_EN_MASK); 460 dev_dbg(adev->dev, 461 "Unsetting baco dummy mode %x", 462 baco_cntl); 463 WREG32_SOC15(NBIO, i, regBIF_BX0_BACO_CNTL, 464 baco_cntl); 465 } 466 } 467 } 468 } 469 470 static u64 nbio_v7_9_get_pcie_replay_count(struct amdgpu_device *adev) 471 { 472 u32 val, nak_r, nak_g; 473 474 if (adev->flags & AMD_IS_APU) 475 return 0; 476 477 /* Get the number of NAKs received and generated */ 478 val = RREG32_PCIE(smnPCIEP_NAK_COUNTER); 479 nak_r = val & 0xFFFF; 480 nak_g = val >> 16; 481 482 /* Add the total number of NAKs, i.e the number of replays */ 483 return (nak_r + nak_g); 484 } 485 486 #define MMIO_REG_HOLE_OFFSET 0x1A000 487 488 static void nbio_v7_9_set_reg_remap(struct amdgpu_device *adev) 489 { 490 if (!amdgpu_sriov_vf(adev) && (PAGE_SIZE <= 4096)) { 491 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; 492 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; 493 } else { 494 adev->rmmio_remap.reg_offset = 495 SOC15_REG_OFFSET( 496 NBIO, 0, 497 regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL) 498 << 2; 499 adev->rmmio_remap.bus_addr = 0; 500 } 501 } 502 503 const struct amdgpu_nbio_funcs nbio_v7_9_funcs = { 504 .get_hdp_flush_req_offset = nbio_v7_9_get_hdp_flush_req_offset, 505 .get_hdp_flush_done_offset = nbio_v7_9_get_hdp_flush_done_offset, 506 .get_pcie_index_offset = nbio_v7_9_get_pcie_index_offset, 507 .get_pcie_data_offset = nbio_v7_9_get_pcie_data_offset, 508 .get_pcie_index_hi_offset = nbio_v7_9_get_pcie_index_hi_offset, 509 .get_rev_id = nbio_v7_9_get_rev_id, 510 .mc_access_enable = nbio_v7_9_mc_access_enable, 511 .get_memsize = nbio_v7_9_get_memsize, 512 .sdma_doorbell_range = nbio_v7_9_sdma_doorbell_range, 513 .vcn_doorbell_range = nbio_v7_9_vcn_doorbell_range, 514 .enable_doorbell_aperture = nbio_v7_9_enable_doorbell_aperture, 515 .enable_doorbell_selfring_aperture = nbio_v7_9_enable_doorbell_selfring_aperture, 516 .ih_doorbell_range = nbio_v7_9_ih_doorbell_range, 517 .enable_doorbell_interrupt = nbio_v7_9_enable_doorbell_interrupt, 518 .update_medium_grain_clock_gating = nbio_v7_9_update_medium_grain_clock_gating, 519 .update_medium_grain_light_sleep = nbio_v7_9_update_medium_grain_light_sleep, 520 .get_clockgating_state = nbio_v7_9_get_clockgating_state, 521 .ih_control = nbio_v7_9_ih_control, 522 .remap_hdp_registers = nbio_v7_9_remap_hdp_registers, 523 .get_compute_partition_mode = nbio_v7_9_get_compute_partition_mode, 524 .get_memory_partition_mode = nbio_v7_9_get_memory_partition_mode, 525 .is_nps_switch_requested = nbio_v7_9_is_nps_switch_requested, 526 .init_registers = nbio_v7_9_init_registers, 527 .get_pcie_replay_count = nbio_v7_9_get_pcie_replay_count, 528 .set_reg_remap = nbio_v7_9_set_reg_remap, 529 }; 530 531 static void nbio_v7_9_query_ras_error_count(struct amdgpu_device *adev, 532 void *ras_error_status) 533 { 534 } 535 536 static void nbio_v7_9_handle_ras_controller_intr_no_bifring(struct amdgpu_device *adev) 537 { 538 uint32_t bif_doorbell_intr_cntl; 539 struct ras_manager *obj = amdgpu_ras_find_obj(adev, adev->nbio.ras_if); 540 struct ras_err_data err_data; 541 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 542 543 if (amdgpu_ras_error_data_init(&err_data)) 544 return; 545 546 bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_DOORBELL_INT_CNTL); 547 548 if (REG_GET_FIELD(bif_doorbell_intr_cntl, 549 BIF_BX0_BIF_DOORBELL_INT_CNTL, RAS_CNTLR_INTERRUPT_STATUS)) { 550 /* driver has to clear the interrupt status when bif ring is disabled */ 551 bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl, 552 BIF_BX0_BIF_DOORBELL_INT_CNTL, 553 RAS_CNTLR_INTERRUPT_CLEAR, 1); 554 WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl); 555 556 if (!ras->disable_ras_err_cnt_harvest) { 557 /* 558 * clear error status after ras_controller_intr 559 * according to hw team and count ue number 560 * for query 561 */ 562 nbio_v7_9_query_ras_error_count(adev, &err_data); 563 564 /* logging on error cnt and printing for awareness */ 565 obj->err_data.ue_count += err_data.ue_count; 566 obj->err_data.ce_count += err_data.ce_count; 567 568 if (err_data.ce_count) 569 dev_info(adev->dev, "%ld correctable hardware " 570 "errors detected in %s block\n", 571 obj->err_data.ce_count, 572 get_ras_block_str(adev->nbio.ras_if)); 573 574 if (err_data.ue_count) 575 dev_info(adev->dev, "%ld uncorrectable hardware " 576 "errors detected in %s block\n", 577 obj->err_data.ue_count, 578 get_ras_block_str(adev->nbio.ras_if)); 579 } 580 581 dev_info(adev->dev, "RAS controller interrupt triggered " 582 "by NBIF error\n"); 583 } 584 585 amdgpu_ras_error_data_fini(&err_data); 586 } 587 588 static void nbio_v7_9_handle_ras_err_event_athub_intr_no_bifring(struct amdgpu_device *adev) 589 { 590 uint32_t bif_doorbell_intr_cntl; 591 592 bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_DOORBELL_INT_CNTL); 593 594 if (REG_GET_FIELD(bif_doorbell_intr_cntl, 595 BIF_BX0_BIF_DOORBELL_INT_CNTL, RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS)) { 596 /* driver has to clear the interrupt status when bif ring is disabled */ 597 bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl, 598 BIF_BX0_BIF_DOORBELL_INT_CNTL, 599 RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR, 1); 600 601 WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl); 602 603 amdgpu_ras_global_ras_isr(adev); 604 } 605 } 606 607 static int nbio_v7_9_set_ras_controller_irq_state(struct amdgpu_device *adev, 608 struct amdgpu_irq_src *src, 609 unsigned type, 610 enum amdgpu_interrupt_state state) 611 { 612 /* Dummy function, there is no initialization operation in driver */ 613 614 return 0; 615 } 616 617 static int nbio_v7_9_process_ras_controller_irq(struct amdgpu_device *adev, 618 struct amdgpu_irq_src *source, 619 struct amdgpu_iv_entry *entry) 620 { 621 /* By design, the ih cookie for ras_controller_irq should be written 622 * to BIFring instead of general iv ring. However, due to known bif ring 623 * hw bug, it has to be disabled. There is no chance the process function 624 * will be involked. Just left it as a dummy one. 625 */ 626 return 0; 627 } 628 629 static int nbio_v7_9_set_ras_err_event_athub_irq_state(struct amdgpu_device *adev, 630 struct amdgpu_irq_src *src, 631 unsigned type, 632 enum amdgpu_interrupt_state state) 633 { 634 /* Dummy function, there is no initialization operation in driver */ 635 636 return 0; 637 } 638 639 static int nbio_v7_9_process_err_event_athub_irq(struct amdgpu_device *adev, 640 struct amdgpu_irq_src *source, 641 struct amdgpu_iv_entry *entry) 642 { 643 /* By design, the ih cookie for err_event_athub_irq should be written 644 * to BIFring instead of general iv ring. However, due to known bif ring 645 * hw bug, it has to be disabled. There is no chance the process function 646 * will be involked. Just left it as a dummy one. 647 */ 648 return 0; 649 } 650 651 static const struct amdgpu_irq_src_funcs nbio_v7_9_ras_controller_irq_funcs = { 652 .set = nbio_v7_9_set_ras_controller_irq_state, 653 .process = nbio_v7_9_process_ras_controller_irq, 654 }; 655 656 static const struct amdgpu_irq_src_funcs nbio_v7_9_ras_err_event_athub_irq_funcs = { 657 .set = nbio_v7_9_set_ras_err_event_athub_irq_state, 658 .process = nbio_v7_9_process_err_event_athub_irq, 659 }; 660 661 static int nbio_v7_9_init_ras_controller_interrupt (struct amdgpu_device *adev) 662 { 663 int r; 664 665 /* init the irq funcs */ 666 adev->nbio.ras_controller_irq.funcs = 667 &nbio_v7_9_ras_controller_irq_funcs; 668 adev->nbio.ras_controller_irq.num_types = 1; 669 670 /* register ras controller interrupt */ 671 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF, 672 NBIF_7_4__SRCID__RAS_CONTROLLER_INTERRUPT, 673 &adev->nbio.ras_controller_irq); 674 675 return r; 676 } 677 678 static int nbio_v7_9_init_ras_err_event_athub_interrupt (struct amdgpu_device *adev) 679 { 680 681 int r; 682 683 /* init the irq funcs */ 684 adev->nbio.ras_err_event_athub_irq.funcs = 685 &nbio_v7_9_ras_err_event_athub_irq_funcs; 686 adev->nbio.ras_err_event_athub_irq.num_types = 1; 687 688 /* register ras err event athub interrupt */ 689 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF, 690 NBIF_7_4__SRCID__ERREVENT_ATHUB_INTERRUPT, 691 &adev->nbio.ras_err_event_athub_irq); 692 693 return r; 694 } 695 696 const struct amdgpu_ras_block_hw_ops nbio_v7_9_ras_hw_ops = { 697 .query_ras_error_count = nbio_v7_9_query_ras_error_count, 698 }; 699 700 struct amdgpu_nbio_ras nbio_v7_9_ras = { 701 .ras_block = { 702 .ras_comm = { 703 .name = "pcie_bif", 704 .block = AMDGPU_RAS_BLOCK__PCIE_BIF, 705 .type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 706 }, 707 .hw_ops = &nbio_v7_9_ras_hw_ops, 708 .ras_late_init = amdgpu_nbio_ras_late_init, 709 }, 710 .handle_ras_controller_intr_no_bifring = nbio_v7_9_handle_ras_controller_intr_no_bifring, 711 .handle_ras_err_event_athub_intr_no_bifring = nbio_v7_9_handle_ras_err_event_athub_intr_no_bifring, 712 .init_ras_controller_interrupt = nbio_v7_9_init_ras_controller_interrupt, 713 .init_ras_err_event_athub_interrupt = nbio_v7_9_init_ras_err_event_athub_interrupt, 714 }; 715