1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "amdgpu.h" 24 #include "nbio_v7_9.h" 25 #include "amdgpu_ras.h" 26 27 #include "nbio/nbio_7_9_0_offset.h" 28 #include "nbio/nbio_7_9_0_sh_mask.h" 29 #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h" 30 #include <uapi/linux/kfd_ioctl.h> 31 32 #define NPS_MODE_MASK 0x000000FFL 33 34 /* Core 0 Port 0 counter */ 35 #define smnPCIEP_NAK_COUNTER 0x1A340218 36 37 static void nbio_v7_9_remap_hdp_registers(struct amdgpu_device *adev) 38 { 39 WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL, 40 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL); 41 WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL, 42 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL); 43 } 44 45 static u32 nbio_v7_9_get_rev_id(struct amdgpu_device *adev) 46 { 47 u32 tmp; 48 49 tmp = IP_VERSION_SUBREV(amdgpu_ip_version_full(adev, NBIO_HWIP, 0)); 50 /* If it is VF or subrevision holds a non-zero value, that should be used */ 51 if (tmp || amdgpu_sriov_vf(adev)) 52 return tmp; 53 54 /* If discovery subrev is not updated, use register version */ 55 tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0); 56 tmp = REG_GET_FIELD(tmp, RCC_STRAP0_RCC_DEV0_EPF0_STRAP0, 57 STRAP_ATI_REV_ID_DEV0_F0); 58 59 return tmp; 60 } 61 62 static void nbio_v7_9_mc_access_enable(struct amdgpu_device *adev, bool enable) 63 { 64 if (enable) 65 WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN, 66 BIF_BX0_BIF_FB_EN__FB_READ_EN_MASK | BIF_BX0_BIF_FB_EN__FB_WRITE_EN_MASK); 67 else 68 WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN, 0); 69 } 70 71 static u32 nbio_v7_9_get_memsize(struct amdgpu_device *adev) 72 { 73 return RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE); 74 } 75 76 static void nbio_v7_9_sdma_doorbell_range(struct amdgpu_device *adev, int instance, 77 bool use_doorbell, int doorbell_index, int doorbell_size) 78 { 79 u32 doorbell_range = 0, doorbell_ctrl = 0; 80 int aid_id, dev_inst; 81 82 dev_inst = GET_INST(SDMA0, instance); 83 aid_id = adev->sdma.instance[instance].aid_id; 84 85 if (use_doorbell == false) 86 return; 87 88 doorbell_range = 89 REG_SET_FIELD(doorbell_range, DOORBELL0_CTRL_ENTRY_0, 90 BIF_DOORBELL0_RANGE_OFFSET_ENTRY, doorbell_index); 91 doorbell_range = 92 REG_SET_FIELD(doorbell_range, DOORBELL0_CTRL_ENTRY_0, 93 BIF_DOORBELL0_RANGE_SIZE_ENTRY, doorbell_size); 94 doorbell_ctrl = 95 REG_SET_FIELD(doorbell_ctrl, S2A_DOORBELL_ENTRY_1_CTRL, 96 S2A_DOORBELL_PORT1_ENABLE, 1); 97 doorbell_ctrl = 98 REG_SET_FIELD(doorbell_ctrl, S2A_DOORBELL_ENTRY_1_CTRL, 99 S2A_DOORBELL_PORT1_RANGE_SIZE, doorbell_size); 100 101 switch (dev_inst % adev->sdma.num_inst_per_aid) { 102 case 0: 103 WREG32_SOC15_OFFSET(NBIO, 0, regDOORBELL0_CTRL_ENTRY_1, 104 4 * aid_id, doorbell_range); 105 106 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, 107 S2A_DOORBELL_ENTRY_1_CTRL, 108 S2A_DOORBELL_PORT1_AWID, 0xe); 109 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, 110 S2A_DOORBELL_ENTRY_1_CTRL, 111 S2A_DOORBELL_PORT1_RANGE_OFFSET, 0xe); 112 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, 113 S2A_DOORBELL_ENTRY_1_CTRL, 114 S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE, 115 0x1); 116 WREG32_SOC15_EXT(NBIO, aid_id, regS2A_DOORBELL_ENTRY_1_CTRL, 117 aid_id, doorbell_ctrl); 118 break; 119 case 1: 120 WREG32_SOC15_OFFSET(NBIO, 0, regDOORBELL0_CTRL_ENTRY_2, 121 4 * aid_id, doorbell_range); 122 123 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, 124 S2A_DOORBELL_ENTRY_1_CTRL, 125 S2A_DOORBELL_PORT1_AWID, 0x8); 126 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, 127 S2A_DOORBELL_ENTRY_1_CTRL, 128 S2A_DOORBELL_PORT1_RANGE_OFFSET, 0x8); 129 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, 130 S2A_DOORBELL_ENTRY_1_CTRL, 131 S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE, 132 0x2); 133 WREG32_SOC15_EXT(NBIO, aid_id, regS2A_DOORBELL_ENTRY_2_CTRL, 134 aid_id, doorbell_ctrl); 135 break; 136 case 2: 137 WREG32_SOC15_OFFSET(NBIO, 0, regDOORBELL0_CTRL_ENTRY_3, 138 4 * aid_id, doorbell_range); 139 140 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, 141 S2A_DOORBELL_ENTRY_1_CTRL, 142 S2A_DOORBELL_PORT1_AWID, 0x9); 143 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, 144 S2A_DOORBELL_ENTRY_1_CTRL, 145 S2A_DOORBELL_PORT1_RANGE_OFFSET, 0x9); 146 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, 147 S2A_DOORBELL_ENTRY_1_CTRL, 148 S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE, 149 0x8); 150 WREG32_SOC15_EXT(NBIO, aid_id, regS2A_DOORBELL_ENTRY_5_CTRL, 151 aid_id, doorbell_ctrl); 152 break; 153 case 3: 154 WREG32_SOC15_OFFSET(NBIO, 0, regDOORBELL0_CTRL_ENTRY_4, 155 4 * aid_id, doorbell_range); 156 157 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, 158 S2A_DOORBELL_ENTRY_1_CTRL, 159 S2A_DOORBELL_PORT1_AWID, 0xa); 160 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, 161 S2A_DOORBELL_ENTRY_1_CTRL, 162 S2A_DOORBELL_PORT1_RANGE_OFFSET, 0xa); 163 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, 164 S2A_DOORBELL_ENTRY_1_CTRL, 165 S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE, 166 0x9); 167 WREG32_SOC15_EXT(NBIO, aid_id, regS2A_DOORBELL_ENTRY_6_CTRL, 168 aid_id, doorbell_ctrl); 169 break; 170 default: 171 break; 172 } 173 } 174 175 static void nbio_v7_9_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell, 176 int doorbell_index, int instance) 177 { 178 u32 doorbell_range = 0, doorbell_ctrl = 0; 179 u32 aid_id = instance; 180 181 if (use_doorbell) { 182 doorbell_range = REG_SET_FIELD(doorbell_range, 183 DOORBELL0_CTRL_ENTRY_0, 184 BIF_DOORBELL0_RANGE_OFFSET_ENTRY, 185 doorbell_index); 186 doorbell_range = REG_SET_FIELD(doorbell_range, 187 DOORBELL0_CTRL_ENTRY_0, 188 BIF_DOORBELL0_RANGE_SIZE_ENTRY, 189 0x9); 190 if (aid_id) 191 doorbell_range = REG_SET_FIELD(doorbell_range, 192 DOORBELL0_CTRL_ENTRY_0, 193 DOORBELL0_FENCE_ENABLE_ENTRY, 194 0x4); 195 196 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, 197 S2A_DOORBELL_ENTRY_1_CTRL, 198 S2A_DOORBELL_PORT1_ENABLE, 1); 199 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, 200 S2A_DOORBELL_ENTRY_1_CTRL, 201 S2A_DOORBELL_PORT1_AWID, 0x4); 202 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, 203 S2A_DOORBELL_ENTRY_1_CTRL, 204 S2A_DOORBELL_PORT1_RANGE_OFFSET, 0x4); 205 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, 206 S2A_DOORBELL_ENTRY_1_CTRL, 207 S2A_DOORBELL_PORT1_RANGE_SIZE, 0x9); 208 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, 209 S2A_DOORBELL_ENTRY_1_CTRL, 210 S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE, 0x4); 211 212 WREG32_SOC15_OFFSET(NBIO, 0, regDOORBELL0_CTRL_ENTRY_17, 213 aid_id, doorbell_range); 214 WREG32_SOC15_EXT(NBIO, aid_id, regS2A_DOORBELL_ENTRY_4_CTRL, 215 aid_id, doorbell_ctrl); 216 } else { 217 doorbell_range = REG_SET_FIELD(doorbell_range, 218 DOORBELL0_CTRL_ENTRY_0, 219 BIF_DOORBELL0_RANGE_SIZE_ENTRY, 0); 220 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl, 221 S2A_DOORBELL_ENTRY_1_CTRL, 222 S2A_DOORBELL_PORT1_RANGE_SIZE, 0); 223 224 WREG32_SOC15_OFFSET(NBIO, 0, regDOORBELL0_CTRL_ENTRY_17, 225 aid_id, doorbell_range); 226 WREG32_SOC15_EXT(NBIO, aid_id, regS2A_DOORBELL_ENTRY_4_CTRL, 227 aid_id, doorbell_ctrl); 228 } 229 } 230 231 static void nbio_v7_9_enable_doorbell_aperture(struct amdgpu_device *adev, 232 bool enable) 233 { 234 /* Enable to allow doorbell pass thru on pre-silicon bare-metal */ 235 WREG32_SOC15(NBIO, 0, regBIFC_DOORBELL_ACCESS_EN_PF, 0xfffff); 236 WREG32_FIELD15_PREREG(NBIO, 0, RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN, 237 BIF_DOORBELL_APER_EN, enable ? 1 : 0); 238 } 239 240 static void nbio_v7_9_enable_doorbell_selfring_aperture(struct amdgpu_device *adev, 241 bool enable) 242 { 243 u32 tmp = 0; 244 245 if (enable) { 246 tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, 247 DOORBELL_SELFRING_GPA_APER_EN, 1) | 248 REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, 249 DOORBELL_SELFRING_GPA_APER_MODE, 1) | 250 REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, 251 DOORBELL_SELFRING_GPA_APER_SIZE, 0); 252 253 WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW, 254 lower_32_bits(adev->doorbell.base)); 255 WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH, 256 upper_32_bits(adev->doorbell.base)); 257 } 258 259 WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, tmp); 260 } 261 262 static void nbio_v7_9_ih_doorbell_range(struct amdgpu_device *adev, 263 bool use_doorbell, int doorbell_index) 264 { 265 u32 ih_doorbell_range = 0, ih_doorbell_ctrl = 0; 266 267 if (use_doorbell) { 268 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 269 DOORBELL0_CTRL_ENTRY_0, 270 BIF_DOORBELL0_RANGE_OFFSET_ENTRY, 271 doorbell_index); 272 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 273 DOORBELL0_CTRL_ENTRY_0, 274 BIF_DOORBELL0_RANGE_SIZE_ENTRY, 275 0x8); 276 277 ih_doorbell_ctrl = REG_SET_FIELD(ih_doorbell_ctrl, 278 S2A_DOORBELL_ENTRY_1_CTRL, 279 S2A_DOORBELL_PORT1_ENABLE, 1); 280 ih_doorbell_ctrl = REG_SET_FIELD(ih_doorbell_ctrl, 281 S2A_DOORBELL_ENTRY_1_CTRL, 282 S2A_DOORBELL_PORT1_AWID, 0); 283 ih_doorbell_ctrl = REG_SET_FIELD(ih_doorbell_ctrl, 284 S2A_DOORBELL_ENTRY_1_CTRL, 285 S2A_DOORBELL_PORT1_RANGE_OFFSET, 0); 286 ih_doorbell_ctrl = REG_SET_FIELD(ih_doorbell_ctrl, 287 S2A_DOORBELL_ENTRY_1_CTRL, 288 S2A_DOORBELL_PORT1_RANGE_SIZE, 0x8); 289 ih_doorbell_ctrl = REG_SET_FIELD(ih_doorbell_ctrl, 290 S2A_DOORBELL_ENTRY_1_CTRL, 291 S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE, 0); 292 } else { 293 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 294 DOORBELL0_CTRL_ENTRY_0, 295 BIF_DOORBELL0_RANGE_SIZE_ENTRY, 0); 296 ih_doorbell_ctrl = REG_SET_FIELD(ih_doorbell_ctrl, 297 S2A_DOORBELL_ENTRY_1_CTRL, 298 S2A_DOORBELL_PORT1_RANGE_SIZE, 0); 299 } 300 301 WREG32_SOC15(NBIO, 0, regDOORBELL0_CTRL_ENTRY_0, ih_doorbell_range); 302 WREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_3_CTRL, ih_doorbell_ctrl); 303 } 304 305 306 static void nbio_v7_9_update_medium_grain_clock_gating(struct amdgpu_device *adev, 307 bool enable) 308 { 309 } 310 311 static void nbio_v7_9_update_medium_grain_light_sleep(struct amdgpu_device *adev, 312 bool enable) 313 { 314 } 315 316 static void nbio_v7_9_get_clockgating_state(struct amdgpu_device *adev, 317 u64 *flags) 318 { 319 } 320 321 static void nbio_v7_9_ih_control(struct amdgpu_device *adev) 322 { 323 u32 interrupt_cntl; 324 325 /* setup interrupt control */ 326 WREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL2, adev->dummy_page_addr >> 8); 327 interrupt_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL); 328 /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi 329 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN 330 */ 331 interrupt_cntl = 332 REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0); 333 /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */ 334 interrupt_cntl = 335 REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0); 336 WREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL, interrupt_cntl); 337 } 338 339 static u32 nbio_v7_9_get_hdp_flush_req_offset(struct amdgpu_device *adev) 340 { 341 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_REQ); 342 } 343 344 static u32 nbio_v7_9_get_hdp_flush_done_offset(struct amdgpu_device *adev) 345 { 346 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_DONE); 347 } 348 349 static u32 nbio_v7_9_get_pcie_index_offset(struct amdgpu_device *adev) 350 { 351 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_INDEX2); 352 } 353 354 static u32 nbio_v7_9_get_pcie_data_offset(struct amdgpu_device *adev) 355 { 356 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_DATA2); 357 } 358 359 static u32 nbio_v7_9_get_pcie_index_hi_offset(struct amdgpu_device *adev) 360 { 361 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_INDEX2_HI); 362 } 363 364 const struct nbio_hdp_flush_reg nbio_v7_9_hdp_flush_reg = { 365 .ref_and_mask_cp0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK, 366 .ref_and_mask_cp1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1_MASK, 367 .ref_and_mask_cp2 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2_MASK, 368 .ref_and_mask_cp3 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3_MASK, 369 .ref_and_mask_cp4 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4_MASK, 370 .ref_and_mask_cp5 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5_MASK, 371 .ref_and_mask_cp6 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6_MASK, 372 .ref_and_mask_cp7 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7_MASK, 373 .ref_and_mask_cp8 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8_MASK, 374 .ref_and_mask_cp9 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9_MASK, 375 .ref_and_mask_sdma0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK, 376 .ref_and_mask_sdma1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK, 377 .ref_and_mask_sdma2 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK, 378 .ref_and_mask_sdma3 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK, 379 .ref_and_mask_sdma4 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK, 380 .ref_and_mask_sdma5 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK, 381 .ref_and_mask_sdma6 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK, 382 .ref_and_mask_sdma7 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK, 383 }; 384 385 static void nbio_v7_9_enable_doorbell_interrupt(struct amdgpu_device *adev, 386 bool enable) 387 { 388 WREG32_FIELD15_PREREG(NBIO, 0, BIF_BX0_BIF_DOORBELL_INT_CNTL, 389 DOORBELL_INTERRUPT_DISABLE, enable ? 0 : 1); 390 } 391 392 static int nbio_v7_9_get_compute_partition_mode(struct amdgpu_device *adev) 393 { 394 u32 tmp, px; 395 396 tmp = RREG32_SOC15(NBIO, 0, regBIF_BX_PF0_PARTITION_COMPUTE_STATUS); 397 px = REG_GET_FIELD(tmp, BIF_BX_PF0_PARTITION_COMPUTE_STATUS, 398 PARTITION_MODE); 399 400 return px; 401 } 402 403 static bool nbio_v7_9_is_nps_switch_requested(struct amdgpu_device *adev) 404 { 405 u32 tmp; 406 407 tmp = RREG32_SOC15(NBIO, 0, regBIF_BX_PF0_PARTITION_MEM_STATUS); 408 tmp = REG_GET_FIELD(tmp, BIF_BX_PF0_PARTITION_MEM_STATUS, 409 CHANGE_STATUE); 410 411 /* 0x8 - NPS switch requested */ 412 return (tmp == 0x8); 413 } 414 static u32 nbio_v7_9_get_memory_partition_mode(struct amdgpu_device *adev, 415 u32 *supp_modes) 416 { 417 u32 tmp; 418 419 tmp = RREG32_SOC15(NBIO, 0, regBIF_BX_PF0_PARTITION_MEM_STATUS); 420 tmp = REG_GET_FIELD(tmp, BIF_BX_PF0_PARTITION_MEM_STATUS, NPS_MODE); 421 422 if (supp_modes) { 423 *supp_modes = 424 RREG32_SOC15(NBIO, 0, regBIF_BX_PF0_PARTITION_MEM_CAP); 425 } 426 427 return ffs(tmp); 428 } 429 430 static void nbio_v7_9_init_registers(struct amdgpu_device *adev) 431 { 432 u32 inst_mask; 433 int i; 434 435 WREG32_SOC15(NBIO, 0, regXCC_DOORBELL_FENCE, 436 0xff & ~(adev->gfx.xcc_mask)); 437 438 WREG32_SOC15(NBIO, 0, regBIFC_GFX_INT_MONITOR_MASK, 0x7ff); 439 440 inst_mask = adev->aid_mask & ~1U; 441 for_each_inst(i, inst_mask) { 442 WREG32_SOC15_EXT(NBIO, i, regXCC_DOORBELL_FENCE, i, 443 XCC_DOORBELL_FENCE__SHUB_SLV_MODE_MASK); 444 445 } 446 447 if (!amdgpu_sriov_vf(adev)) { 448 u32 baco_cntl; 449 for_each_inst(i, adev->aid_mask) { 450 baco_cntl = RREG32_SOC15(NBIO, i, regBIF_BX0_BACO_CNTL); 451 if (baco_cntl & (BIF_BX0_BACO_CNTL__BACO_DUMMY_EN_MASK | 452 BIF_BX0_BACO_CNTL__BACO_EN_MASK)) { 453 baco_cntl &= ~( 454 BIF_BX0_BACO_CNTL__BACO_DUMMY_EN_MASK | 455 BIF_BX0_BACO_CNTL__BACO_EN_MASK); 456 dev_dbg(adev->dev, 457 "Unsetting baco dummy mode %x", 458 baco_cntl); 459 WREG32_SOC15(NBIO, i, regBIF_BX0_BACO_CNTL, 460 baco_cntl); 461 } 462 } 463 } 464 } 465 466 static u64 nbio_v7_9_get_pcie_replay_count(struct amdgpu_device *adev) 467 { 468 u32 val, nak_r, nak_g; 469 470 if (adev->flags & AMD_IS_APU) 471 return 0; 472 473 /* Get the number of NAKs received and generated */ 474 val = RREG32_PCIE(smnPCIEP_NAK_COUNTER); 475 nak_r = val & 0xFFFF; 476 nak_g = val >> 16; 477 478 /* Add the total number of NAKs, i.e the number of replays */ 479 return (nak_r + nak_g); 480 } 481 482 #define MMIO_REG_HOLE_OFFSET 0x1A000 483 484 static void nbio_v7_9_set_reg_remap(struct amdgpu_device *adev) 485 { 486 if (!amdgpu_sriov_vf(adev) && (PAGE_SIZE <= 4096)) { 487 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; 488 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; 489 } else { 490 adev->rmmio_remap.reg_offset = 491 SOC15_REG_OFFSET( 492 NBIO, 0, 493 regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL) 494 << 2; 495 adev->rmmio_remap.bus_addr = 0; 496 } 497 } 498 499 const struct amdgpu_nbio_funcs nbio_v7_9_funcs = { 500 .get_hdp_flush_req_offset = nbio_v7_9_get_hdp_flush_req_offset, 501 .get_hdp_flush_done_offset = nbio_v7_9_get_hdp_flush_done_offset, 502 .get_pcie_index_offset = nbio_v7_9_get_pcie_index_offset, 503 .get_pcie_data_offset = nbio_v7_9_get_pcie_data_offset, 504 .get_pcie_index_hi_offset = nbio_v7_9_get_pcie_index_hi_offset, 505 .get_rev_id = nbio_v7_9_get_rev_id, 506 .mc_access_enable = nbio_v7_9_mc_access_enable, 507 .get_memsize = nbio_v7_9_get_memsize, 508 .sdma_doorbell_range = nbio_v7_9_sdma_doorbell_range, 509 .vcn_doorbell_range = nbio_v7_9_vcn_doorbell_range, 510 .enable_doorbell_aperture = nbio_v7_9_enable_doorbell_aperture, 511 .enable_doorbell_selfring_aperture = nbio_v7_9_enable_doorbell_selfring_aperture, 512 .ih_doorbell_range = nbio_v7_9_ih_doorbell_range, 513 .enable_doorbell_interrupt = nbio_v7_9_enable_doorbell_interrupt, 514 .update_medium_grain_clock_gating = nbio_v7_9_update_medium_grain_clock_gating, 515 .update_medium_grain_light_sleep = nbio_v7_9_update_medium_grain_light_sleep, 516 .get_clockgating_state = nbio_v7_9_get_clockgating_state, 517 .ih_control = nbio_v7_9_ih_control, 518 .remap_hdp_registers = nbio_v7_9_remap_hdp_registers, 519 .get_compute_partition_mode = nbio_v7_9_get_compute_partition_mode, 520 .get_memory_partition_mode = nbio_v7_9_get_memory_partition_mode, 521 .is_nps_switch_requested = nbio_v7_9_is_nps_switch_requested, 522 .init_registers = nbio_v7_9_init_registers, 523 .get_pcie_replay_count = nbio_v7_9_get_pcie_replay_count, 524 .set_reg_remap = nbio_v7_9_set_reg_remap, 525 }; 526 527 static void nbio_v7_9_query_ras_error_count(struct amdgpu_device *adev, 528 void *ras_error_status) 529 { 530 } 531 532 static void nbio_v7_9_handle_ras_controller_intr_no_bifring(struct amdgpu_device *adev) 533 { 534 uint32_t bif_doorbell_intr_cntl; 535 struct ras_manager *obj = amdgpu_ras_find_obj(adev, adev->nbio.ras_if); 536 struct ras_err_data err_data; 537 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 538 539 if (amdgpu_ras_error_data_init(&err_data)) 540 return; 541 542 bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_DOORBELL_INT_CNTL); 543 544 if (REG_GET_FIELD(bif_doorbell_intr_cntl, 545 BIF_BX0_BIF_DOORBELL_INT_CNTL, RAS_CNTLR_INTERRUPT_STATUS)) { 546 /* driver has to clear the interrupt status when bif ring is disabled */ 547 bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl, 548 BIF_BX0_BIF_DOORBELL_INT_CNTL, 549 RAS_CNTLR_INTERRUPT_CLEAR, 1); 550 WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl); 551 552 if (!ras->disable_ras_err_cnt_harvest) { 553 /* 554 * clear error status after ras_controller_intr 555 * according to hw team and count ue number 556 * for query 557 */ 558 nbio_v7_9_query_ras_error_count(adev, &err_data); 559 560 /* logging on error cnt and printing for awareness */ 561 obj->err_data.ue_count += err_data.ue_count; 562 obj->err_data.ce_count += err_data.ce_count; 563 564 if (err_data.ce_count) 565 dev_info(adev->dev, "%ld correctable hardware " 566 "errors detected in %s block\n", 567 obj->err_data.ce_count, 568 get_ras_block_str(adev->nbio.ras_if)); 569 570 if (err_data.ue_count) 571 dev_info(adev->dev, "%ld uncorrectable hardware " 572 "errors detected in %s block\n", 573 obj->err_data.ue_count, 574 get_ras_block_str(adev->nbio.ras_if)); 575 } 576 577 dev_info(adev->dev, "RAS controller interrupt triggered " 578 "by NBIF error\n"); 579 } 580 581 amdgpu_ras_error_data_fini(&err_data); 582 } 583 584 static void nbio_v7_9_handle_ras_err_event_athub_intr_no_bifring(struct amdgpu_device *adev) 585 { 586 uint32_t bif_doorbell_intr_cntl; 587 588 bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_DOORBELL_INT_CNTL); 589 590 if (REG_GET_FIELD(bif_doorbell_intr_cntl, 591 BIF_BX0_BIF_DOORBELL_INT_CNTL, RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS)) { 592 /* driver has to clear the interrupt status when bif ring is disabled */ 593 bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl, 594 BIF_BX0_BIF_DOORBELL_INT_CNTL, 595 RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR, 1); 596 597 WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl); 598 599 amdgpu_ras_global_ras_isr(adev); 600 } 601 } 602 603 static int nbio_v7_9_set_ras_controller_irq_state(struct amdgpu_device *adev, 604 struct amdgpu_irq_src *src, 605 unsigned type, 606 enum amdgpu_interrupt_state state) 607 { 608 /* Dummy function, there is no initialization operation in driver */ 609 610 return 0; 611 } 612 613 static int nbio_v7_9_process_ras_controller_irq(struct amdgpu_device *adev, 614 struct amdgpu_irq_src *source, 615 struct amdgpu_iv_entry *entry) 616 { 617 /* By design, the ih cookie for ras_controller_irq should be written 618 * to BIFring instead of general iv ring. However, due to known bif ring 619 * hw bug, it has to be disabled. There is no chance the process function 620 * will be involked. Just left it as a dummy one. 621 */ 622 return 0; 623 } 624 625 static int nbio_v7_9_set_ras_err_event_athub_irq_state(struct amdgpu_device *adev, 626 struct amdgpu_irq_src *src, 627 unsigned type, 628 enum amdgpu_interrupt_state state) 629 { 630 /* Dummy function, there is no initialization operation in driver */ 631 632 return 0; 633 } 634 635 static int nbio_v7_9_process_err_event_athub_irq(struct amdgpu_device *adev, 636 struct amdgpu_irq_src *source, 637 struct amdgpu_iv_entry *entry) 638 { 639 /* By design, the ih cookie for err_event_athub_irq should be written 640 * to BIFring instead of general iv ring. However, due to known bif ring 641 * hw bug, it has to be disabled. There is no chance the process function 642 * will be involked. Just left it as a dummy one. 643 */ 644 return 0; 645 } 646 647 static const struct amdgpu_irq_src_funcs nbio_v7_9_ras_controller_irq_funcs = { 648 .set = nbio_v7_9_set_ras_controller_irq_state, 649 .process = nbio_v7_9_process_ras_controller_irq, 650 }; 651 652 static const struct amdgpu_irq_src_funcs nbio_v7_9_ras_err_event_athub_irq_funcs = { 653 .set = nbio_v7_9_set_ras_err_event_athub_irq_state, 654 .process = nbio_v7_9_process_err_event_athub_irq, 655 }; 656 657 static int nbio_v7_9_init_ras_controller_interrupt (struct amdgpu_device *adev) 658 { 659 int r; 660 661 /* init the irq funcs */ 662 adev->nbio.ras_controller_irq.funcs = 663 &nbio_v7_9_ras_controller_irq_funcs; 664 adev->nbio.ras_controller_irq.num_types = 1; 665 666 /* register ras controller interrupt */ 667 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF, 668 NBIF_7_4__SRCID__RAS_CONTROLLER_INTERRUPT, 669 &adev->nbio.ras_controller_irq); 670 671 return r; 672 } 673 674 static int nbio_v7_9_init_ras_err_event_athub_interrupt (struct amdgpu_device *adev) 675 { 676 677 int r; 678 679 /* init the irq funcs */ 680 adev->nbio.ras_err_event_athub_irq.funcs = 681 &nbio_v7_9_ras_err_event_athub_irq_funcs; 682 adev->nbio.ras_err_event_athub_irq.num_types = 1; 683 684 /* register ras err event athub interrupt */ 685 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF, 686 NBIF_7_4__SRCID__ERREVENT_ATHUB_INTERRUPT, 687 &adev->nbio.ras_err_event_athub_irq); 688 689 return r; 690 } 691 692 const struct amdgpu_ras_block_hw_ops nbio_v7_9_ras_hw_ops = { 693 .query_ras_error_count = nbio_v7_9_query_ras_error_count, 694 }; 695 696 struct amdgpu_nbio_ras nbio_v7_9_ras = { 697 .ras_block = { 698 .ras_comm = { 699 .name = "pcie_bif", 700 .block = AMDGPU_RAS_BLOCK__PCIE_BIF, 701 .type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 702 }, 703 .hw_ops = &nbio_v7_9_ras_hw_ops, 704 .ras_late_init = amdgpu_nbio_ras_late_init, 705 }, 706 .handle_ras_controller_intr_no_bifring = nbio_v7_9_handle_ras_controller_intr_no_bifring, 707 .handle_ras_err_event_athub_intr_no_bifring = nbio_v7_9_handle_ras_err_event_athub_intr_no_bifring, 708 .init_ras_controller_interrupt = nbio_v7_9_init_ras_controller_interrupt, 709 .init_ras_err_event_athub_interrupt = nbio_v7_9_init_ras_err_event_athub_interrupt, 710 }; 711