1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "amdgpu.h" 24 #include "amdgpu_atombios.h" 25 #include "nbio_v7_4.h" 26 #include "amdgpu_ras.h" 27 28 #include "nbio/nbio_7_4_offset.h" 29 #include "nbio/nbio_7_4_sh_mask.h" 30 #include "nbio/nbio_7_4_0_smn.h" 31 #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h" 32 #include <uapi/linux/kfd_ioctl.h> 33 34 #define smnPCIE_LC_CNTL 0x11140280 35 #define smnPCIE_LC_CNTL3 0x111402d4 36 #define smnPCIE_LC_CNTL6 0x111402ec 37 #define smnPCIE_LC_CNTL7 0x111402f0 38 #define smnNBIF_MGCG_CTRL_LCLK 0x1013a21c 39 #define smnRCC_BIF_STRAP3 0x1012348c 40 #define RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK 0x0000FFFFL 41 #define RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK 0xFFFF0000L 42 #define smnRCC_BIF_STRAP5 0x10123494 43 #define RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK 0x0000FFFFL 44 #define smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2 0x1014008c 45 #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L 46 #define smnBIF_CFG_DEV0_EPF0_PCIE_LTR_CAP 0x10140324 47 #define smnPSWUSP0_PCIE_LC_CNTL2 0x111402c4 48 #define smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL 0x10123538 49 #define smnRCC_BIF_STRAP2 0x10123488 50 #define RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK 0x00004000L 51 #define RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT 0x0 52 #define RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT 0x10 53 #define RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT 0x0 54 55 /* 56 * These are nbio v7_4_1 registers mask. Temporarily define these here since 57 * nbio v7_4_1 header is incomplete. 58 */ 59 #define GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L /* Don't use. Firmware uses this bit internally */ 60 #define GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L 61 #define GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L 62 #define GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L 63 #define GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L 64 #define GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L 65 #define GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L 66 #define GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L 67 #define GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L 68 69 #define mmBIF_MMSCH1_DOORBELL_RANGE 0x01dc 70 #define mmBIF_MMSCH1_DOORBELL_RANGE_BASE_IDX 2 71 //BIF_MMSCH1_DOORBELL_RANGE 72 #define BIF_MMSCH1_DOORBELL_RANGE__OFFSET__SHIFT 0x2 73 #define BIF_MMSCH1_DOORBELL_RANGE__SIZE__SHIFT 0x10 74 #define BIF_MMSCH1_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL 75 #define BIF_MMSCH1_DOORBELL_RANGE__SIZE_MASK 0x001F0000L 76 77 #define BIF_MMSCH1_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL 78 #define BIF_MMSCH1_DOORBELL_RANGE__SIZE_MASK 0x001F0000L 79 80 #define mmBIF_MMSCH1_DOORBELL_RANGE_ALDE 0x01d8 81 #define mmBIF_MMSCH1_DOORBELL_RANGE_ALDE_BASE_IDX 2 82 //BIF_MMSCH1_DOORBELL_ALDE_RANGE 83 #define BIF_MMSCH1_DOORBELL_RANGE_ALDE__OFFSET__SHIFT 0x2 84 #define BIF_MMSCH1_DOORBELL_RANGE_ALDE__SIZE__SHIFT 0x10 85 #define BIF_MMSCH1_DOORBELL_RANGE_ALDE__OFFSET_MASK 0x00000FFCL 86 #define BIF_MMSCH1_DOORBELL_RANGE_ALDE__SIZE_MASK 0x001F0000L 87 88 #define mmRCC_DEV0_EPF0_STRAP0_ALDE 0x0015 89 #define mmRCC_DEV0_EPF0_STRAP0_ALDE_BASE_IDX 2 90 91 #define mmBIF_DOORBELL_INT_CNTL_ALDE 0x00fe 92 #define mmBIF_DOORBELL_INT_CNTL_ALDE_BASE_IDX 2 93 #define BIF_DOORBELL_INT_CNTL_ALDE__DOORBELL_INTERRUPT_DISABLE__SHIFT 0x18 94 #define BIF_DOORBELL_INT_CNTL_ALDE__DOORBELL_INTERRUPT_DISABLE_MASK 0x01000000L 95 96 #define mmBIF_INTR_CNTL_ALDE 0x0101 97 #define mmBIF_INTR_CNTL_ALDE_BASE_IDX 2 98 99 static void nbio_v7_4_query_ras_error_count(struct amdgpu_device *adev, 100 void *ras_error_status); 101 102 static void nbio_v7_4_remap_hdp_registers(struct amdgpu_device *adev) 103 { 104 WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL, 105 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL); 106 WREG32_SOC15(NBIO, 0, mmREMAP_HDP_REG_FLUSH_CNTL, 107 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL); 108 } 109 110 static u32 nbio_v7_4_get_rev_id(struct amdgpu_device *adev) 111 { 112 u32 tmp; 113 114 if (adev->asic_type == CHIP_ALDEBARAN) 115 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0_ALDE); 116 else 117 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0); 118 119 tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK; 120 tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT; 121 122 return tmp; 123 } 124 125 static void nbio_v7_4_mc_access_enable(struct amdgpu_device *adev, bool enable) 126 { 127 if (enable) 128 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 129 BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK); 130 else 131 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0); 132 } 133 134 static u32 nbio_v7_4_get_memsize(struct amdgpu_device *adev) 135 { 136 return RREG32_SOC15(NBIO, 0, mmRCC_CONFIG_MEMSIZE); 137 } 138 139 static void nbio_v7_4_sdma_doorbell_range(struct amdgpu_device *adev, int instance, 140 bool use_doorbell, int doorbell_index, int doorbell_size) 141 { 142 u32 reg, doorbell_range; 143 144 if (instance < 2) { 145 reg = instance + 146 SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE); 147 } else { 148 /* 149 * These registers address of SDMA2~7 is not consecutive 150 * from SDMA0~1. Need plus 4 dwords offset. 151 * 152 * BIF_SDMA0_DOORBELL_RANGE: 0x3bc0 153 * BIF_SDMA1_DOORBELL_RANGE: 0x3bc4 154 * BIF_SDMA2_DOORBELL_RANGE: 0x3bd8 155 + * BIF_SDMA4_DOORBELL_RANGE: 156 + * ARCTURUS: 0x3be0 157 + * ALDEBARAN: 0x3be4 158 */ 159 if (adev->asic_type == CHIP_ALDEBARAN && instance == 4) 160 reg = instance + 0x4 + 0x1 + 161 SOC15_REG_OFFSET(NBIO, 0, 162 mmBIF_SDMA0_DOORBELL_RANGE); 163 else 164 reg = instance + 0x4 + 165 SOC15_REG_OFFSET(NBIO, 0, 166 mmBIF_SDMA0_DOORBELL_RANGE); 167 } 168 169 doorbell_range = RREG32(reg); 170 171 if (use_doorbell) { 172 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index); 173 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, doorbell_size); 174 } else 175 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0); 176 177 WREG32(reg, doorbell_range); 178 } 179 180 static void nbio_v7_4_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell, 181 int doorbell_index, int instance) 182 { 183 u32 reg; 184 u32 doorbell_range; 185 186 if (instance) { 187 if (adev->asic_type == CHIP_ALDEBARAN) 188 reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH1_DOORBELL_RANGE_ALDE); 189 else 190 reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH1_DOORBELL_RANGE); 191 } else 192 reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH0_DOORBELL_RANGE); 193 194 doorbell_range = RREG32(reg); 195 196 if (use_doorbell) { 197 doorbell_range = REG_SET_FIELD(doorbell_range, 198 BIF_MMSCH0_DOORBELL_RANGE, OFFSET, 199 doorbell_index); 200 doorbell_range = REG_SET_FIELD(doorbell_range, 201 BIF_MMSCH0_DOORBELL_RANGE, SIZE, 8); 202 } else 203 doorbell_range = REG_SET_FIELD(doorbell_range, 204 BIF_MMSCH0_DOORBELL_RANGE, SIZE, 0); 205 206 WREG32(reg, doorbell_range); 207 } 208 209 static void nbio_v7_4_enable_doorbell_aperture(struct amdgpu_device *adev, 210 bool enable) 211 { 212 WREG32_FIELD15(NBIO, 0, RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, enable ? 1 : 0); 213 } 214 215 static void nbio_v7_4_enable_doorbell_selfring_aperture(struct amdgpu_device *adev, 216 bool enable) 217 { 218 u32 tmp = 0; 219 220 if (enable) { 221 tmp = REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_EN, 1) | 222 REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_MODE, 1) | 223 REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_SIZE, 0); 224 225 WREG32_SOC15(NBIO, 0, mmDOORBELL_SELFRING_GPA_APER_BASE_LOW, 226 lower_32_bits(adev->doorbell.base)); 227 WREG32_SOC15(NBIO, 0, mmDOORBELL_SELFRING_GPA_APER_BASE_HIGH, 228 upper_32_bits(adev->doorbell.base)); 229 } 230 231 WREG32_SOC15(NBIO, 0, mmDOORBELL_SELFRING_GPA_APER_CNTL, tmp); 232 } 233 234 static void nbio_v7_4_ih_doorbell_range(struct amdgpu_device *adev, 235 bool use_doorbell, int doorbell_index) 236 { 237 u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0 , mmBIF_IH_DOORBELL_RANGE); 238 239 if (use_doorbell) { 240 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index); 241 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 8); 242 } else 243 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 0); 244 245 WREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE, ih_doorbell_range); 246 } 247 248 249 static void nbio_v7_4_update_medium_grain_clock_gating(struct amdgpu_device *adev, 250 bool enable) 251 { 252 //TODO: Add support for v7.4 253 } 254 255 static void nbio_v7_4_update_medium_grain_light_sleep(struct amdgpu_device *adev, 256 bool enable) 257 { 258 uint32_t def, data; 259 260 def = data = RREG32_PCIE(smnPCIE_CNTL2); 261 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) { 262 data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK | 263 PCIE_CNTL2__MST_MEM_LS_EN_MASK | 264 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK); 265 } else { 266 data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK | 267 PCIE_CNTL2__MST_MEM_LS_EN_MASK | 268 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK); 269 } 270 271 if (def != data) 272 WREG32_PCIE(smnPCIE_CNTL2, data); 273 } 274 275 static void nbio_v7_4_get_clockgating_state(struct amdgpu_device *adev, 276 u64 *flags) 277 { 278 int data; 279 280 /* AMD_CG_SUPPORT_BIF_MGCG */ 281 data = RREG32_PCIE(smnCPM_CONTROL); 282 if (data & CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK) 283 *flags |= AMD_CG_SUPPORT_BIF_MGCG; 284 285 /* AMD_CG_SUPPORT_BIF_LS */ 286 data = RREG32_PCIE(smnPCIE_CNTL2); 287 if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK) 288 *flags |= AMD_CG_SUPPORT_BIF_LS; 289 } 290 291 static void nbio_v7_4_ih_control(struct amdgpu_device *adev) 292 { 293 u32 interrupt_cntl; 294 295 /* setup interrupt control */ 296 WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8); 297 interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL); 298 /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi 299 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN 300 */ 301 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0); 302 /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */ 303 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0); 304 WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl); 305 } 306 307 static u32 nbio_v7_4_get_hdp_flush_req_offset(struct amdgpu_device *adev) 308 { 309 return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_REQ); 310 } 311 312 static u32 nbio_v7_4_get_hdp_flush_done_offset(struct amdgpu_device *adev) 313 { 314 return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_DONE); 315 } 316 317 static u32 nbio_v7_4_get_pcie_index_offset(struct amdgpu_device *adev) 318 { 319 return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2); 320 } 321 322 static u32 nbio_v7_4_get_pcie_data_offset(struct amdgpu_device *adev) 323 { 324 return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2); 325 } 326 327 const struct nbio_hdp_flush_reg nbio_v7_4_hdp_flush_reg = { 328 .ref_and_mask_cp0 = GPU_HDP_FLUSH_DONE__CP0_MASK, 329 .ref_and_mask_cp1 = GPU_HDP_FLUSH_DONE__CP1_MASK, 330 .ref_and_mask_cp2 = GPU_HDP_FLUSH_DONE__CP2_MASK, 331 .ref_and_mask_cp3 = GPU_HDP_FLUSH_DONE__CP3_MASK, 332 .ref_and_mask_cp4 = GPU_HDP_FLUSH_DONE__CP4_MASK, 333 .ref_and_mask_cp5 = GPU_HDP_FLUSH_DONE__CP5_MASK, 334 .ref_and_mask_cp6 = GPU_HDP_FLUSH_DONE__CP6_MASK, 335 .ref_and_mask_cp7 = GPU_HDP_FLUSH_DONE__CP7_MASK, 336 .ref_and_mask_cp8 = GPU_HDP_FLUSH_DONE__CP8_MASK, 337 .ref_and_mask_cp9 = GPU_HDP_FLUSH_DONE__CP9_MASK, 338 .ref_and_mask_sdma0 = GPU_HDP_FLUSH_DONE__SDMA0_MASK, 339 .ref_and_mask_sdma1 = GPU_HDP_FLUSH_DONE__SDMA1_MASK, 340 }; 341 342 static void nbio_v7_4_init_registers(struct amdgpu_device *adev) 343 { 344 uint32_t baco_cntl; 345 346 if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 4, 4) && 347 !amdgpu_sriov_vf(adev)) { 348 baco_cntl = RREG32_SOC15(NBIO, 0, mmBACO_CNTL); 349 if (baco_cntl & 350 (BACO_CNTL__BACO_DUMMY_EN_MASK | BACO_CNTL__BACO_EN_MASK)) { 351 baco_cntl &= ~(BACO_CNTL__BACO_DUMMY_EN_MASK | 352 BACO_CNTL__BACO_EN_MASK); 353 dev_dbg(adev->dev, "Unsetting baco dummy mode %x", 354 baco_cntl); 355 WREG32_SOC15(NBIO, 0, mmBACO_CNTL, baco_cntl); 356 } 357 } 358 } 359 360 static void nbio_v7_4_handle_ras_controller_intr_no_bifring(struct amdgpu_device *adev) 361 { 362 uint32_t bif_doorbell_intr_cntl; 363 struct ras_manager *obj = amdgpu_ras_find_obj(adev, adev->nbio.ras_if); 364 struct ras_err_data err_data; 365 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 366 367 if (amdgpu_ras_error_data_init(&err_data)) 368 return; 369 370 if (adev->asic_type == CHIP_ALDEBARAN) 371 bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL_ALDE); 372 else 373 bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL); 374 375 if (REG_GET_FIELD(bif_doorbell_intr_cntl, 376 BIF_DOORBELL_INT_CNTL, RAS_CNTLR_INTERRUPT_STATUS)) { 377 /* driver has to clear the interrupt status when bif ring is disabled */ 378 bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl, 379 BIF_DOORBELL_INT_CNTL, 380 RAS_CNTLR_INTERRUPT_CLEAR, 1); 381 if (adev->asic_type == CHIP_ALDEBARAN) 382 WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL_ALDE, bif_doorbell_intr_cntl); 383 else 384 WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl); 385 386 if (ras && !ras->disable_ras_err_cnt_harvest && obj) { 387 /* 388 * clear error status after ras_controller_intr 389 * according to hw team and count ue number 390 * for query 391 */ 392 nbio_v7_4_query_ras_error_count(adev, &err_data); 393 394 /* logging on error cnt and printing for awareness */ 395 obj->err_data.ue_count += err_data.ue_count; 396 obj->err_data.ce_count += err_data.ce_count; 397 398 if (err_data.ce_count) 399 dev_info(adev->dev, "%ld correctable hardware " 400 "errors detected in %s block\n", 401 obj->err_data.ce_count, 402 get_ras_block_str(adev->nbio.ras_if)); 403 404 if (err_data.ue_count) 405 dev_info(adev->dev, "%ld uncorrectable hardware " 406 "errors detected in %s block\n", 407 obj->err_data.ue_count, 408 get_ras_block_str(adev->nbio.ras_if)); 409 } 410 411 dev_info(adev->dev, "RAS controller interrupt triggered " 412 "by NBIF error\n"); 413 414 /* ras_controller_int is dedicated for nbif ras error, 415 * not the global interrupt for sync flood 416 */ 417 amdgpu_ras_set_fed(adev, true); 418 amdgpu_ras_reset_gpu(adev); 419 } 420 421 amdgpu_ras_error_data_fini(&err_data); 422 } 423 424 static void nbio_v7_4_handle_ras_err_event_athub_intr_no_bifring(struct amdgpu_device *adev) 425 { 426 uint32_t bif_doorbell_intr_cntl; 427 428 if (adev->asic_type == CHIP_ALDEBARAN) 429 bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL_ALDE); 430 else 431 bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL); 432 433 if (REG_GET_FIELD(bif_doorbell_intr_cntl, 434 BIF_DOORBELL_INT_CNTL, RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS)) { 435 /* driver has to clear the interrupt status when bif ring is disabled */ 436 bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl, 437 BIF_DOORBELL_INT_CNTL, 438 RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR, 1); 439 440 if (adev->asic_type == CHIP_ALDEBARAN) 441 WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL_ALDE, bif_doorbell_intr_cntl); 442 else 443 WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl); 444 445 amdgpu_ras_global_ras_isr(adev); 446 } 447 } 448 449 450 static int nbio_v7_4_set_ras_controller_irq_state(struct amdgpu_device *adev, 451 struct amdgpu_irq_src *src, 452 unsigned type, 453 enum amdgpu_interrupt_state state) 454 { 455 /* The ras_controller_irq enablement should be done in psp bl when it 456 * tries to enable ras feature. Driver only need to set the correct interrupt 457 * vector for bare-metal and sriov use case respectively 458 */ 459 uint32_t bif_intr_cntl; 460 461 if (adev->asic_type == CHIP_ALDEBARAN) 462 bif_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL_ALDE); 463 else 464 bif_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL); 465 466 if (state == AMDGPU_IRQ_STATE_ENABLE) { 467 /* set interrupt vector select bit to 0 to select 468 * vetcor 1 for bare metal case */ 469 bif_intr_cntl = REG_SET_FIELD(bif_intr_cntl, 470 BIF_INTR_CNTL, 471 RAS_INTR_VEC_SEL, 0); 472 473 if (adev->asic_type == CHIP_ALDEBARAN) 474 WREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL_ALDE, bif_intr_cntl); 475 else 476 WREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL, bif_intr_cntl); 477 478 } 479 480 return 0; 481 } 482 483 static int nbio_v7_4_process_ras_controller_irq(struct amdgpu_device *adev, 484 struct amdgpu_irq_src *source, 485 struct amdgpu_iv_entry *entry) 486 { 487 /* By design, the ih cookie for ras_controller_irq should be written 488 * to BIFring instead of general iv ring. However, due to known bif ring 489 * hw bug, it has to be disabled. There is no chance the process function 490 * will be involked. Just left it as a dummy one. 491 */ 492 return 0; 493 } 494 495 static int nbio_v7_4_set_ras_err_event_athub_irq_state(struct amdgpu_device *adev, 496 struct amdgpu_irq_src *src, 497 unsigned type, 498 enum amdgpu_interrupt_state state) 499 { 500 /* The ras_controller_irq enablement should be done in psp bl when it 501 * tries to enable ras feature. Driver only need to set the correct interrupt 502 * vector for bare-metal and sriov use case respectively 503 */ 504 uint32_t bif_intr_cntl; 505 506 if (adev->asic_type == CHIP_ALDEBARAN) 507 bif_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL_ALDE); 508 else 509 bif_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL); 510 511 if (state == AMDGPU_IRQ_STATE_ENABLE) { 512 /* set interrupt vector select bit to 0 to select 513 * vetcor 1 for bare metal case */ 514 bif_intr_cntl = REG_SET_FIELD(bif_intr_cntl, 515 BIF_INTR_CNTL, 516 RAS_INTR_VEC_SEL, 0); 517 518 if (adev->asic_type == CHIP_ALDEBARAN) 519 WREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL_ALDE, bif_intr_cntl); 520 else 521 WREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL, bif_intr_cntl); 522 } 523 524 return 0; 525 } 526 527 static int nbio_v7_4_process_err_event_athub_irq(struct amdgpu_device *adev, 528 struct amdgpu_irq_src *source, 529 struct amdgpu_iv_entry *entry) 530 { 531 /* By design, the ih cookie for err_event_athub_irq should be written 532 * to BIFring instead of general iv ring. However, due to known bif ring 533 * hw bug, it has to be disabled. There is no chance the process function 534 * will be involked. Just left it as a dummy one. 535 */ 536 return 0; 537 } 538 539 static const struct amdgpu_irq_src_funcs nbio_v7_4_ras_controller_irq_funcs = { 540 .set = nbio_v7_4_set_ras_controller_irq_state, 541 .process = nbio_v7_4_process_ras_controller_irq, 542 }; 543 544 static const struct amdgpu_irq_src_funcs nbio_v7_4_ras_err_event_athub_irq_funcs = { 545 .set = nbio_v7_4_set_ras_err_event_athub_irq_state, 546 .process = nbio_v7_4_process_err_event_athub_irq, 547 }; 548 549 static int nbio_v7_4_init_ras_controller_interrupt (struct amdgpu_device *adev) 550 { 551 int r; 552 553 /* init the irq funcs */ 554 adev->nbio.ras_controller_irq.funcs = 555 &nbio_v7_4_ras_controller_irq_funcs; 556 adev->nbio.ras_controller_irq.num_types = 1; 557 558 /* register ras controller interrupt */ 559 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF, 560 NBIF_7_4__SRCID__RAS_CONTROLLER_INTERRUPT, 561 &adev->nbio.ras_controller_irq); 562 563 return r; 564 } 565 566 static int nbio_v7_4_init_ras_err_event_athub_interrupt (struct amdgpu_device *adev) 567 { 568 569 int r; 570 571 /* init the irq funcs */ 572 adev->nbio.ras_err_event_athub_irq.funcs = 573 &nbio_v7_4_ras_err_event_athub_irq_funcs; 574 adev->nbio.ras_err_event_athub_irq.num_types = 1; 575 576 /* register ras err event athub interrupt */ 577 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF, 578 NBIF_7_4__SRCID__ERREVENT_ATHUB_INTERRUPT, 579 &adev->nbio.ras_err_event_athub_irq); 580 581 return r; 582 } 583 584 #define smnPARITY_ERROR_STATUS_UNCORR_GRP2 0x13a20030 585 #define smnPARITY_ERROR_STATUS_UNCORR_GRP2_ALDE 0x13b20030 586 #define smnRAS_GLOBAL_STATUS_LO_ALDE 0x13b20020 587 588 static void nbio_v7_4_query_ras_error_count(struct amdgpu_device *adev, 589 void *ras_error_status) 590 { 591 uint32_t global_sts, central_sts, int_eoi, parity_sts; 592 uint32_t corr, fatal, non_fatal; 593 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 594 595 if (adev->asic_type == CHIP_ALDEBARAN) 596 global_sts = RREG32_PCIE(smnRAS_GLOBAL_STATUS_LO_ALDE); 597 else 598 global_sts = RREG32_PCIE(smnRAS_GLOBAL_STATUS_LO); 599 600 corr = REG_GET_FIELD(global_sts, RAS_GLOBAL_STATUS_LO, ParityErrCorr); 601 fatal = REG_GET_FIELD(global_sts, RAS_GLOBAL_STATUS_LO, ParityErrFatal); 602 non_fatal = REG_GET_FIELD(global_sts, RAS_GLOBAL_STATUS_LO, 603 ParityErrNonFatal); 604 605 if (adev->asic_type == CHIP_ALDEBARAN) 606 parity_sts = RREG32_PCIE(smnPARITY_ERROR_STATUS_UNCORR_GRP2_ALDE); 607 else 608 parity_sts = RREG32_PCIE(smnPARITY_ERROR_STATUS_UNCORR_GRP2); 609 610 if (corr) 611 err_data->ce_count++; 612 if (fatal) 613 err_data->ue_count++; 614 615 if (corr || fatal || non_fatal) { 616 central_sts = RREG32_PCIE(smnBIFL_RAS_CENTRAL_STATUS); 617 618 /* clear error status register */ 619 if (adev->asic_type == CHIP_ALDEBARAN) 620 WREG32_PCIE(smnRAS_GLOBAL_STATUS_LO_ALDE, global_sts); 621 else 622 WREG32_PCIE(smnRAS_GLOBAL_STATUS_LO, global_sts); 623 624 if (fatal) 625 { 626 /* clear parity fatal error indication field */ 627 if (adev->asic_type == CHIP_ALDEBARAN) 628 WREG32_PCIE(smnPARITY_ERROR_STATUS_UNCORR_GRP2_ALDE, parity_sts); 629 else 630 WREG32_PCIE(smnPARITY_ERROR_STATUS_UNCORR_GRP2, parity_sts); 631 } 632 633 if (REG_GET_FIELD(central_sts, BIFL_RAS_CENTRAL_STATUS, 634 BIFL_RasContller_Intr_Recv)) { 635 /* clear interrupt status register */ 636 WREG32_PCIE(smnBIFL_RAS_CENTRAL_STATUS, central_sts); 637 int_eoi = RREG32_PCIE(smnIOHC_INTERRUPT_EOI); 638 int_eoi = REG_SET_FIELD(int_eoi, 639 IOHC_INTERRUPT_EOI, SMI_EOI, 1); 640 WREG32_PCIE(smnIOHC_INTERRUPT_EOI, int_eoi); 641 } 642 } 643 } 644 645 static void nbio_v7_4_enable_doorbell_interrupt(struct amdgpu_device *adev, 646 bool enable) 647 { 648 if (adev->asic_type == CHIP_ALDEBARAN) 649 WREG32_FIELD15(NBIO, 0, BIF_DOORBELL_INT_CNTL_ALDE, 650 DOORBELL_INTERRUPT_DISABLE, enable ? 0 : 1); 651 else 652 WREG32_FIELD15(NBIO, 0, BIF_DOORBELL_INT_CNTL, 653 DOORBELL_INTERRUPT_DISABLE, enable ? 0 : 1); 654 } 655 656 const struct amdgpu_ras_block_hw_ops nbio_v7_4_ras_hw_ops = { 657 .query_ras_error_count = nbio_v7_4_query_ras_error_count, 658 }; 659 660 struct amdgpu_nbio_ras nbio_v7_4_ras = { 661 .ras_block = { 662 .ras_comm = { 663 .name = "pcie_bif", 664 .block = AMDGPU_RAS_BLOCK__PCIE_BIF, 665 .type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 666 }, 667 .hw_ops = &nbio_v7_4_ras_hw_ops, 668 .ras_late_init = amdgpu_nbio_ras_late_init, 669 }, 670 .handle_ras_controller_intr_no_bifring = nbio_v7_4_handle_ras_controller_intr_no_bifring, 671 .handle_ras_err_event_athub_intr_no_bifring = nbio_v7_4_handle_ras_err_event_athub_intr_no_bifring, 672 .init_ras_controller_interrupt = nbio_v7_4_init_ras_controller_interrupt, 673 .init_ras_err_event_athub_interrupt = nbio_v7_4_init_ras_err_event_athub_interrupt, 674 }; 675 676 677 #ifdef CONFIG_PCIEASPM 678 static void nbio_v7_4_program_ltr(struct amdgpu_device *adev) 679 { 680 uint32_t def, data; 681 682 WREG32_PCIE(smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL, 0x75EB); 683 684 def = data = RREG32_PCIE(smnRCC_BIF_STRAP2); 685 data &= ~RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK; 686 if (def != data) 687 WREG32_PCIE(smnRCC_BIF_STRAP2, data); 688 689 def = data = RREG32_PCIE(smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL); 690 data &= ~EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK; 691 if (def != data) 692 WREG32_PCIE(smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL, data); 693 694 def = data = RREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2); 695 data |= BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK; 696 if (def != data) 697 WREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2, data); 698 } 699 #endif 700 701 static void nbio_v7_4_program_aspm(struct amdgpu_device *adev) 702 { 703 #ifdef CONFIG_PCIEASPM 704 uint32_t def, data; 705 706 if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 4, 4)) 707 return; 708 709 def = data = RREG32_PCIE(smnPCIE_LC_CNTL); 710 data &= ~PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK; 711 data &= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK; 712 data |= PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK; 713 if (def != data) 714 WREG32_PCIE(smnPCIE_LC_CNTL, data); 715 716 def = data = RREG32_PCIE(smnPCIE_LC_CNTL7); 717 data |= PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN_MASK; 718 if (def != data) 719 WREG32_PCIE(smnPCIE_LC_CNTL7, data); 720 721 def = data = RREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK); 722 data |= NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_REG_DIS_LCLK_MASK; 723 if (def != data) 724 WREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK, data); 725 726 def = data = RREG32_PCIE(smnPCIE_LC_CNTL3); 727 data |= PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK; 728 if (def != data) 729 WREG32_PCIE(smnPCIE_LC_CNTL3, data); 730 731 def = data = RREG32_PCIE(smnRCC_BIF_STRAP3); 732 data &= ~RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK; 733 data &= ~RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK; 734 if (def != data) 735 WREG32_PCIE(smnRCC_BIF_STRAP3, data); 736 737 def = data = RREG32_PCIE(smnRCC_BIF_STRAP5); 738 data &= ~RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK; 739 if (def != data) 740 WREG32_PCIE(smnRCC_BIF_STRAP5, data); 741 742 def = data = RREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2); 743 data &= ~BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK; 744 if (def != data) 745 WREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2, data); 746 747 WREG32_PCIE(smnBIF_CFG_DEV0_EPF0_PCIE_LTR_CAP, 0x10011001); 748 749 def = data = RREG32_PCIE(smnPSWUSP0_PCIE_LC_CNTL2); 750 data |= PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK | 751 PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK; 752 data &= ~PSWUSP0_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK; 753 if (def != data) 754 WREG32_PCIE(smnPSWUSP0_PCIE_LC_CNTL2, data); 755 756 def = data = RREG32_PCIE(smnPCIE_LC_CNTL6); 757 data |= PCIE_LC_CNTL6__LC_L1_POWERDOWN_MASK | 758 PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN_MASK; 759 if (def != data) 760 WREG32_PCIE(smnPCIE_LC_CNTL6, data); 761 762 /* Don't bother about LTR if LTR is not enabled 763 * in the path */ 764 if (adev->pdev->ltr_path) 765 nbio_v7_4_program_ltr(adev); 766 767 def = data = RREG32_PCIE(smnRCC_BIF_STRAP3); 768 data |= 0x5DE0 << RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT; 769 data |= 0x0010 << RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT; 770 if (def != data) 771 WREG32_PCIE(smnRCC_BIF_STRAP3, data); 772 773 def = data = RREG32_PCIE(smnRCC_BIF_STRAP5); 774 data |= 0x0010 << RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT; 775 if (def != data) 776 WREG32_PCIE(smnRCC_BIF_STRAP5, data); 777 778 def = data = RREG32_PCIE(smnPCIE_LC_CNTL); 779 data &= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK; 780 data |= 0x9 << PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT; 781 data |= 0x1 << PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT; 782 if (def != data) 783 WREG32_PCIE(smnPCIE_LC_CNTL, data); 784 785 def = data = RREG32_PCIE(smnPCIE_LC_CNTL3); 786 data &= ~PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK; 787 if (def != data) 788 WREG32_PCIE(smnPCIE_LC_CNTL3, data); 789 #endif 790 } 791 792 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE) 793 794 static void nbio_v7_4_set_reg_remap(struct amdgpu_device *adev) 795 { 796 if (!amdgpu_sriov_vf(adev) && (PAGE_SIZE <= 4096)) { 797 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; 798 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; 799 } else { 800 adev->rmmio_remap.reg_offset = 801 SOC15_REG_OFFSET(NBIO, 0, 802 mmBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL) << 2; 803 adev->rmmio_remap.bus_addr = 0; 804 } 805 } 806 807 const struct amdgpu_nbio_funcs nbio_v7_4_funcs = { 808 .get_hdp_flush_req_offset = nbio_v7_4_get_hdp_flush_req_offset, 809 .get_hdp_flush_done_offset = nbio_v7_4_get_hdp_flush_done_offset, 810 .get_pcie_index_offset = nbio_v7_4_get_pcie_index_offset, 811 .get_pcie_data_offset = nbio_v7_4_get_pcie_data_offset, 812 .get_rev_id = nbio_v7_4_get_rev_id, 813 .mc_access_enable = nbio_v7_4_mc_access_enable, 814 .get_memsize = nbio_v7_4_get_memsize, 815 .sdma_doorbell_range = nbio_v7_4_sdma_doorbell_range, 816 .vcn_doorbell_range = nbio_v7_4_vcn_doorbell_range, 817 .enable_doorbell_aperture = nbio_v7_4_enable_doorbell_aperture, 818 .enable_doorbell_selfring_aperture = nbio_v7_4_enable_doorbell_selfring_aperture, 819 .ih_doorbell_range = nbio_v7_4_ih_doorbell_range, 820 .enable_doorbell_interrupt = nbio_v7_4_enable_doorbell_interrupt, 821 .update_medium_grain_clock_gating = nbio_v7_4_update_medium_grain_clock_gating, 822 .update_medium_grain_light_sleep = nbio_v7_4_update_medium_grain_light_sleep, 823 .get_clockgating_state = nbio_v7_4_get_clockgating_state, 824 .ih_control = nbio_v7_4_ih_control, 825 .init_registers = nbio_v7_4_init_registers, 826 .remap_hdp_registers = nbio_v7_4_remap_hdp_registers, 827 .program_aspm = nbio_v7_4_program_aspm, 828 .set_reg_remap = nbio_v7_4_set_reg_remap, 829 }; 830