1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "amdgpu.h" 24 #include "amdgpu_atombios.h" 25 #include "nbio_v7_4.h" 26 #include "amdgpu_ras.h" 27 28 #include "nbio/nbio_7_4_offset.h" 29 #include "nbio/nbio_7_4_sh_mask.h" 30 #include "nbio/nbio_7_4_0_smn.h" 31 #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h" 32 #include <uapi/linux/kfd_ioctl.h> 33 34 #define smnPCIE_LC_CNTL 0x11140280 35 #define smnPCIE_LC_CNTL3 0x111402d4 36 #define smnPCIE_LC_CNTL6 0x111402ec 37 #define smnPCIE_LC_CNTL7 0x111402f0 38 #define smnNBIF_MGCG_CTRL_LCLK 0x1013a21c 39 #define smnRCC_BIF_STRAP3 0x1012348c 40 #define RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK 0x0000FFFFL 41 #define RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK 0xFFFF0000L 42 #define smnRCC_BIF_STRAP5 0x10123494 43 #define RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK 0x0000FFFFL 44 #define smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2 0x1014008c 45 #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L 46 #define smnBIF_CFG_DEV0_EPF0_PCIE_LTR_CAP 0x10140324 47 #define smnPSWUSP0_PCIE_LC_CNTL2 0x111402c4 48 #define smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL 0x10123538 49 #define smnRCC_BIF_STRAP2 0x10123488 50 #define RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK 0x00004000L 51 #define RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT 0x0 52 #define RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT 0x10 53 #define RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT 0x0 54 55 /* 56 * These are nbio v7_4_1 registers mask. Temporarily define these here since 57 * nbio v7_4_1 header is incomplete. 58 */ 59 #define GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L /* Don't use. Firmware uses this bit internally */ 60 #define GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L 61 #define GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L 62 #define GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L 63 #define GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L 64 #define GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L 65 #define GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L 66 #define GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L 67 #define GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L 68 69 #define mmBIF_MMSCH1_DOORBELL_RANGE 0x01dc 70 #define mmBIF_MMSCH1_DOORBELL_RANGE_BASE_IDX 2 71 //BIF_MMSCH1_DOORBELL_RANGE 72 #define BIF_MMSCH1_DOORBELL_RANGE__OFFSET__SHIFT 0x2 73 #define BIF_MMSCH1_DOORBELL_RANGE__SIZE__SHIFT 0x10 74 #define BIF_MMSCH1_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL 75 #define BIF_MMSCH1_DOORBELL_RANGE__SIZE_MASK 0x001F0000L 76 77 #define BIF_MMSCH1_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL 78 #define BIF_MMSCH1_DOORBELL_RANGE__SIZE_MASK 0x001F0000L 79 80 #define mmBIF_MMSCH1_DOORBELL_RANGE_ALDE 0x01d8 81 #define mmBIF_MMSCH1_DOORBELL_RANGE_ALDE_BASE_IDX 2 82 //BIF_MMSCH1_DOORBELL_ALDE_RANGE 83 #define BIF_MMSCH1_DOORBELL_RANGE_ALDE__OFFSET__SHIFT 0x2 84 #define BIF_MMSCH1_DOORBELL_RANGE_ALDE__SIZE__SHIFT 0x10 85 #define BIF_MMSCH1_DOORBELL_RANGE_ALDE__OFFSET_MASK 0x00000FFCL 86 #define BIF_MMSCH1_DOORBELL_RANGE_ALDE__SIZE_MASK 0x001F0000L 87 88 #define mmRCC_DEV0_EPF0_STRAP0_ALDE 0x0015 89 #define mmRCC_DEV0_EPF0_STRAP0_ALDE_BASE_IDX 2 90 91 #define mmBIF_DOORBELL_INT_CNTL_ALDE 0x00fe 92 #define mmBIF_DOORBELL_INT_CNTL_ALDE_BASE_IDX 2 93 #define BIF_DOORBELL_INT_CNTL_ALDE__DOORBELL_INTERRUPT_DISABLE__SHIFT 0x18 94 #define BIF_DOORBELL_INT_CNTL_ALDE__DOORBELL_INTERRUPT_DISABLE_MASK 0x01000000L 95 96 #define mmBIF_INTR_CNTL_ALDE 0x0101 97 #define mmBIF_INTR_CNTL_ALDE_BASE_IDX 2 98 99 static void nbio_v7_4_query_ras_error_count(struct amdgpu_device *adev, 100 void *ras_error_status); 101 102 static void nbio_v7_4_remap_hdp_registers(struct amdgpu_device *adev) 103 { 104 WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL, 105 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL); 106 WREG32_SOC15(NBIO, 0, mmREMAP_HDP_REG_FLUSH_CNTL, 107 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL); 108 } 109 110 static u32 nbio_v7_4_get_rev_id(struct amdgpu_device *adev) 111 { 112 u32 tmp; 113 114 if (adev->asic_type == CHIP_ALDEBARAN) 115 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0_ALDE); 116 else 117 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0); 118 119 tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK; 120 tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT; 121 122 return tmp; 123 } 124 125 static void nbio_v7_4_mc_access_enable(struct amdgpu_device *adev, bool enable) 126 { 127 if (enable) 128 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 129 BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK); 130 else 131 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0); 132 } 133 134 static u32 nbio_v7_4_get_memsize(struct amdgpu_device *adev) 135 { 136 return RREG32_SOC15(NBIO, 0, mmRCC_CONFIG_MEMSIZE); 137 } 138 139 static void nbio_v7_4_sdma_doorbell_range(struct amdgpu_device *adev, int instance, 140 bool use_doorbell, int doorbell_index, int doorbell_size) 141 { 142 u32 reg, doorbell_range; 143 144 if (instance < 2) { 145 reg = instance + 146 SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE); 147 } else { 148 /* 149 * These registers address of SDMA2~7 is not consecutive 150 * from SDMA0~1. Need plus 4 dwords offset. 151 * 152 * BIF_SDMA0_DOORBELL_RANGE: 0x3bc0 153 * BIF_SDMA1_DOORBELL_RANGE: 0x3bc4 154 * BIF_SDMA2_DOORBELL_RANGE: 0x3bd8 155 + * BIF_SDMA4_DOORBELL_RANGE: 156 + * ARCTURUS: 0x3be0 157 + * ALDEBARAN: 0x3be4 158 */ 159 if (adev->asic_type == CHIP_ALDEBARAN && instance == 4) 160 reg = instance + 0x4 + 0x1 + 161 SOC15_REG_OFFSET(NBIO, 0, 162 mmBIF_SDMA0_DOORBELL_RANGE); 163 else 164 reg = instance + 0x4 + 165 SOC15_REG_OFFSET(NBIO, 0, 166 mmBIF_SDMA0_DOORBELL_RANGE); 167 } 168 169 doorbell_range = RREG32(reg); 170 171 if (use_doorbell) { 172 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index); 173 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, doorbell_size); 174 } else 175 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0); 176 177 WREG32(reg, doorbell_range); 178 } 179 180 static void nbio_v7_4_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell, 181 int doorbell_index, int instance) 182 { 183 u32 reg; 184 u32 doorbell_range; 185 186 if (instance) { 187 if (adev->asic_type == CHIP_ALDEBARAN) 188 reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH1_DOORBELL_RANGE_ALDE); 189 else 190 reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH1_DOORBELL_RANGE); 191 } else 192 reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH0_DOORBELL_RANGE); 193 194 doorbell_range = RREG32(reg); 195 196 if (use_doorbell) { 197 doorbell_range = REG_SET_FIELD(doorbell_range, 198 BIF_MMSCH0_DOORBELL_RANGE, OFFSET, 199 doorbell_index); 200 doorbell_range = REG_SET_FIELD(doorbell_range, 201 BIF_MMSCH0_DOORBELL_RANGE, SIZE, 8); 202 } else 203 doorbell_range = REG_SET_FIELD(doorbell_range, 204 BIF_MMSCH0_DOORBELL_RANGE, SIZE, 0); 205 206 WREG32(reg, doorbell_range); 207 } 208 209 static void nbio_v7_4_enable_doorbell_aperture(struct amdgpu_device *adev, 210 bool enable) 211 { 212 WREG32_FIELD15(NBIO, 0, RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, enable ? 1 : 0); 213 } 214 215 static void nbio_v7_4_enable_doorbell_selfring_aperture(struct amdgpu_device *adev, 216 bool enable) 217 { 218 u32 tmp = 0; 219 220 if (enable) { 221 tmp = REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_EN, 1) | 222 REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_MODE, 1) | 223 REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_SIZE, 0); 224 225 WREG32_SOC15(NBIO, 0, mmDOORBELL_SELFRING_GPA_APER_BASE_LOW, 226 lower_32_bits(adev->doorbell.base)); 227 WREG32_SOC15(NBIO, 0, mmDOORBELL_SELFRING_GPA_APER_BASE_HIGH, 228 upper_32_bits(adev->doorbell.base)); 229 } 230 231 WREG32_SOC15(NBIO, 0, mmDOORBELL_SELFRING_GPA_APER_CNTL, tmp); 232 } 233 234 static void nbio_v7_4_ih_doorbell_range(struct amdgpu_device *adev, 235 bool use_doorbell, int doorbell_index) 236 { 237 u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0 , mmBIF_IH_DOORBELL_RANGE); 238 239 if (use_doorbell) { 240 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index); 241 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 8); 242 } else 243 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 0); 244 245 WREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE, ih_doorbell_range); 246 } 247 248 249 static void nbio_v7_4_update_medium_grain_clock_gating(struct amdgpu_device *adev, 250 bool enable) 251 { 252 //TODO: Add support for v7.4 253 } 254 255 static void nbio_v7_4_update_medium_grain_light_sleep(struct amdgpu_device *adev, 256 bool enable) 257 { 258 uint32_t def, data; 259 260 def = data = RREG32_PCIE(smnPCIE_CNTL2); 261 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) { 262 data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK | 263 PCIE_CNTL2__MST_MEM_LS_EN_MASK | 264 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK); 265 } else { 266 data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK | 267 PCIE_CNTL2__MST_MEM_LS_EN_MASK | 268 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK); 269 } 270 271 if (def != data) 272 WREG32_PCIE(smnPCIE_CNTL2, data); 273 } 274 275 static void nbio_v7_4_get_clockgating_state(struct amdgpu_device *adev, 276 u64 *flags) 277 { 278 int data; 279 280 /* AMD_CG_SUPPORT_BIF_MGCG */ 281 data = RREG32_PCIE(smnCPM_CONTROL); 282 if (data & CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK) 283 *flags |= AMD_CG_SUPPORT_BIF_MGCG; 284 285 /* AMD_CG_SUPPORT_BIF_LS */ 286 data = RREG32_PCIE(smnPCIE_CNTL2); 287 if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK) 288 *flags |= AMD_CG_SUPPORT_BIF_LS; 289 } 290 291 static void nbio_v7_4_ih_control(struct amdgpu_device *adev) 292 { 293 u32 interrupt_cntl; 294 295 /* setup interrupt control */ 296 WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8); 297 interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL); 298 /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi 299 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN 300 */ 301 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0); 302 /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */ 303 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0); 304 WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl); 305 } 306 307 static u32 nbio_v7_4_get_hdp_flush_req_offset(struct amdgpu_device *adev) 308 { 309 return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_REQ); 310 } 311 312 static u32 nbio_v7_4_get_hdp_flush_done_offset(struct amdgpu_device *adev) 313 { 314 return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_DONE); 315 } 316 317 static u32 nbio_v7_4_get_pcie_index_offset(struct amdgpu_device *adev) 318 { 319 return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2); 320 } 321 322 static u32 nbio_v7_4_get_pcie_data_offset(struct amdgpu_device *adev) 323 { 324 return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2); 325 } 326 327 const struct nbio_hdp_flush_reg nbio_v7_4_hdp_flush_reg = { 328 .ref_and_mask_cp0 = GPU_HDP_FLUSH_DONE__CP0_MASK, 329 .ref_and_mask_cp1 = GPU_HDP_FLUSH_DONE__CP1_MASK, 330 .ref_and_mask_cp2 = GPU_HDP_FLUSH_DONE__CP2_MASK, 331 .ref_and_mask_cp3 = GPU_HDP_FLUSH_DONE__CP3_MASK, 332 .ref_and_mask_cp4 = GPU_HDP_FLUSH_DONE__CP4_MASK, 333 .ref_and_mask_cp5 = GPU_HDP_FLUSH_DONE__CP5_MASK, 334 .ref_and_mask_cp6 = GPU_HDP_FLUSH_DONE__CP6_MASK, 335 .ref_and_mask_cp7 = GPU_HDP_FLUSH_DONE__CP7_MASK, 336 .ref_and_mask_cp8 = GPU_HDP_FLUSH_DONE__CP8_MASK, 337 .ref_and_mask_cp9 = GPU_HDP_FLUSH_DONE__CP9_MASK, 338 .ref_and_mask_sdma0 = GPU_HDP_FLUSH_DONE__SDMA0_MASK, 339 .ref_and_mask_sdma1 = GPU_HDP_FLUSH_DONE__SDMA1_MASK, 340 }; 341 342 static void nbio_v7_4_init_registers(struct amdgpu_device *adev) 343 { 344 uint32_t baco_cntl; 345 346 if (amdgpu_sriov_vf(adev)) 347 adev->rmmio_remap.reg_offset = SOC15_REG_OFFSET(NBIO, 0, 348 mmBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL) << 2; 349 350 if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 4, 4) && 351 !amdgpu_sriov_vf(adev)) { 352 baco_cntl = RREG32_SOC15(NBIO, 0, mmBACO_CNTL); 353 if (baco_cntl & 354 (BACO_CNTL__BACO_DUMMY_EN_MASK | BACO_CNTL__BACO_EN_MASK)) { 355 baco_cntl &= ~(BACO_CNTL__BACO_DUMMY_EN_MASK | 356 BACO_CNTL__BACO_EN_MASK); 357 dev_dbg(adev->dev, "Unsetting baco dummy mode %x", 358 baco_cntl); 359 WREG32_SOC15(NBIO, 0, mmBACO_CNTL, baco_cntl); 360 } 361 } 362 } 363 364 static void nbio_v7_4_handle_ras_controller_intr_no_bifring(struct amdgpu_device *adev) 365 { 366 uint32_t bif_doorbell_intr_cntl; 367 struct ras_manager *obj = amdgpu_ras_find_obj(adev, adev->nbio.ras_if); 368 struct ras_err_data err_data; 369 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 370 371 if (amdgpu_ras_error_data_init(&err_data)) 372 return; 373 374 if (adev->asic_type == CHIP_ALDEBARAN) 375 bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL_ALDE); 376 else 377 bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL); 378 379 if (REG_GET_FIELD(bif_doorbell_intr_cntl, 380 BIF_DOORBELL_INT_CNTL, RAS_CNTLR_INTERRUPT_STATUS)) { 381 /* driver has to clear the interrupt status when bif ring is disabled */ 382 bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl, 383 BIF_DOORBELL_INT_CNTL, 384 RAS_CNTLR_INTERRUPT_CLEAR, 1); 385 if (adev->asic_type == CHIP_ALDEBARAN) 386 WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL_ALDE, bif_doorbell_intr_cntl); 387 else 388 WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl); 389 390 if (!ras->disable_ras_err_cnt_harvest) { 391 /* 392 * clear error status after ras_controller_intr 393 * according to hw team and count ue number 394 * for query 395 */ 396 nbio_v7_4_query_ras_error_count(adev, &err_data); 397 398 /* logging on error cnt and printing for awareness */ 399 obj->err_data.ue_count += err_data.ue_count; 400 obj->err_data.ce_count += err_data.ce_count; 401 402 if (err_data.ce_count) 403 dev_info(adev->dev, "%ld correctable hardware " 404 "errors detected in %s block, " 405 "no user action is needed.\n", 406 obj->err_data.ce_count, 407 get_ras_block_str(adev->nbio.ras_if)); 408 409 if (err_data.ue_count) 410 dev_info(adev->dev, "%ld uncorrectable hardware " 411 "errors detected in %s block\n", 412 obj->err_data.ue_count, 413 get_ras_block_str(adev->nbio.ras_if)); 414 } 415 416 dev_info(adev->dev, "RAS controller interrupt triggered " 417 "by NBIF error\n"); 418 419 /* ras_controller_int is dedicated for nbif ras error, 420 * not the global interrupt for sync flood 421 */ 422 amdgpu_ras_reset_gpu(adev); 423 } 424 425 amdgpu_ras_error_data_fini(&err_data); 426 } 427 428 static void nbio_v7_4_handle_ras_err_event_athub_intr_no_bifring(struct amdgpu_device *adev) 429 { 430 uint32_t bif_doorbell_intr_cntl; 431 432 if (adev->asic_type == CHIP_ALDEBARAN) 433 bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL_ALDE); 434 else 435 bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL); 436 437 if (REG_GET_FIELD(bif_doorbell_intr_cntl, 438 BIF_DOORBELL_INT_CNTL, RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS)) { 439 /* driver has to clear the interrupt status when bif ring is disabled */ 440 bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl, 441 BIF_DOORBELL_INT_CNTL, 442 RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR, 1); 443 444 if (adev->asic_type == CHIP_ALDEBARAN) 445 WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL_ALDE, bif_doorbell_intr_cntl); 446 else 447 WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl); 448 449 amdgpu_ras_global_ras_isr(adev); 450 } 451 } 452 453 454 static int nbio_v7_4_set_ras_controller_irq_state(struct amdgpu_device *adev, 455 struct amdgpu_irq_src *src, 456 unsigned type, 457 enum amdgpu_interrupt_state state) 458 { 459 /* The ras_controller_irq enablement should be done in psp bl when it 460 * tries to enable ras feature. Driver only need to set the correct interrupt 461 * vector for bare-metal and sriov use case respectively 462 */ 463 uint32_t bif_intr_cntl; 464 465 if (adev->asic_type == CHIP_ALDEBARAN) 466 bif_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL_ALDE); 467 else 468 bif_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL); 469 470 if (state == AMDGPU_IRQ_STATE_ENABLE) { 471 /* set interrupt vector select bit to 0 to select 472 * vetcor 1 for bare metal case */ 473 bif_intr_cntl = REG_SET_FIELD(bif_intr_cntl, 474 BIF_INTR_CNTL, 475 RAS_INTR_VEC_SEL, 0); 476 477 if (adev->asic_type == CHIP_ALDEBARAN) 478 WREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL_ALDE, bif_intr_cntl); 479 else 480 WREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL, bif_intr_cntl); 481 482 } 483 484 return 0; 485 } 486 487 static int nbio_v7_4_process_ras_controller_irq(struct amdgpu_device *adev, 488 struct amdgpu_irq_src *source, 489 struct amdgpu_iv_entry *entry) 490 { 491 /* By design, the ih cookie for ras_controller_irq should be written 492 * to BIFring instead of general iv ring. However, due to known bif ring 493 * hw bug, it has to be disabled. There is no chance the process function 494 * will be involked. Just left it as a dummy one. 495 */ 496 return 0; 497 } 498 499 static int nbio_v7_4_set_ras_err_event_athub_irq_state(struct amdgpu_device *adev, 500 struct amdgpu_irq_src *src, 501 unsigned type, 502 enum amdgpu_interrupt_state state) 503 { 504 /* The ras_controller_irq enablement should be done in psp bl when it 505 * tries to enable ras feature. Driver only need to set the correct interrupt 506 * vector for bare-metal and sriov use case respectively 507 */ 508 uint32_t bif_intr_cntl; 509 510 if (adev->asic_type == CHIP_ALDEBARAN) 511 bif_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL_ALDE); 512 else 513 bif_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL); 514 515 if (state == AMDGPU_IRQ_STATE_ENABLE) { 516 /* set interrupt vector select bit to 0 to select 517 * vetcor 1 for bare metal case */ 518 bif_intr_cntl = REG_SET_FIELD(bif_intr_cntl, 519 BIF_INTR_CNTL, 520 RAS_INTR_VEC_SEL, 0); 521 522 if (adev->asic_type == CHIP_ALDEBARAN) 523 WREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL_ALDE, bif_intr_cntl); 524 else 525 WREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL, bif_intr_cntl); 526 } 527 528 return 0; 529 } 530 531 static int nbio_v7_4_process_err_event_athub_irq(struct amdgpu_device *adev, 532 struct amdgpu_irq_src *source, 533 struct amdgpu_iv_entry *entry) 534 { 535 /* By design, the ih cookie for err_event_athub_irq should be written 536 * to BIFring instead of general iv ring. However, due to known bif ring 537 * hw bug, it has to be disabled. There is no chance the process function 538 * will be involked. Just left it as a dummy one. 539 */ 540 return 0; 541 } 542 543 static const struct amdgpu_irq_src_funcs nbio_v7_4_ras_controller_irq_funcs = { 544 .set = nbio_v7_4_set_ras_controller_irq_state, 545 .process = nbio_v7_4_process_ras_controller_irq, 546 }; 547 548 static const struct amdgpu_irq_src_funcs nbio_v7_4_ras_err_event_athub_irq_funcs = { 549 .set = nbio_v7_4_set_ras_err_event_athub_irq_state, 550 .process = nbio_v7_4_process_err_event_athub_irq, 551 }; 552 553 static int nbio_v7_4_init_ras_controller_interrupt (struct amdgpu_device *adev) 554 { 555 int r; 556 557 /* init the irq funcs */ 558 adev->nbio.ras_controller_irq.funcs = 559 &nbio_v7_4_ras_controller_irq_funcs; 560 adev->nbio.ras_controller_irq.num_types = 1; 561 562 /* register ras controller interrupt */ 563 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF, 564 NBIF_7_4__SRCID__RAS_CONTROLLER_INTERRUPT, 565 &adev->nbio.ras_controller_irq); 566 567 return r; 568 } 569 570 static int nbio_v7_4_init_ras_err_event_athub_interrupt (struct amdgpu_device *adev) 571 { 572 573 int r; 574 575 /* init the irq funcs */ 576 adev->nbio.ras_err_event_athub_irq.funcs = 577 &nbio_v7_4_ras_err_event_athub_irq_funcs; 578 adev->nbio.ras_err_event_athub_irq.num_types = 1; 579 580 /* register ras err event athub interrupt */ 581 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF, 582 NBIF_7_4__SRCID__ERREVENT_ATHUB_INTERRUPT, 583 &adev->nbio.ras_err_event_athub_irq); 584 585 return r; 586 } 587 588 #define smnPARITY_ERROR_STATUS_UNCORR_GRP2 0x13a20030 589 #define smnPARITY_ERROR_STATUS_UNCORR_GRP2_ALDE 0x13b20030 590 #define smnRAS_GLOBAL_STATUS_LO_ALDE 0x13b20020 591 592 static void nbio_v7_4_query_ras_error_count(struct amdgpu_device *adev, 593 void *ras_error_status) 594 { 595 uint32_t global_sts, central_sts, int_eoi, parity_sts; 596 uint32_t corr, fatal, non_fatal; 597 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 598 599 if (adev->asic_type == CHIP_ALDEBARAN) 600 global_sts = RREG32_PCIE(smnRAS_GLOBAL_STATUS_LO_ALDE); 601 else 602 global_sts = RREG32_PCIE(smnRAS_GLOBAL_STATUS_LO); 603 604 corr = REG_GET_FIELD(global_sts, RAS_GLOBAL_STATUS_LO, ParityErrCorr); 605 fatal = REG_GET_FIELD(global_sts, RAS_GLOBAL_STATUS_LO, ParityErrFatal); 606 non_fatal = REG_GET_FIELD(global_sts, RAS_GLOBAL_STATUS_LO, 607 ParityErrNonFatal); 608 609 if (adev->asic_type == CHIP_ALDEBARAN) 610 parity_sts = RREG32_PCIE(smnPARITY_ERROR_STATUS_UNCORR_GRP2_ALDE); 611 else 612 parity_sts = RREG32_PCIE(smnPARITY_ERROR_STATUS_UNCORR_GRP2); 613 614 if (corr) 615 err_data->ce_count++; 616 if (fatal) 617 err_data->ue_count++; 618 619 if (corr || fatal || non_fatal) { 620 central_sts = RREG32_PCIE(smnBIFL_RAS_CENTRAL_STATUS); 621 622 /* clear error status register */ 623 if (adev->asic_type == CHIP_ALDEBARAN) 624 WREG32_PCIE(smnRAS_GLOBAL_STATUS_LO_ALDE, global_sts); 625 else 626 WREG32_PCIE(smnRAS_GLOBAL_STATUS_LO, global_sts); 627 628 if (fatal) 629 { 630 /* clear parity fatal error indication field */ 631 if (adev->asic_type == CHIP_ALDEBARAN) 632 WREG32_PCIE(smnPARITY_ERROR_STATUS_UNCORR_GRP2_ALDE, parity_sts); 633 else 634 WREG32_PCIE(smnPARITY_ERROR_STATUS_UNCORR_GRP2, parity_sts); 635 } 636 637 if (REG_GET_FIELD(central_sts, BIFL_RAS_CENTRAL_STATUS, 638 BIFL_RasContller_Intr_Recv)) { 639 /* clear interrupt status register */ 640 WREG32_PCIE(smnBIFL_RAS_CENTRAL_STATUS, central_sts); 641 int_eoi = RREG32_PCIE(smnIOHC_INTERRUPT_EOI); 642 int_eoi = REG_SET_FIELD(int_eoi, 643 IOHC_INTERRUPT_EOI, SMI_EOI, 1); 644 WREG32_PCIE(smnIOHC_INTERRUPT_EOI, int_eoi); 645 } 646 } 647 } 648 649 static void nbio_v7_4_enable_doorbell_interrupt(struct amdgpu_device *adev, 650 bool enable) 651 { 652 if (adev->asic_type == CHIP_ALDEBARAN) 653 WREG32_FIELD15(NBIO, 0, BIF_DOORBELL_INT_CNTL_ALDE, 654 DOORBELL_INTERRUPT_DISABLE, enable ? 0 : 1); 655 else 656 WREG32_FIELD15(NBIO, 0, BIF_DOORBELL_INT_CNTL, 657 DOORBELL_INTERRUPT_DISABLE, enable ? 0 : 1); 658 } 659 660 const struct amdgpu_ras_block_hw_ops nbio_v7_4_ras_hw_ops = { 661 .query_ras_error_count = nbio_v7_4_query_ras_error_count, 662 }; 663 664 struct amdgpu_nbio_ras nbio_v7_4_ras = { 665 .ras_block = { 666 .ras_comm = { 667 .name = "pcie_bif", 668 .block = AMDGPU_RAS_BLOCK__PCIE_BIF, 669 .type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 670 }, 671 .hw_ops = &nbio_v7_4_ras_hw_ops, 672 .ras_late_init = amdgpu_nbio_ras_late_init, 673 }, 674 .handle_ras_controller_intr_no_bifring = nbio_v7_4_handle_ras_controller_intr_no_bifring, 675 .handle_ras_err_event_athub_intr_no_bifring = nbio_v7_4_handle_ras_err_event_athub_intr_no_bifring, 676 .init_ras_controller_interrupt = nbio_v7_4_init_ras_controller_interrupt, 677 .init_ras_err_event_athub_interrupt = nbio_v7_4_init_ras_err_event_athub_interrupt, 678 }; 679 680 681 #ifdef CONFIG_PCIEASPM 682 static void nbio_v7_4_program_ltr(struct amdgpu_device *adev) 683 { 684 uint32_t def, data; 685 686 WREG32_PCIE(smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL, 0x75EB); 687 688 def = data = RREG32_PCIE(smnRCC_BIF_STRAP2); 689 data &= ~RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK; 690 if (def != data) 691 WREG32_PCIE(smnRCC_BIF_STRAP2, data); 692 693 def = data = RREG32_PCIE(smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL); 694 data &= ~EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK; 695 if (def != data) 696 WREG32_PCIE(smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL, data); 697 698 def = data = RREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2); 699 data |= BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK; 700 if (def != data) 701 WREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2, data); 702 } 703 #endif 704 705 static void nbio_v7_4_program_aspm(struct amdgpu_device *adev) 706 { 707 #ifdef CONFIG_PCIEASPM 708 uint32_t def, data; 709 710 if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 4, 4)) 711 return; 712 713 def = data = RREG32_PCIE(smnPCIE_LC_CNTL); 714 data &= ~PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK; 715 data &= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK; 716 data |= PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK; 717 if (def != data) 718 WREG32_PCIE(smnPCIE_LC_CNTL, data); 719 720 def = data = RREG32_PCIE(smnPCIE_LC_CNTL7); 721 data |= PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN_MASK; 722 if (def != data) 723 WREG32_PCIE(smnPCIE_LC_CNTL7, data); 724 725 def = data = RREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK); 726 data |= NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_REG_DIS_LCLK_MASK; 727 if (def != data) 728 WREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK, data); 729 730 def = data = RREG32_PCIE(smnPCIE_LC_CNTL3); 731 data |= PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK; 732 if (def != data) 733 WREG32_PCIE(smnPCIE_LC_CNTL3, data); 734 735 def = data = RREG32_PCIE(smnRCC_BIF_STRAP3); 736 data &= ~RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK; 737 data &= ~RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK; 738 if (def != data) 739 WREG32_PCIE(smnRCC_BIF_STRAP3, data); 740 741 def = data = RREG32_PCIE(smnRCC_BIF_STRAP5); 742 data &= ~RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK; 743 if (def != data) 744 WREG32_PCIE(smnRCC_BIF_STRAP5, data); 745 746 def = data = RREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2); 747 data &= ~BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK; 748 if (def != data) 749 WREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2, data); 750 751 WREG32_PCIE(smnBIF_CFG_DEV0_EPF0_PCIE_LTR_CAP, 0x10011001); 752 753 def = data = RREG32_PCIE(smnPSWUSP0_PCIE_LC_CNTL2); 754 data |= PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK | 755 PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK; 756 data &= ~PSWUSP0_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK; 757 if (def != data) 758 WREG32_PCIE(smnPSWUSP0_PCIE_LC_CNTL2, data); 759 760 def = data = RREG32_PCIE(smnPCIE_LC_CNTL6); 761 data |= PCIE_LC_CNTL6__LC_L1_POWERDOWN_MASK | 762 PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN_MASK; 763 if (def != data) 764 WREG32_PCIE(smnPCIE_LC_CNTL6, data); 765 766 /* Don't bother about LTR if LTR is not enabled 767 * in the path */ 768 if (adev->pdev->ltr_path) 769 nbio_v7_4_program_ltr(adev); 770 771 def = data = RREG32_PCIE(smnRCC_BIF_STRAP3); 772 data |= 0x5DE0 << RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT; 773 data |= 0x0010 << RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT; 774 if (def != data) 775 WREG32_PCIE(smnRCC_BIF_STRAP3, data); 776 777 def = data = RREG32_PCIE(smnRCC_BIF_STRAP5); 778 data |= 0x0010 << RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT; 779 if (def != data) 780 WREG32_PCIE(smnRCC_BIF_STRAP5, data); 781 782 def = data = RREG32_PCIE(smnPCIE_LC_CNTL); 783 data &= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK; 784 data |= 0x9 << PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT; 785 data |= 0x1 << PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT; 786 if (def != data) 787 WREG32_PCIE(smnPCIE_LC_CNTL, data); 788 789 def = data = RREG32_PCIE(smnPCIE_LC_CNTL3); 790 data &= ~PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK; 791 if (def != data) 792 WREG32_PCIE(smnPCIE_LC_CNTL3, data); 793 #endif 794 } 795 796 const struct amdgpu_nbio_funcs nbio_v7_4_funcs = { 797 .get_hdp_flush_req_offset = nbio_v7_4_get_hdp_flush_req_offset, 798 .get_hdp_flush_done_offset = nbio_v7_4_get_hdp_flush_done_offset, 799 .get_pcie_index_offset = nbio_v7_4_get_pcie_index_offset, 800 .get_pcie_data_offset = nbio_v7_4_get_pcie_data_offset, 801 .get_rev_id = nbio_v7_4_get_rev_id, 802 .mc_access_enable = nbio_v7_4_mc_access_enable, 803 .get_memsize = nbio_v7_4_get_memsize, 804 .sdma_doorbell_range = nbio_v7_4_sdma_doorbell_range, 805 .vcn_doorbell_range = nbio_v7_4_vcn_doorbell_range, 806 .enable_doorbell_aperture = nbio_v7_4_enable_doorbell_aperture, 807 .enable_doorbell_selfring_aperture = nbio_v7_4_enable_doorbell_selfring_aperture, 808 .ih_doorbell_range = nbio_v7_4_ih_doorbell_range, 809 .enable_doorbell_interrupt = nbio_v7_4_enable_doorbell_interrupt, 810 .update_medium_grain_clock_gating = nbio_v7_4_update_medium_grain_clock_gating, 811 .update_medium_grain_light_sleep = nbio_v7_4_update_medium_grain_light_sleep, 812 .get_clockgating_state = nbio_v7_4_get_clockgating_state, 813 .ih_control = nbio_v7_4_ih_control, 814 .init_registers = nbio_v7_4_init_registers, 815 .remap_hdp_registers = nbio_v7_4_remap_hdp_registers, 816 .program_aspm = nbio_v7_4_program_aspm, 817 }; 818