1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "amdgpu.h" 24 #include "amdgpu_atombios.h" 25 #include "nbio_v7_11.h" 26 27 #include "nbio/nbio_7_11_0_offset.h" 28 #include "nbio/nbio_7_11_0_sh_mask.h" 29 #include <uapi/linux/kfd_ioctl.h> 30 31 static u32 nbio_v7_11_get_rev_id(struct amdgpu_device *adev) 32 { 33 u32 tmp; 34 printk("%s, getid\n",__func__); 35 36 tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP1_RCC_DEV0_EPF0_STRAP0); 37 38 tmp &= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK; 39 tmp >>= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT; 40 41 return tmp; 42 } 43 44 static void nbio_v7_11_mc_access_enable(struct amdgpu_device *adev, bool enable) 45 { 46 if (enable) 47 WREG32_SOC15(NBIO, 0, regBIF_BX1_BIF_FB_EN, 48 BIF_BX1_BIF_FB_EN__FB_READ_EN_MASK | 49 BIF_BX1_BIF_FB_EN__FB_WRITE_EN_MASK); 50 else 51 WREG32_SOC15(NBIO, 0, regBIF_BX1_BIF_FB_EN, 0); 52 } 53 54 static u32 nbio_v7_11_get_memsize(struct amdgpu_device *adev) 55 { 56 return RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_CONFIG_MEMSIZE); 57 } 58 59 static void nbio_v7_11_sdma_doorbell_range(struct amdgpu_device *adev, int instance, 60 bool use_doorbell, int doorbell_index, 61 int doorbell_size) 62 { 63 u32 reg = SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_SDMA0_DOORBELL_RANGE); 64 u32 doorbell_range = RREG32_PCIE_PORT(reg); 65 66 if (use_doorbell) { 67 doorbell_range = REG_SET_FIELD(doorbell_range, 68 GDC0_BIF_SDMA0_DOORBELL_RANGE, 69 OFFSET, doorbell_index); 70 doorbell_range = REG_SET_FIELD(doorbell_range, 71 GDC0_BIF_SDMA0_DOORBELL_RANGE, 72 SIZE, doorbell_size); 73 } else { 74 doorbell_range = REG_SET_FIELD(doorbell_range, 75 GDC0_BIF_SDMA0_DOORBELL_RANGE, 76 SIZE, 0); 77 } 78 79 WREG32_PCIE_PORT(reg, doorbell_range); 80 } 81 82 static void nbio_v7_11_enable_doorbell_aperture(struct amdgpu_device *adev, 83 bool enable) 84 { 85 u32 reg; 86 87 88 reg = RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN); 89 reg = REG_SET_FIELD(reg, RCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN, 90 BIF_DOORBELL_APER_EN, enable ? 1 : 0); 91 92 WREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN, reg); 93 } 94 95 static void nbio_v7_11_enable_doorbell_selfring_aperture(struct amdgpu_device *adev, 96 bool enable) 97 { 98 /* u32 tmp = 0; 99 100 if (enable) { 101 tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, 102 DOORBELL_SELFRING_GPA_APER_EN, 1) | 103 REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, 104 DOORBELL_SELFRING_GPA_APER_MODE, 1) | 105 REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, 106 DOORBELL_SELFRING_GPA_APER_SIZE, 0); 107 108 WREG32_SOC15(NBIO, 0, 109 regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW, 110 lower_32_bits(adev->doorbell.base)); 111 WREG32_SOC15(NBIO, 0, 112 regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH, 113 upper_32_bits(adev->doorbell.base)); 114 } 115 116 WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, 117 tmp); 118 */ 119 } 120 121 122 static void nbio_v7_11_ih_doorbell_range(struct amdgpu_device *adev, 123 bool use_doorbell, int doorbell_index) 124 { 125 u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0,regGDC0_BIF_IH_DOORBELL_RANGE); 126 127 if (use_doorbell) { 128 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 129 GDC0_BIF_IH_DOORBELL_RANGE, OFFSET, 130 doorbell_index); 131 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 132 GDC0_BIF_IH_DOORBELL_RANGE, SIZE, 133 2); 134 } else { 135 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 136 GDC0_BIF_IH_DOORBELL_RANGE, SIZE, 137 0); 138 } 139 140 WREG32_SOC15(NBIO, 0, regGDC0_BIF_IH_DOORBELL_RANGE, 141 ih_doorbell_range); 142 } 143 144 static void nbio_v7_11_ih_control(struct amdgpu_device *adev) 145 { 146 u32 interrupt_cntl; 147 148 /* setup interrupt control */ 149 WREG32_SOC15(NBIO, 0, regBIF_BX1_INTERRUPT_CNTL2, 150 adev->dummy_page_addr >> 8); 151 152 interrupt_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX1_INTERRUPT_CNTL); 153 /* 154 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi 155 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN 156 */ 157 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX1_INTERRUPT_CNTL, 158 IH_DUMMY_RD_OVERRIDE, 0); 159 160 /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */ 161 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX1_INTERRUPT_CNTL, 162 IH_REQ_NONSNOOP_EN, 0); 163 164 WREG32_SOC15(NBIO, 0, regBIF_BX1_INTERRUPT_CNTL, interrupt_cntl); 165 } 166 167 static u32 nbio_v7_11_get_hdp_flush_req_offset(struct amdgpu_device *adev) 168 { 169 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_REQ); 170 } 171 172 static u32 nbio_v7_11_get_hdp_flush_done_offset(struct amdgpu_device *adev) 173 { 174 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_DONE); 175 } 176 177 static u32 nbio_v7_11_get_pcie_index_offset(struct amdgpu_device *adev) 178 { 179 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX1_PCIE_INDEX2); 180 } 181 182 static u32 nbio_v7_11_get_pcie_data_offset(struct amdgpu_device *adev) 183 { 184 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX1_PCIE_DATA2); 185 } 186 187 static u32 nbio_v7_11_get_pcie_port_index_offset(struct amdgpu_device *adev) 188 { 189 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_INDEX); 190 } 191 192 static u32 nbio_v7_11_get_pcie_port_data_offset(struct amdgpu_device *adev) 193 { 194 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_DATA); 195 } 196 197 const struct nbio_hdp_flush_reg nbio_v7_11_hdp_flush_reg = { 198 .ref_and_mask_cp0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK, 199 .ref_and_mask_cp1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1_MASK, 200 .ref_and_mask_cp2 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2_MASK, 201 .ref_and_mask_cp3 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3_MASK, 202 .ref_and_mask_cp4 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4_MASK, 203 .ref_and_mask_cp5 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5_MASK, 204 .ref_and_mask_cp6 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6_MASK, 205 .ref_and_mask_cp7 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7_MASK, 206 .ref_and_mask_cp8 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8_MASK, 207 .ref_and_mask_cp9 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9_MASK, 208 .ref_and_mask_sdma0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK, 209 .ref_and_mask_sdma1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK, 210 }; 211 212 static void nbio_v7_11_init_registers(struct amdgpu_device *adev) 213 { 214 /* uint32_t def, data; 215 216 def = data = RREG32_SOC15(NBIO, 0, regBIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3); 217 data = REG_SET_FIELD(data, BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3, 218 CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1); 219 data = REG_SET_FIELD(data, BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3, 220 CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1); 221 222 if (def != data) 223 WREG32_SOC15(NBIO, 0, regBIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3, data); 224 */ 225 } 226 227 const struct amdgpu_nbio_funcs nbio_v7_11_funcs = { 228 .get_hdp_flush_req_offset = nbio_v7_11_get_hdp_flush_req_offset, 229 .get_hdp_flush_done_offset = nbio_v7_11_get_hdp_flush_done_offset, 230 .get_pcie_index_offset = nbio_v7_11_get_pcie_index_offset, 231 .get_pcie_data_offset = nbio_v7_11_get_pcie_data_offset, 232 .get_pcie_port_index_offset = nbio_v7_11_get_pcie_port_index_offset, 233 .get_pcie_port_data_offset = nbio_v7_11_get_pcie_port_data_offset, 234 .get_rev_id = nbio_v7_11_get_rev_id, 235 .mc_access_enable = nbio_v7_11_mc_access_enable, 236 .get_memsize = nbio_v7_11_get_memsize, 237 .sdma_doorbell_range = nbio_v7_11_sdma_doorbell_range, 238 .enable_doorbell_aperture = nbio_v7_11_enable_doorbell_aperture, 239 .enable_doorbell_selfring_aperture = nbio_v7_11_enable_doorbell_selfring_aperture, 240 .ih_doorbell_range = nbio_v7_11_ih_doorbell_range, 241 .ih_control = nbio_v7_11_ih_control, 242 .init_registers = nbio_v7_11_init_registers, 243 }; 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