1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "amdgpu.h" 24 #include "amdgpu_atombios.h" 25 #include "nbio_v7_11.h" 26 27 #include "nbio/nbio_7_11_0_offset.h" 28 #include "nbio/nbio_7_11_0_sh_mask.h" 29 #include <uapi/linux/kfd_ioctl.h> 30 31 static void nbio_v7_11_remap_hdp_registers(struct amdgpu_device *adev) 32 { 33 WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL, 34 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL); 35 WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL, 36 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL); 37 } 38 39 static u32 nbio_v7_11_get_rev_id(struct amdgpu_device *adev) 40 { 41 u32 tmp; 42 43 tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP1_RCC_DEV0_EPF0_STRAP0); 44 tmp &= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK; 45 tmp >>= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT; 46 47 return tmp; 48 } 49 50 static void nbio_v7_11_mc_access_enable(struct amdgpu_device *adev, bool enable) 51 { 52 if (enable) 53 WREG32_SOC15(NBIO, 0, regBIF_BX1_BIF_FB_EN, 54 BIF_BX1_BIF_FB_EN__FB_READ_EN_MASK | 55 BIF_BX1_BIF_FB_EN__FB_WRITE_EN_MASK); 56 else 57 WREG32_SOC15(NBIO, 0, regBIF_BX1_BIF_FB_EN, 0); 58 } 59 60 static u32 nbio_v7_11_get_memsize(struct amdgpu_device *adev) 61 { 62 return RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_CONFIG_MEMSIZE); 63 } 64 65 static void nbio_v7_11_sdma_doorbell_range(struct amdgpu_device *adev, int instance, 66 bool use_doorbell, int doorbell_index, 67 int doorbell_size) 68 { 69 u32 reg = SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_SDMA0_DOORBELL_RANGE); 70 u32 doorbell_range = RREG32_PCIE_PORT(reg); 71 72 if (use_doorbell) { 73 doorbell_range = REG_SET_FIELD(doorbell_range, 74 GDC0_BIF_SDMA0_DOORBELL_RANGE, 75 OFFSET, doorbell_index); 76 doorbell_range = REG_SET_FIELD(doorbell_range, 77 GDC0_BIF_SDMA0_DOORBELL_RANGE, 78 SIZE, doorbell_size); 79 } else { 80 doorbell_range = REG_SET_FIELD(doorbell_range, 81 GDC0_BIF_SDMA0_DOORBELL_RANGE, 82 SIZE, 0); 83 } 84 85 WREG32_PCIE_PORT(reg, doorbell_range); 86 } 87 88 static void nbio_v7_11_vpe_doorbell_range(struct amdgpu_device *adev, int instance, 89 bool use_doorbell, int doorbell_index, 90 int doorbell_size) 91 { 92 u32 reg = SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_VPE_DOORBELL_RANGE); 93 u32 doorbell_range = RREG32_PCIE_PORT(reg); 94 95 if (use_doorbell) { 96 doorbell_range = REG_SET_FIELD(doorbell_range, 97 GDC0_BIF_VPE_DOORBELL_RANGE, 98 OFFSET, doorbell_index); 99 doorbell_range = REG_SET_FIELD(doorbell_range, 100 GDC0_BIF_VPE_DOORBELL_RANGE, 101 SIZE, doorbell_size); 102 } else { 103 doorbell_range = REG_SET_FIELD(doorbell_range, 104 GDC0_BIF_VPE_DOORBELL_RANGE, 105 SIZE, 0); 106 } 107 108 WREG32_PCIE_PORT(reg, doorbell_range); 109 } 110 111 static void nbio_v7_11_vcn_doorbell_range(struct amdgpu_device *adev, 112 bool use_doorbell, 113 int doorbell_index, int instance) 114 { 115 u32 reg = SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_VCN0_DOORBELL_RANGE); 116 u32 doorbell_range = RREG32_PCIE_PORT(reg); 117 118 if (use_doorbell) { 119 doorbell_range = REG_SET_FIELD(doorbell_range, 120 GDC0_BIF_VCN0_DOORBELL_RANGE, OFFSET, 121 doorbell_index); 122 doorbell_range = REG_SET_FIELD(doorbell_range, 123 GDC0_BIF_VCN0_DOORBELL_RANGE, SIZE, 8); 124 } else { 125 doorbell_range = REG_SET_FIELD(doorbell_range, 126 GDC0_BIF_VCN0_DOORBELL_RANGE, SIZE, 0); 127 } 128 129 WREG32_PCIE_PORT(reg, doorbell_range); 130 } 131 132 static void nbio_v7_11_enable_doorbell_aperture(struct amdgpu_device *adev, 133 bool enable) 134 { 135 u32 reg; 136 137 138 reg = RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN); 139 reg = REG_SET_FIELD(reg, RCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN, 140 BIF_DOORBELL_APER_EN, enable ? 1 : 0); 141 142 WREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN, reg); 143 } 144 145 static void nbio_v7_11_enable_doorbell_selfring_aperture(struct amdgpu_device *adev, 146 bool enable) 147 { 148 /* u32 tmp = 0; 149 150 if (enable) { 151 tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, 152 DOORBELL_SELFRING_GPA_APER_EN, 1) | 153 REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, 154 DOORBELL_SELFRING_GPA_APER_MODE, 1) | 155 REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, 156 DOORBELL_SELFRING_GPA_APER_SIZE, 0); 157 158 WREG32_SOC15(NBIO, 0, 159 regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW, 160 lower_32_bits(adev->doorbell.base)); 161 WREG32_SOC15(NBIO, 0, 162 regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH, 163 upper_32_bits(adev->doorbell.base)); 164 } 165 166 WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, 167 tmp); 168 */ 169 } 170 171 172 static void nbio_v7_11_ih_doorbell_range(struct amdgpu_device *adev, 173 bool use_doorbell, int doorbell_index) 174 { 175 u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0,regGDC0_BIF_IH_DOORBELL_RANGE); 176 177 if (use_doorbell) { 178 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 179 GDC0_BIF_IH_DOORBELL_RANGE, OFFSET, 180 doorbell_index); 181 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 182 GDC0_BIF_IH_DOORBELL_RANGE, SIZE, 183 2); 184 } else { 185 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 186 GDC0_BIF_IH_DOORBELL_RANGE, SIZE, 187 0); 188 } 189 190 WREG32_SOC15(NBIO, 0, regGDC0_BIF_IH_DOORBELL_RANGE, 191 ih_doorbell_range); 192 } 193 194 static void nbio_v7_11_ih_control(struct amdgpu_device *adev) 195 { 196 u32 interrupt_cntl; 197 198 /* setup interrupt control */ 199 WREG32_SOC15(NBIO, 0, regBIF_BX1_INTERRUPT_CNTL2, 200 adev->dummy_page_addr >> 8); 201 202 interrupt_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX1_INTERRUPT_CNTL); 203 /* 204 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi 205 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN 206 */ 207 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX1_INTERRUPT_CNTL, 208 IH_DUMMY_RD_OVERRIDE, 0); 209 210 /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */ 211 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX1_INTERRUPT_CNTL, 212 IH_REQ_NONSNOOP_EN, 0); 213 214 WREG32_SOC15(NBIO, 0, regBIF_BX1_INTERRUPT_CNTL, interrupt_cntl); 215 } 216 217 static u32 nbio_v7_11_get_hdp_flush_req_offset(struct amdgpu_device *adev) 218 { 219 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_REQ); 220 } 221 222 static u32 nbio_v7_11_get_hdp_flush_done_offset(struct amdgpu_device *adev) 223 { 224 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_DONE); 225 } 226 227 static u32 nbio_v7_11_get_pcie_index_offset(struct amdgpu_device *adev) 228 { 229 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX1_PCIE_INDEX2); 230 } 231 232 static u32 nbio_v7_11_get_pcie_data_offset(struct amdgpu_device *adev) 233 { 234 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX1_PCIE_DATA2); 235 } 236 237 static u32 nbio_v7_11_get_pcie_port_index_offset(struct amdgpu_device *adev) 238 { 239 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_INDEX); 240 } 241 242 static u32 nbio_v7_11_get_pcie_port_data_offset(struct amdgpu_device *adev) 243 { 244 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_DATA); 245 } 246 247 const struct nbio_hdp_flush_reg nbio_v7_11_hdp_flush_reg = { 248 .ref_and_mask_cp0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK, 249 .ref_and_mask_cp1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1_MASK, 250 .ref_and_mask_cp2 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2_MASK, 251 .ref_and_mask_cp3 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3_MASK, 252 .ref_and_mask_cp4 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4_MASK, 253 .ref_and_mask_cp5 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5_MASK, 254 .ref_and_mask_cp6 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6_MASK, 255 .ref_and_mask_cp7 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7_MASK, 256 .ref_and_mask_cp8 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8_MASK, 257 .ref_and_mask_cp9 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9_MASK, 258 .ref_and_mask_sdma0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK, 259 .ref_and_mask_sdma1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK, 260 }; 261 262 static void nbio_v7_11_init_registers(struct amdgpu_device *adev) 263 { 264 /* uint32_t def, data; 265 266 def = data = RREG32_SOC15(NBIO, 0, regBIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3); 267 data = REG_SET_FIELD(data, BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3, 268 CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1); 269 data = REG_SET_FIELD(data, BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3, 270 CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1); 271 272 if (def != data) 273 WREG32_SOC15(NBIO, 0, regBIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3, data); 274 */ 275 } 276 277 const struct amdgpu_nbio_funcs nbio_v7_11_funcs = { 278 .get_hdp_flush_req_offset = nbio_v7_11_get_hdp_flush_req_offset, 279 .get_hdp_flush_done_offset = nbio_v7_11_get_hdp_flush_done_offset, 280 .get_pcie_index_offset = nbio_v7_11_get_pcie_index_offset, 281 .get_pcie_data_offset = nbio_v7_11_get_pcie_data_offset, 282 .get_pcie_port_index_offset = nbio_v7_11_get_pcie_port_index_offset, 283 .get_pcie_port_data_offset = nbio_v7_11_get_pcie_port_data_offset, 284 .get_rev_id = nbio_v7_11_get_rev_id, 285 .mc_access_enable = nbio_v7_11_mc_access_enable, 286 .get_memsize = nbio_v7_11_get_memsize, 287 .sdma_doorbell_range = nbio_v7_11_sdma_doorbell_range, 288 .vcn_doorbell_range = nbio_v7_11_vcn_doorbell_range, 289 .vpe_doorbell_range = nbio_v7_11_vpe_doorbell_range, 290 .enable_doorbell_aperture = nbio_v7_11_enable_doorbell_aperture, 291 .enable_doorbell_selfring_aperture = nbio_v7_11_enable_doorbell_selfring_aperture, 292 .ih_doorbell_range = nbio_v7_11_ih_doorbell_range, 293 .ih_control = nbio_v7_11_ih_control, 294 .init_registers = nbio_v7_11_init_registers, 295 .remap_hdp_registers = nbio_v7_11_remap_hdp_registers, 296 }; 297