1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "amdgpu.h" 24 #include "nbio_v7_0.h" 25 26 #include "nbio/nbio_7_0_default.h" 27 #include "nbio/nbio_7_0_offset.h" 28 #include "nbio/nbio_7_0_sh_mask.h" 29 #include "nbio/nbio_7_0_smn.h" 30 #include "vega10_enum.h" 31 #include <uapi/linux/kfd_ioctl.h> 32 33 #define smnNBIF_MGCG_CTRL_LCLK 0x1013a05c 34 35 static void nbio_v7_0_remap_hdp_registers(struct amdgpu_device *adev) 36 { 37 WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL, 38 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL); 39 WREG32_SOC15(NBIO, 0, mmREMAP_HDP_REG_FLUSH_CNTL, 40 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL); 41 } 42 43 static u32 nbio_v7_0_get_rev_id(struct amdgpu_device *adev) 44 { 45 u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0); 46 47 tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK; 48 tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT; 49 50 return tmp; 51 } 52 53 static void nbio_v7_0_mc_access_enable(struct amdgpu_device *adev, bool enable) 54 { 55 if (enable) 56 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 57 BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK); 58 else 59 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0); 60 } 61 62 static u32 nbio_v7_0_get_memsize(struct amdgpu_device *adev) 63 { 64 return RREG32_SOC15(NBIO, 0, mmRCC_CONFIG_MEMSIZE); 65 } 66 67 static void nbio_v7_0_sdma_doorbell_range(struct amdgpu_device *adev, int instance, 68 bool use_doorbell, int doorbell_index, int doorbell_size) 69 { 70 u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) : 71 SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE); 72 73 u32 doorbell_range = RREG32(reg); 74 75 if (use_doorbell) { 76 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index); 77 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, doorbell_size); 78 } else 79 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0); 80 81 WREG32(reg, doorbell_range); 82 } 83 84 static void nbio_v7_0_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell, 85 int doorbell_index, int instance) 86 { 87 u32 reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH0_DOORBELL_RANGE); 88 89 u32 doorbell_range = RREG32(reg); 90 91 if (use_doorbell) { 92 doorbell_range = REG_SET_FIELD(doorbell_range, 93 BIF_MMSCH0_DOORBELL_RANGE, OFFSET, 94 doorbell_index); 95 doorbell_range = REG_SET_FIELD(doorbell_range, 96 BIF_MMSCH0_DOORBELL_RANGE, SIZE, 8); 97 } else 98 doorbell_range = REG_SET_FIELD(doorbell_range, 99 BIF_MMSCH0_DOORBELL_RANGE, SIZE, 0); 100 101 WREG32(reg, doorbell_range); 102 } 103 104 static void nbio_v7_0_enable_doorbell_aperture(struct amdgpu_device *adev, 105 bool enable) 106 { 107 WREG32_FIELD15(NBIO, 0, RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, enable ? 1 : 0); 108 } 109 110 static void nbio_v7_0_enable_doorbell_selfring_aperture(struct amdgpu_device *adev, 111 bool enable) 112 { 113 114 } 115 116 static void nbio_v7_0_ih_doorbell_range(struct amdgpu_device *adev, 117 bool use_doorbell, int doorbell_index) 118 { 119 u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE); 120 121 if (use_doorbell) { 122 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index); 123 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 2); 124 } else 125 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 0); 126 127 WREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE, ih_doorbell_range); 128 } 129 130 static uint32_t nbio_7_0_read_syshub_ind_mmr(struct amdgpu_device *adev, uint32_t offset) 131 { 132 uint32_t data; 133 134 WREG32_SOC15(NBIO, 0, mmSYSHUB_INDEX, offset); 135 data = RREG32_SOC15(NBIO, 0, mmSYSHUB_DATA); 136 137 return data; 138 } 139 140 static void nbio_7_0_write_syshub_ind_mmr(struct amdgpu_device *adev, uint32_t offset, 141 uint32_t data) 142 { 143 WREG32_SOC15(NBIO, 0, mmSYSHUB_INDEX, offset); 144 WREG32_SOC15(NBIO, 0, mmSYSHUB_DATA, data); 145 } 146 147 static void nbio_v7_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 148 bool enable) 149 { 150 uint32_t def, data; 151 152 /* NBIF_MGCG_CTRL_LCLK */ 153 def = data = RREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK); 154 155 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG)) 156 data |= NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_EN_LCLK_MASK; 157 else 158 data &= ~NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_EN_LCLK_MASK; 159 160 if (def != data) 161 WREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK, data); 162 163 /* SYSHUB_MGCG_CTRL_SOCCLK */ 164 def = data = nbio_7_0_read_syshub_ind_mmr(adev, ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK); 165 166 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG)) 167 data |= SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_EN_SOCCLK_MASK; 168 else 169 data &= ~SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_EN_SOCCLK_MASK; 170 171 if (def != data) 172 nbio_7_0_write_syshub_ind_mmr(adev, ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK, data); 173 174 /* SYSHUB_MGCG_CTRL_SHUBCLK */ 175 def = data = nbio_7_0_read_syshub_ind_mmr(adev, ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK); 176 177 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG)) 178 data |= SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_EN_SHUBCLK_MASK; 179 else 180 data &= ~SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_EN_SHUBCLK_MASK; 181 182 if (def != data) 183 nbio_7_0_write_syshub_ind_mmr(adev, ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK, data); 184 } 185 186 static void nbio_v7_0_update_medium_grain_light_sleep(struct amdgpu_device *adev, 187 bool enable) 188 { 189 uint32_t def, data; 190 191 def = data = RREG32_PCIE(smnPCIE_CNTL2); 192 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) { 193 data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK | 194 PCIE_CNTL2__MST_MEM_LS_EN_MASK | 195 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK); 196 } else { 197 data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK | 198 PCIE_CNTL2__MST_MEM_LS_EN_MASK | 199 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK); 200 } 201 202 if (def != data) 203 WREG32_PCIE(smnPCIE_CNTL2, data); 204 } 205 206 static void nbio_v7_0_get_clockgating_state(struct amdgpu_device *adev, 207 u64 *flags) 208 { 209 int data; 210 211 /* AMD_CG_SUPPORT_BIF_MGCG */ 212 data = RREG32_PCIE(smnCPM_CONTROL); 213 if (data & CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK) 214 *flags |= AMD_CG_SUPPORT_BIF_MGCG; 215 216 /* AMD_CG_SUPPORT_BIF_LS */ 217 data = RREG32_PCIE(smnPCIE_CNTL2); 218 if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK) 219 *flags |= AMD_CG_SUPPORT_BIF_LS; 220 } 221 222 static void nbio_v7_0_ih_control(struct amdgpu_device *adev) 223 { 224 u32 interrupt_cntl; 225 226 /* setup interrupt control */ 227 WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8); 228 interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL); 229 /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi 230 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN 231 */ 232 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0); 233 /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */ 234 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0); 235 WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl); 236 } 237 238 static u32 nbio_v7_0_get_hdp_flush_req_offset(struct amdgpu_device *adev) 239 { 240 return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_REQ); 241 } 242 243 static u32 nbio_v7_0_get_hdp_flush_done_offset(struct amdgpu_device *adev) 244 { 245 return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_DONE); 246 } 247 248 static u32 nbio_v7_0_get_pcie_index_offset(struct amdgpu_device *adev) 249 { 250 return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2); 251 } 252 253 static u32 nbio_v7_0_get_pcie_data_offset(struct amdgpu_device *adev) 254 { 255 return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2); 256 } 257 258 const struct nbio_hdp_flush_reg nbio_v7_0_hdp_flush_reg = { 259 .ref_and_mask_cp0 = GPU_HDP_FLUSH_DONE__CP0_MASK, 260 .ref_and_mask_cp1 = GPU_HDP_FLUSH_DONE__CP1_MASK, 261 .ref_and_mask_cp2 = GPU_HDP_FLUSH_DONE__CP2_MASK, 262 .ref_and_mask_cp3 = GPU_HDP_FLUSH_DONE__CP3_MASK, 263 .ref_and_mask_cp4 = GPU_HDP_FLUSH_DONE__CP4_MASK, 264 .ref_and_mask_cp5 = GPU_HDP_FLUSH_DONE__CP5_MASK, 265 .ref_and_mask_cp6 = GPU_HDP_FLUSH_DONE__CP6_MASK, 266 .ref_and_mask_cp7 = GPU_HDP_FLUSH_DONE__CP7_MASK, 267 .ref_and_mask_cp8 = GPU_HDP_FLUSH_DONE__CP8_MASK, 268 .ref_and_mask_cp9 = GPU_HDP_FLUSH_DONE__CP9_MASK, 269 .ref_and_mask_sdma0 = GPU_HDP_FLUSH_DONE__SDMA0_MASK, 270 .ref_and_mask_sdma1 = GPU_HDP_FLUSH_DONE__SDMA1_MASK, 271 }; 272 273 #define regRCC_DEV0_EPF6_STRAP4 0xd304 274 #define regRCC_DEV0_EPF6_STRAP4_BASE_IDX 5 275 276 static void nbio_v7_0_init_registers(struct amdgpu_device *adev) 277 { 278 uint32_t data; 279 280 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) { 281 case IP_VERSION(2, 5, 0): 282 data = RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF6_STRAP4) & ~BIT(23); 283 WREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF6_STRAP4, data); 284 break; 285 } 286 } 287 288 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE) 289 290 static void nbio_v7_0_set_reg_remap(struct amdgpu_device *adev) 291 { 292 if (!amdgpu_sriov_vf(adev) && (PAGE_SIZE <= 4096)) { 293 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; 294 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; 295 } else { 296 adev->rmmio_remap.reg_offset = 297 SOC15_REG_OFFSET(NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL) << 2; 298 adev->rmmio_remap.bus_addr = 0; 299 } 300 } 301 302 const struct amdgpu_nbio_funcs nbio_v7_0_funcs = { 303 .get_hdp_flush_req_offset = nbio_v7_0_get_hdp_flush_req_offset, 304 .get_hdp_flush_done_offset = nbio_v7_0_get_hdp_flush_done_offset, 305 .get_pcie_index_offset = nbio_v7_0_get_pcie_index_offset, 306 .get_pcie_data_offset = nbio_v7_0_get_pcie_data_offset, 307 .get_rev_id = nbio_v7_0_get_rev_id, 308 .mc_access_enable = nbio_v7_0_mc_access_enable, 309 .get_memsize = nbio_v7_0_get_memsize, 310 .sdma_doorbell_range = nbio_v7_0_sdma_doorbell_range, 311 .vcn_doorbell_range = nbio_v7_0_vcn_doorbell_range, 312 .enable_doorbell_aperture = nbio_v7_0_enable_doorbell_aperture, 313 .enable_doorbell_selfring_aperture = nbio_v7_0_enable_doorbell_selfring_aperture, 314 .ih_doorbell_range = nbio_v7_0_ih_doorbell_range, 315 .update_medium_grain_clock_gating = nbio_v7_0_update_medium_grain_clock_gating, 316 .update_medium_grain_light_sleep = nbio_v7_0_update_medium_grain_light_sleep, 317 .get_clockgating_state = nbio_v7_0_get_clockgating_state, 318 .ih_control = nbio_v7_0_ih_control, 319 .init_registers = nbio_v7_0_init_registers, 320 .remap_hdp_registers = nbio_v7_0_remap_hdp_registers, 321 .set_reg_remap = nbio_v7_0_set_reg_remap, 322 }; 323