1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "amdgpu.h" 24 #include "nbif_v6_3_1.h" 25 26 #include "nbif/nbif_6_3_1_offset.h" 27 #include "nbif/nbif_6_3_1_sh_mask.h" 28 #include "pcie/pcie_6_1_0_offset.h" 29 #include "pcie/pcie_6_1_0_sh_mask.h" 30 #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h" 31 #include <uapi/linux/kfd_ioctl.h> 32 33 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL_nbif_4_10 0x4f0aeb 34 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL_nbif_4_10_BASE_IDX 3 35 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL1_nbif_4_10 0x4f0aec 36 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL1_nbif_4_10_BASE_IDX 3 37 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL_nbif_4_10 0x4f0aed 38 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL_nbif_4_10_BASE_IDX 3 39 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL1_nbif_4_10 0x4f0aee 40 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL1_nbif_4_10_BASE_IDX 3 41 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL_nbif_4_10 0x4f0aef 42 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL_nbif_4_10_BASE_IDX 3 43 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1_nbif_4_10 0x4f0af0 44 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1_nbif_4_10_BASE_IDX 3 45 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL_nbif_4_10 0x4f0af1 46 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL_nbif_4_10_BASE_IDX 3 47 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL1_nbif_4_10 0x4f0af2 48 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL1_nbif_4_10_BASE_IDX 3 49 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL_nbif_4_10 0x4f0af3 50 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL_nbif_4_10_BASE_IDX 3 51 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL1_nbif_4_10 0x4f0af4 52 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL1_nbif_4_10_BASE_IDX 3 53 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL_nbif_4_10 0x4f0af5 54 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL_nbif_4_10_BASE_IDX 3 55 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL1_nbif_4_10 0x4f0af6 56 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL1_nbif_4_10_BASE_IDX 3 57 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_nbif_4_10 0x0021 58 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_nbif_4_10_BASE_IDX 2 59 60 #define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_nbio_7_11_5 0x8e13 61 #define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_nbio_7_11_5_BASE_IDX 5 62 #define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_nbio_7_11_5 0x8e14 63 #define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_nbio_7_11_5_BASE_IDX 5 64 #define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL_nbio_7_11_5 0x8e15 65 #define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL_nbio_7_11_5_BASE_IDX 5 66 67 #define regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL_nbio_7_11_5 0x8e4d 68 #define regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL_nbio_7_11_5_BASE_IDX 5 69 #define regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL_nbio_7_11_5 0x8e4e 70 #define regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL_nbio_7_11_5_BASE_IDX 5 71 72 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_nbio_7_11_5 0xd000 73 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_nbio_7_11_5_BASE_IDX 5 74 75 #define regBIF_BX0_BIF_FB_EN_nbio_7_11_5 0x8e20 76 #define regBIF_BX0_BIF_FB_EN_nbio_7_11_5_BASE_IDX 5 77 78 #define regBIF_BX0_INTERRUPT_CNTL_nbio_7_11_5 0x8e11 79 #define regBIF_BX0_INTERRUPT_CNTL_nbio_7_11_5_BASE_IDX 5 80 #define regBIF_BX0_INTERRUPT_CNTL2_nbio_7_11_5 0x8e12 81 #define regBIF_BX0_INTERRUPT_CNTL2_nbio_7_11_5_BASE_IDX 5 82 83 #define regBIF_BX_PF0_GPU_HDP_FLUSH_REQ_nbio_7_11_5 0x8e26 84 #define regBIF_BX_PF0_GPU_HDP_FLUSH_REQ_nbio_7_11_5_BASE_IDX 5 85 #define regBIF_BX_PF0_GPU_HDP_FLUSH_DONE_nbio_7_11_5 0x8e27 86 #define regBIF_BX_PF0_GPU_HDP_FLUSH_DONE_nbio_7_11_5_BASE_IDX 5 87 88 #define regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL_nbio_7_11_5 0x8e17 89 #define regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL_nbio_7_11_5_BASE_IDX 5 90 91 static void nbif_v6_3_1_remap_hdp_registers(struct amdgpu_device *adev) 92 { 93 if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 5)) { 94 WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL_nbio_7_11_5, 95 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL); 96 WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL_nbio_7_11_5, 97 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL); 98 } else { 99 WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL, 100 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL); 101 WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL, 102 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL); 103 } 104 } 105 106 static u32 nbif_v6_3_1_get_rev_id(struct amdgpu_device *adev) 107 { 108 u32 tmp; 109 110 if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 4)) 111 tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_nbif_4_10); 112 else if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 5)) 113 tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_nbio_7_11_5); 114 else 115 tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0); 116 117 tmp &= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK; 118 tmp >>= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT; 119 120 return tmp; 121 } 122 123 static void nbif_v6_3_1_mc_access_enable(struct amdgpu_device *adev, bool enable) 124 { 125 if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 5)) { 126 if (enable) 127 WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN_nbio_7_11_5, 128 BIF_BX0_BIF_FB_EN__FB_READ_EN_MASK | 129 BIF_BX0_BIF_FB_EN__FB_WRITE_EN_MASK); 130 else 131 WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN_nbio_7_11_5, 0); 132 } else { 133 if (enable) 134 WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN, 135 BIF_BX0_BIF_FB_EN__FB_READ_EN_MASK | 136 BIF_BX0_BIF_FB_EN__FB_WRITE_EN_MASK); 137 else 138 WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN, 0); 139 } 140 } 141 142 static u32 nbif_v6_3_1_get_memsize(struct amdgpu_device *adev) 143 { 144 return RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE); 145 } 146 147 static void nbif_v6_3_1_sdma_doorbell_range(struct amdgpu_device *adev, 148 int instance, bool use_doorbell, 149 int doorbell_index, 150 int doorbell_size) 151 { 152 u32 doorbell_range; 153 if (instance == 0) { 154 if (amdgpu_ip_version(adev, NBIO_HWIP, 0) >= IP_VERSION(7, 11, 4)) 155 doorbell_range = RREG32_SOC15(NBIO, 0, 156 regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL_nbif_4_10); 157 else 158 doorbell_range = RREG32_SOC15(NBIO, 0, 159 regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL); 160 161 if (use_doorbell) { 162 doorbell_range = REG_SET_FIELD(doorbell_range, 163 GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL, 164 S2A_DOORBELL_PORT2_ENABLE, 165 0x1); 166 doorbell_range = REG_SET_FIELD(doorbell_range, 167 GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL, 168 S2A_DOORBELL_PORT2_AWID, 169 0xe); 170 doorbell_range = REG_SET_FIELD(doorbell_range, 171 GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL, 172 S2A_DOORBELL_PORT2_RANGE_OFFSET, 173 doorbell_index); 174 doorbell_range = REG_SET_FIELD(doorbell_range, 175 GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL, 176 S2A_DOORBELL_PORT2_RANGE_SIZE, 177 doorbell_size); 178 doorbell_range = REG_SET_FIELD(doorbell_range, 179 GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL, 180 S2A_DOORBELL_PORT2_AWADDR_31_28_VALUE, 181 0x3); 182 } else 183 doorbell_range = REG_SET_FIELD(doorbell_range, 184 GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL, 185 S2A_DOORBELL_PORT2_RANGE_SIZE, 186 0); 187 188 if (amdgpu_ip_version(adev, NBIO_HWIP, 0) >= IP_VERSION(7, 11, 4)) 189 WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL_nbif_4_10, doorbell_range); 190 else 191 WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL, doorbell_range); 192 } 193 } 194 195 static void nbif_v6_3_1_vcn_doorbell_range(struct amdgpu_device *adev, 196 bool use_doorbell, int doorbell_index, 197 int instance) 198 { 199 u32 doorbell_range; 200 201 if (instance) { 202 if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 4)) 203 return; 204 doorbell_range = RREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL); 205 } else { 206 doorbell_range = RREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL); 207 } 208 209 if (use_doorbell) { 210 doorbell_range = REG_SET_FIELD(doorbell_range, 211 GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL, 212 S2A_DOORBELL_PORT4_ENABLE, 213 0x1); 214 doorbell_range = REG_SET_FIELD(doorbell_range, 215 GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL, 216 S2A_DOORBELL_PORT4_AWID, 217 instance ? 0x7 : 0x4); 218 doorbell_range = REG_SET_FIELD(doorbell_range, 219 GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL, 220 S2A_DOORBELL_PORT4_RANGE_OFFSET, 221 doorbell_index); 222 doorbell_range = REG_SET_FIELD(doorbell_range, 223 GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL, 224 S2A_DOORBELL_PORT4_RANGE_SIZE, 225 8); 226 doorbell_range = REG_SET_FIELD(doorbell_range, 227 GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL, 228 S2A_DOORBELL_PORT4_AWADDR_31_28_VALUE, 229 instance ? 0x7 : 0x4); 230 } else 231 doorbell_range = REG_SET_FIELD(doorbell_range, 232 GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL, 233 S2A_DOORBELL_PORT4_RANGE_SIZE, 234 0); 235 236 if (amdgpu_ip_version(adev, NBIO_HWIP, 0) >= IP_VERSION(7, 11, 4)) 237 WREG32_SOC15(NBIO, 0, 238 regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL_nbif_4_10, 239 doorbell_range); 240 else 241 if (instance) 242 WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL, doorbell_range); 243 else 244 WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL, doorbell_range); 245 } 246 247 static void nbif_v6_3_1_vpe_doorbell_range(struct amdgpu_device *adev, 248 int instance, bool use_doorbell, 249 int doorbell_index, 250 int doorbell_size) 251 { 252 if (instance) 253 return; 254 255 u32 doorbell_range = RREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL); 256 257 if (use_doorbell) { 258 doorbell_range = REG_SET_FIELD(doorbell_range, 259 GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL, 260 S2A_DOORBELL_PORT5_ENABLE, 261 0x1); 262 doorbell_range = REG_SET_FIELD(doorbell_range, 263 GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL, 264 S2A_DOORBELL_PORT5_AWID, 265 0xf); 266 doorbell_range = REG_SET_FIELD(doorbell_range, 267 GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL, 268 S2A_DOORBELL_PORT5_RANGE_OFFSET, 269 doorbell_index); 270 doorbell_range = REG_SET_FIELD(doorbell_range, 271 GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL, 272 S2A_DOORBELL_PORT5_RANGE_SIZE, 273 doorbell_size); 274 doorbell_range = REG_SET_FIELD(doorbell_range, 275 GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL, 276 S2A_DOORBELL_PORT5_AWADDR_31_28_VALUE, 277 0xf); 278 } else { 279 doorbell_range = REG_SET_FIELD(doorbell_range, 280 GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL, 281 S2A_DOORBELL_PORT5_RANGE_SIZE, 282 0); 283 } 284 285 if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 4) || 286 amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 5)) { 287 WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL_nbif_4_10, doorbell_range); 288 } else { 289 WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL, doorbell_range); 290 } 291 292 } 293 294 static void nbif_v6_3_1_gc_doorbell_init(struct amdgpu_device *adev) 295 { 296 if (amdgpu_ip_version(adev, NBIO_HWIP, 0) >= IP_VERSION(7, 11, 4)) { 297 WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL_nbif_4_10, 0x30000007); 298 WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL_nbif_4_10, 0x3000000d); 299 } else { 300 WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL, 0x30000007); 301 WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL, 0x3000000d); 302 } 303 } 304 305 static void nbif_v6_3_1_enable_doorbell_aperture(struct amdgpu_device *adev, 306 bool enable) 307 { 308 WREG32_FIELD15_PREREG(NBIO, 0, RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN, 309 BIF_DOORBELL_APER_EN, enable ? 1 : 0); 310 } 311 312 static void 313 nbif_v6_3_1_enable_doorbell_selfring_aperture(struct amdgpu_device *adev, 314 bool enable) 315 { 316 u32 tmp = 0; 317 318 if (enable) { 319 tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, 320 DOORBELL_SELFRING_GPA_APER_EN, 1) | 321 REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, 322 DOORBELL_SELFRING_GPA_APER_MODE, 1) | 323 REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, 324 DOORBELL_SELFRING_GPA_APER_SIZE, 0); 325 326 WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW, 327 lower_32_bits(adev->doorbell.base)); 328 WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH, 329 upper_32_bits(adev->doorbell.base)); 330 } 331 332 WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, tmp); 333 } 334 335 static void nbif_v6_3_1_ih_doorbell_range(struct amdgpu_device *adev, 336 bool use_doorbell, int doorbell_index) 337 { 338 u32 ih_doorbell_range; 339 340 if (amdgpu_ip_version(adev, NBIO_HWIP, 0) >= IP_VERSION(7, 11, 4)) 341 ih_doorbell_range = RREG32_SOC15(NBIO, 0, 342 regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL_nbif_4_10); 343 else 344 ih_doorbell_range = RREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL); 345 346 if (use_doorbell) { 347 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 348 GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL, 349 S2A_DOORBELL_PORT1_ENABLE, 350 0x1); 351 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 352 GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL, 353 S2A_DOORBELL_PORT1_AWID, 354 0x0); 355 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 356 GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL, 357 S2A_DOORBELL_PORT1_RANGE_OFFSET, 358 doorbell_index); 359 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 360 GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL, 361 S2A_DOORBELL_PORT1_RANGE_SIZE, 362 2); 363 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 364 GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL, 365 S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE, 366 0x0); 367 } else 368 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 369 GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL, 370 S2A_DOORBELL_PORT1_RANGE_SIZE, 371 0); 372 373 if (amdgpu_ip_version(adev, NBIO_HWIP, 0) >= IP_VERSION(7, 11, 4)) 374 WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL_nbif_4_10, 375 ih_doorbell_range); 376 else 377 WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL, ih_doorbell_range); 378 } 379 380 static void nbif_v6_3_1_ih_control(struct amdgpu_device *adev) 381 { 382 u32 interrupt_cntl; 383 384 /* setup interrupt control */ 385 if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 5)) 386 WREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL2_nbio_7_11_5, 387 adev->dummy_page_addr >> 8); 388 else 389 WREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL2, adev->dummy_page_addr >> 8); 390 391 interrupt_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL_nbio_7_11_5); 392 /* 393 * BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi 394 * BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN 395 */ 396 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL, 397 IH_DUMMY_RD_OVERRIDE, 0); 398 399 /* BIF_BX0_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */ 400 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL, 401 IH_REQ_NONSNOOP_EN, 0); 402 403 if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 5)) 404 WREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL_nbio_7_11_5, interrupt_cntl); 405 else 406 WREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL, interrupt_cntl); 407 } 408 409 static void 410 nbif_v6_3_1_update_medium_grain_clock_gating(struct amdgpu_device *adev, 411 bool enable) 412 { 413 } 414 415 static void 416 nbif_v6_3_1_update_medium_grain_light_sleep(struct amdgpu_device *adev, 417 bool enable) 418 { 419 } 420 421 static void 422 nbif_v6_3_1_get_clockgating_state(struct amdgpu_device *adev, 423 u64 *flags) 424 { 425 } 426 427 static u32 nbif_v6_3_1_get_hdp_flush_req_offset(struct amdgpu_device *adev) 428 { 429 if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 5)) 430 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_REQ_nbio_7_11_5); 431 else 432 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_REQ); 433 } 434 435 static u32 nbif_v6_3_1_get_hdp_flush_done_offset(struct amdgpu_device *adev) 436 { 437 if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 5)) 438 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_DONE_nbio_7_11_5); 439 else 440 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_DONE); 441 } 442 443 static u32 nbif_v6_3_1_get_pcie_index_offset(struct amdgpu_device *adev) 444 { 445 if (amdgpu_ip_version(adev, NBIO_HWIP, 0) >= IP_VERSION(7, 11, 4)) 446 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_INDEX); 447 else 448 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_INDEX); 449 } 450 451 static u32 nbif_v6_3_1_get_pcie_data_offset(struct amdgpu_device *adev) 452 { 453 if (amdgpu_ip_version(adev, NBIO_HWIP, 0) >= IP_VERSION(7, 11, 4)) 454 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_DATA); 455 else 456 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_DATA); 457 } 458 459 const struct nbio_hdp_flush_reg nbif_v6_3_1_hdp_flush_reg = { 460 .ref_and_mask_cp0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK, 461 .ref_and_mask_cp1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1_MASK, 462 .ref_and_mask_cp2 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2_MASK, 463 .ref_and_mask_cp3 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3_MASK, 464 .ref_and_mask_cp4 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4_MASK, 465 .ref_and_mask_cp5 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5_MASK, 466 .ref_and_mask_cp6 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6_MASK, 467 .ref_and_mask_cp7 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7_MASK, 468 .ref_and_mask_cp8 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8_MASK, 469 .ref_and_mask_cp9 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9_MASK, 470 .ref_and_mask_sdma0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK, 471 .ref_and_mask_sdma1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK, 472 }; 473 474 static void nbif_v6_3_1_init_registers(struct amdgpu_device *adev) 475 { 476 uint32_t data; 477 478 data = RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF2_STRAP2); 479 data &= ~RCC_DEV0_EPF2_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F2_MASK; 480 WREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF2_STRAP2, data); 481 } 482 483 static u32 nbif_v6_3_1_get_rom_offset(struct amdgpu_device *adev) 484 { 485 u32 data, rom_offset; 486 487 data = RREG32_SOC15(NBIO, 0, regREGS_ROM_OFFSET_CTRL); 488 rom_offset = REG_GET_FIELD(data, REGS_ROM_OFFSET_CTRL, ROM_OFFSET); 489 490 return rom_offset; 491 } 492 493 #ifdef CONFIG_PCIEASPM 494 static void nbif_v6_3_1_program_ltr(struct amdgpu_device *adev) 495 { 496 uint32_t def, data; 497 u16 devctl2; 498 499 def = RREG32_SOC15(NBIO, 0, regRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL); 500 data = 0x35EB; 501 data &= ~RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK; 502 data &= ~RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK; 503 if (def != data) 504 WREG32_SOC15(NBIO, 0, regRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL, data); 505 506 def = data = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP2); 507 data &= ~RCC_STRAP0_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK; 508 if (def != data) 509 WREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP2, data); 510 511 pcie_capability_read_word(adev->pdev, PCI_EXP_DEVCTL2, &devctl2); 512 513 if (adev->pdev->ltr_path == (devctl2 & PCI_EXP_DEVCTL2_LTR_EN)) 514 return; 515 516 if (adev->pdev->ltr_path) 517 pcie_capability_set_word(adev->pdev, PCI_EXP_DEVCTL2, PCI_EXP_DEVCTL2_LTR_EN); 518 else 519 pcie_capability_clear_word(adev->pdev, PCI_EXP_DEVCTL2, PCI_EXP_DEVCTL2_LTR_EN); 520 } 521 #endif 522 523 static void nbif_v6_3_1_program_aspm(struct amdgpu_device *adev) 524 { 525 #ifdef CONFIG_PCIEASPM 526 uint32_t def, data; 527 u16 devctl2, ltr; 528 529 def = data = RREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL); 530 data &= ~PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK; 531 data &= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK; 532 data |= PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK; 533 if (def != data) 534 WREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL, data); 535 536 def = data = RREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL7); 537 data |= PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN_MASK; 538 if (def != data) 539 WREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL7, data); 540 541 def = data = RREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL3); 542 data |= PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK; 543 if (def != data) 544 WREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL3, data); 545 546 def = data = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP3); 547 data &= ~RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK; 548 data &= ~RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK; 549 if (def != data) 550 WREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP3, data); 551 552 def = data = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP5); 553 data &= ~RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK; 554 if (def != data) 555 WREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP5, data); 556 557 pcie_capability_read_word(adev->pdev, PCI_EXP_DEVCTL2, &devctl2); 558 data = def = devctl2; 559 data &= ~PCI_EXP_DEVCTL2_LTR_EN; 560 if (def != data) 561 pcie_capability_set_word(adev->pdev, PCI_EXP_DEVCTL2, (u16)data); 562 563 ltr = pci_find_ext_capability(adev->pdev, PCI_EXT_CAP_ID_LTR); 564 565 if (ltr) { 566 pci_write_config_dword(adev->pdev, ltr + PCI_LTR_MAX_SNOOP_LAT, 0x10011001); 567 } 568 569 #if 0 570 /* regPSWUSP0_PCIE_LC_CNTL2 should be replace by PCIE_LC_CNTL2 or someone else ? */ 571 def = data = RREG32_SOC15(NBIO, 0, regPSWUSP0_PCIE_LC_CNTL2); 572 data |= PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK | 573 PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK; 574 data &= ~PSWUSP0_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK; 575 if (def != data) 576 WREG32_SOC15(NBIO, 0, regPSWUSP0_PCIE_LC_CNTL2, data); 577 #endif 578 def = data = RREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL4); 579 data |= PCIE_LC_CNTL4__LC_L1_POWERDOWN_MASK; 580 if (def != data) 581 WREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL4, data); 582 583 def = data = RREG32_SOC15(PCIE, 0, regPCIE_LC_RXRECOVER_RXSTANDBY_CNTL); 584 data |= PCIE_LC_RXRECOVER_RXSTANDBY_CNTL__LC_RX_L0S_STANDBY_EN_MASK; 585 if (def != data) 586 WREG32_SOC15(PCIE, 0, regPCIE_LC_RXRECOVER_RXSTANDBY_CNTL, data); 587 588 nbif_v6_3_1_program_ltr(adev); 589 590 def = data = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP3); 591 data |= 0x5DE0 << RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT; 592 data |= 0x0010 << RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT; 593 if (def != data) 594 WREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP3, data); 595 596 def = data = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP5); 597 data |= 0x0010 << RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT; 598 if (def != data) 599 WREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP5, data); 600 601 def = data = RREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL); 602 data |= 0x0 << PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT; 603 data |= 0x9 << PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT; 604 data &= ~PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK; 605 if (def != data) 606 WREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL, data); 607 608 def = data = RREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL3); 609 data &= ~PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK; 610 if (def != data) 611 WREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL3, data); 612 #endif 613 } 614 615 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE) 616 617 static void nbif_v6_3_1_set_reg_remap(struct amdgpu_device *adev) 618 { 619 if (!amdgpu_sriov_vf(adev) && (PAGE_SIZE <= 4096)) { 620 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; 621 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; 622 } else { 623 if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 5)) 624 adev->rmmio_remap.reg_offset = SOC15_REG_OFFSET(NBIO, 0, 625 regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL_nbio_7_11_5) << 2; 626 else 627 adev->rmmio_remap.reg_offset = SOC15_REG_OFFSET(NBIO, 0, 628 regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL) << 2; 629 adev->rmmio_remap.bus_addr = 0; 630 } 631 } 632 633 const struct amdgpu_nbio_funcs nbif_v6_3_1_funcs = { 634 .get_hdp_flush_req_offset = nbif_v6_3_1_get_hdp_flush_req_offset, 635 .get_hdp_flush_done_offset = nbif_v6_3_1_get_hdp_flush_done_offset, 636 .get_pcie_index_offset = nbif_v6_3_1_get_pcie_index_offset, 637 .get_pcie_data_offset = nbif_v6_3_1_get_pcie_data_offset, 638 .get_rev_id = nbif_v6_3_1_get_rev_id, 639 .mc_access_enable = nbif_v6_3_1_mc_access_enable, 640 .get_memsize = nbif_v6_3_1_get_memsize, 641 .sdma_doorbell_range = nbif_v6_3_1_sdma_doorbell_range, 642 .vcn_doorbell_range = nbif_v6_3_1_vcn_doorbell_range, 643 .vpe_doorbell_range = nbif_v6_3_1_vpe_doorbell_range, 644 .gc_doorbell_init = nbif_v6_3_1_gc_doorbell_init, 645 .enable_doorbell_aperture = nbif_v6_3_1_enable_doorbell_aperture, 646 .enable_doorbell_selfring_aperture = nbif_v6_3_1_enable_doorbell_selfring_aperture, 647 .ih_doorbell_range = nbif_v6_3_1_ih_doorbell_range, 648 .update_medium_grain_clock_gating = nbif_v6_3_1_update_medium_grain_clock_gating, 649 .update_medium_grain_light_sleep = nbif_v6_3_1_update_medium_grain_light_sleep, 650 .get_clockgating_state = nbif_v6_3_1_get_clockgating_state, 651 .ih_control = nbif_v6_3_1_ih_control, 652 .init_registers = nbif_v6_3_1_init_registers, 653 .remap_hdp_registers = nbif_v6_3_1_remap_hdp_registers, 654 .get_rom_offset = nbif_v6_3_1_get_rom_offset, 655 .program_aspm = nbif_v6_3_1_program_aspm, 656 .set_reg_remap = nbif_v6_3_1_set_reg_remap, 657 }; 658 659 660 static int nbif_v6_3_1_set_ras_err_event_athub_irq_state(struct amdgpu_device *adev, 661 struct amdgpu_irq_src *src, 662 unsigned type, 663 enum amdgpu_interrupt_state state) 664 { 665 /* The ras_controller_irq enablement should be done in psp bl when it 666 * tries to enable ras feature. Driver only need to set the correct interrupt 667 * vector for bare-metal and sriov use case respectively 668 */ 669 uint32_t bif_doorbell_int_cntl; 670 671 bif_doorbell_int_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_DOORBELL_INT_CNTL); 672 bif_doorbell_int_cntl = REG_SET_FIELD(bif_doorbell_int_cntl, 673 BIF_BX0_BIF_DOORBELL_INT_CNTL, 674 RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE, 675 (state == AMDGPU_IRQ_STATE_ENABLE) ? 0 : 1); 676 WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_DOORBELL_INT_CNTL, bif_doorbell_int_cntl); 677 678 return 0; 679 } 680 681 static int nbif_v6_3_1_process_err_event_athub_irq(struct amdgpu_device *adev, 682 struct amdgpu_irq_src *source, 683 struct amdgpu_iv_entry *entry) 684 { 685 /* By design, the ih cookie for err_event_athub_irq should be written 686 * to bif ring. since bif ring is not enabled, just leave process callback 687 * as a dummy one. 688 */ 689 return 0; 690 } 691 692 static const struct amdgpu_irq_src_funcs nbif_v6_3_1_ras_err_event_athub_irq_funcs = { 693 .set = nbif_v6_3_1_set_ras_err_event_athub_irq_state, 694 .process = nbif_v6_3_1_process_err_event_athub_irq, 695 }; 696 697 static void nbif_v6_3_1_handle_ras_err_event_athub_intr_no_bifring(struct amdgpu_device *adev) 698 { 699 uint32_t bif_doorbell_int_cntl; 700 701 bif_doorbell_int_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_DOORBELL_INT_CNTL); 702 if (REG_GET_FIELD(bif_doorbell_int_cntl, 703 BIF_BX0_BIF_DOORBELL_INT_CNTL, 704 RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS)) { 705 /* driver has to clear the interrupt status when bif ring is disabled */ 706 bif_doorbell_int_cntl = REG_SET_FIELD(bif_doorbell_int_cntl, 707 BIF_BX0_BIF_DOORBELL_INT_CNTL, 708 RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR, 1); 709 WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_DOORBELL_INT_CNTL, bif_doorbell_int_cntl); 710 amdgpu_ras_global_ras_isr(adev); 711 } 712 } 713 714 static int nbif_v6_3_1_init_ras_err_event_athub_interrupt(struct amdgpu_device *adev) 715 { 716 int r; 717 718 /* init the irq funcs */ 719 adev->nbio.ras_err_event_athub_irq.funcs = 720 &nbif_v6_3_1_ras_err_event_athub_irq_funcs; 721 adev->nbio.ras_err_event_athub_irq.num_types = 1; 722 723 /* register ras err event athub interrupt 724 * nbif v6_3_1 uses the same irq source as nbio v7_4 725 */ 726 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_BIF, 727 NBIF_7_4__SRCID__ERREVENT_ATHUB_INTERRUPT, 728 &adev->nbio.ras_err_event_athub_irq); 729 730 return r; 731 } 732 733 struct amdgpu_nbio_ras nbif_v6_3_1_ras = { 734 .handle_ras_err_event_athub_intr_no_bifring = 735 nbif_v6_3_1_handle_ras_err_event_athub_intr_no_bifring, 736 .init_ras_err_event_athub_interrupt = 737 nbif_v6_3_1_init_ras_err_event_athub_interrupt, 738 }; 739