1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "amdgpu.h" 24 #include "nbif_v6_3_1.h" 25 26 #include "nbif/nbif_6_3_1_offset.h" 27 #include "nbif/nbif_6_3_1_sh_mask.h" 28 #include "pcie/pcie_6_1_0_offset.h" 29 #include "pcie/pcie_6_1_0_sh_mask.h" 30 #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h" 31 #include <uapi/linux/kfd_ioctl.h> 32 33 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL_nbif_4_10 0x4f0aeb 34 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL_nbif_4_10_BASE_IDX 3 35 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL1_nbif_4_10 0x4f0aec 36 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL1_nbif_4_10_BASE_IDX 3 37 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL_nbif_4_10 0x4f0aed 38 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL_nbif_4_10_BASE_IDX 3 39 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL1_nbif_4_10 0x4f0aee 40 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL1_nbif_4_10_BASE_IDX 3 41 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL_nbif_4_10 0x4f0aef 42 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL_nbif_4_10_BASE_IDX 3 43 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1_nbif_4_10 0x4f0af0 44 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1_nbif_4_10_BASE_IDX 3 45 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL_nbif_4_10 0x4f0af1 46 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL_nbif_4_10_BASE_IDX 3 47 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL1_nbif_4_10 0x4f0af2 48 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL1_nbif_4_10_BASE_IDX 3 49 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL_nbif_4_10 0x4f0af3 50 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL_nbif_4_10_BASE_IDX 3 51 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL1_nbif_4_10 0x4f0af4 52 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL1_nbif_4_10_BASE_IDX 3 53 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL_nbif_4_10 0x4f0af5 54 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL_nbif_4_10_BASE_IDX 3 55 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL1_nbif_4_10 0x4f0af6 56 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL1_nbif_4_10_BASE_IDX 3 57 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_nbif_4_10 0x0021 58 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_nbif_4_10_BASE_IDX 2 59 60 static void nbif_v6_3_1_remap_hdp_registers(struct amdgpu_device *adev) 61 { 62 WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL, 63 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL); 64 WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL, 65 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL); 66 } 67 68 static u32 nbif_v6_3_1_get_rev_id(struct amdgpu_device *adev) 69 { 70 u32 tmp; 71 72 if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 4)) 73 tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_nbif_4_10); 74 else 75 tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0); 76 77 tmp &= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK; 78 tmp >>= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT; 79 80 return tmp; 81 } 82 83 static void nbif_v6_3_1_mc_access_enable(struct amdgpu_device *adev, bool enable) 84 { 85 if (enable) 86 WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN, 87 BIF_BX0_BIF_FB_EN__FB_READ_EN_MASK | 88 BIF_BX0_BIF_FB_EN__FB_WRITE_EN_MASK); 89 else 90 WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN, 0); 91 } 92 93 static u32 nbif_v6_3_1_get_memsize(struct amdgpu_device *adev) 94 { 95 return RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE); 96 } 97 98 static void nbif_v6_3_1_sdma_doorbell_range(struct amdgpu_device *adev, 99 int instance, bool use_doorbell, 100 int doorbell_index, 101 int doorbell_size) 102 { 103 if (instance == 0) { 104 u32 doorbell_range = RREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL); 105 106 if (use_doorbell) { 107 doorbell_range = REG_SET_FIELD(doorbell_range, 108 GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL, 109 S2A_DOORBELL_PORT2_ENABLE, 110 0x1); 111 doorbell_range = REG_SET_FIELD(doorbell_range, 112 GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL, 113 S2A_DOORBELL_PORT2_AWID, 114 0xe); 115 doorbell_range = REG_SET_FIELD(doorbell_range, 116 GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL, 117 S2A_DOORBELL_PORT2_RANGE_OFFSET, 118 doorbell_index); 119 doorbell_range = REG_SET_FIELD(doorbell_range, 120 GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL, 121 S2A_DOORBELL_PORT2_RANGE_SIZE, 122 doorbell_size); 123 doorbell_range = REG_SET_FIELD(doorbell_range, 124 GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL, 125 S2A_DOORBELL_PORT2_AWADDR_31_28_VALUE, 126 0x3); 127 } else 128 doorbell_range = REG_SET_FIELD(doorbell_range, 129 GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL, 130 S2A_DOORBELL_PORT2_RANGE_SIZE, 131 0); 132 133 if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 4)) { 134 WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL_nbif_4_10, doorbell_range); 135 } else { 136 WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL, doorbell_range); 137 } 138 } 139 } 140 141 static void nbif_v6_3_1_vcn_doorbell_range(struct amdgpu_device *adev, 142 bool use_doorbell, int doorbell_index, 143 int instance) 144 { 145 u32 doorbell_range; 146 147 if (instance) { 148 if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 4)) 149 return; 150 doorbell_range = RREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL); 151 } else { 152 doorbell_range = RREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL); 153 } 154 155 if (use_doorbell) { 156 doorbell_range = REG_SET_FIELD(doorbell_range, 157 GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL, 158 S2A_DOORBELL_PORT4_ENABLE, 159 0x1); 160 doorbell_range = REG_SET_FIELD(doorbell_range, 161 GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL, 162 S2A_DOORBELL_PORT4_AWID, 163 instance ? 0x7 : 0x4); 164 doorbell_range = REG_SET_FIELD(doorbell_range, 165 GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL, 166 S2A_DOORBELL_PORT4_RANGE_OFFSET, 167 doorbell_index); 168 doorbell_range = REG_SET_FIELD(doorbell_range, 169 GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL, 170 S2A_DOORBELL_PORT4_RANGE_SIZE, 171 8); 172 doorbell_range = REG_SET_FIELD(doorbell_range, 173 GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL, 174 S2A_DOORBELL_PORT4_AWADDR_31_28_VALUE, 175 instance ? 0x7 : 0x4); 176 } else 177 doorbell_range = REG_SET_FIELD(doorbell_range, 178 GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL, 179 S2A_DOORBELL_PORT4_RANGE_SIZE, 180 0); 181 182 if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 4)) { 183 WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL_nbif_4_10, doorbell_range); 184 } else { 185 if (instance) 186 WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL, doorbell_range); 187 else 188 WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL, doorbell_range); 189 } 190 } 191 192 static void nbif_v6_3_1_vpe_doorbell_range(struct amdgpu_device *adev, 193 int instance, bool use_doorbell, 194 int doorbell_index, 195 int doorbell_size) 196 { 197 if (instance) 198 return; 199 200 u32 doorbell_range = RREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL); 201 202 if (use_doorbell) { 203 doorbell_range = REG_SET_FIELD(doorbell_range, 204 GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL, 205 S2A_DOORBELL_PORT5_ENABLE, 206 0x1); 207 doorbell_range = REG_SET_FIELD(doorbell_range, 208 GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL, 209 S2A_DOORBELL_PORT5_AWID, 210 0xf); 211 doorbell_range = REG_SET_FIELD(doorbell_range, 212 GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL, 213 S2A_DOORBELL_PORT5_RANGE_OFFSET, 214 doorbell_index); 215 doorbell_range = REG_SET_FIELD(doorbell_range, 216 GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL, 217 S2A_DOORBELL_PORT5_RANGE_SIZE, 218 doorbell_size); 219 doorbell_range = REG_SET_FIELD(doorbell_range, 220 GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL, 221 S2A_DOORBELL_PORT5_AWADDR_31_28_VALUE, 222 0xf); 223 } else { 224 doorbell_range = REG_SET_FIELD(doorbell_range, 225 GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL, 226 S2A_DOORBELL_PORT5_RANGE_SIZE, 227 0); 228 } 229 230 if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 4)) 231 WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL_nbif_4_10, doorbell_range); 232 else 233 WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL, doorbell_range); 234 235 } 236 237 static void nbif_v6_3_1_gc_doorbell_init(struct amdgpu_device *adev) 238 { 239 if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 4)) { 240 WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL_nbif_4_10, 0x30000007); 241 WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL_nbif_4_10, 0x3000000d); 242 } else { 243 WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL, 0x30000007); 244 WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL, 0x3000000d); 245 } 246 } 247 248 static void nbif_v6_3_1_enable_doorbell_aperture(struct amdgpu_device *adev, 249 bool enable) 250 { 251 WREG32_FIELD15_PREREG(NBIO, 0, RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN, 252 BIF_DOORBELL_APER_EN, enable ? 1 : 0); 253 } 254 255 static void 256 nbif_v6_3_1_enable_doorbell_selfring_aperture(struct amdgpu_device *adev, 257 bool enable) 258 { 259 u32 tmp = 0; 260 261 if (enable) { 262 tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, 263 DOORBELL_SELFRING_GPA_APER_EN, 1) | 264 REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, 265 DOORBELL_SELFRING_GPA_APER_MODE, 1) | 266 REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, 267 DOORBELL_SELFRING_GPA_APER_SIZE, 0); 268 269 WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW, 270 lower_32_bits(adev->doorbell.base)); 271 WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH, 272 upper_32_bits(adev->doorbell.base)); 273 } 274 275 WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, tmp); 276 } 277 278 static void nbif_v6_3_1_ih_doorbell_range(struct amdgpu_device *adev, 279 bool use_doorbell, int doorbell_index) 280 { 281 u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL); 282 283 if (use_doorbell) { 284 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 285 GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL, 286 S2A_DOORBELL_PORT1_ENABLE, 287 0x1); 288 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 289 GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL, 290 S2A_DOORBELL_PORT1_AWID, 291 0x0); 292 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 293 GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL, 294 S2A_DOORBELL_PORT1_RANGE_OFFSET, 295 doorbell_index); 296 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 297 GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL, 298 S2A_DOORBELL_PORT1_RANGE_SIZE, 299 2); 300 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 301 GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL, 302 S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE, 303 0x0); 304 } else 305 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 306 GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL, 307 S2A_DOORBELL_PORT1_RANGE_SIZE, 308 0); 309 310 if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 4)) { 311 WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL_nbif_4_10, ih_doorbell_range); 312 } else { 313 WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL, ih_doorbell_range); 314 } 315 } 316 317 static void nbif_v6_3_1_ih_control(struct amdgpu_device *adev) 318 { 319 u32 interrupt_cntl; 320 321 /* setup interrupt control */ 322 WREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL2, adev->dummy_page_addr >> 8); 323 324 interrupt_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL); 325 /* 326 * BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi 327 * BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN 328 */ 329 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL, 330 IH_DUMMY_RD_OVERRIDE, 0); 331 332 /* BIF_BX0_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */ 333 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL, 334 IH_REQ_NONSNOOP_EN, 0); 335 336 WREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL, interrupt_cntl); 337 } 338 339 static void 340 nbif_v6_3_1_update_medium_grain_clock_gating(struct amdgpu_device *adev, 341 bool enable) 342 { 343 } 344 345 static void 346 nbif_v6_3_1_update_medium_grain_light_sleep(struct amdgpu_device *adev, 347 bool enable) 348 { 349 } 350 351 static void 352 nbif_v6_3_1_get_clockgating_state(struct amdgpu_device *adev, 353 u64 *flags) 354 { 355 } 356 357 static u32 nbif_v6_3_1_get_hdp_flush_req_offset(struct amdgpu_device *adev) 358 { 359 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_REQ); 360 } 361 362 static u32 nbif_v6_3_1_get_hdp_flush_done_offset(struct amdgpu_device *adev) 363 { 364 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_DONE); 365 } 366 367 static u32 nbif_v6_3_1_get_pcie_index_offset(struct amdgpu_device *adev) 368 { 369 if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 4)) { 370 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_INDEX); 371 } 372 else { 373 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_INDEX); 374 } 375 } 376 377 static u32 nbif_v6_3_1_get_pcie_data_offset(struct amdgpu_device *adev) 378 { 379 if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 4)) 380 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_DATA); 381 else 382 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_DATA); 383 } 384 385 const struct nbio_hdp_flush_reg nbif_v6_3_1_hdp_flush_reg = { 386 .ref_and_mask_cp0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK, 387 .ref_and_mask_cp1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1_MASK, 388 .ref_and_mask_cp2 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2_MASK, 389 .ref_and_mask_cp3 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3_MASK, 390 .ref_and_mask_cp4 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4_MASK, 391 .ref_and_mask_cp5 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5_MASK, 392 .ref_and_mask_cp6 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6_MASK, 393 .ref_and_mask_cp7 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7_MASK, 394 .ref_and_mask_cp8 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8_MASK, 395 .ref_and_mask_cp9 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9_MASK, 396 .ref_and_mask_sdma0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK, 397 .ref_and_mask_sdma1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK, 398 }; 399 400 static void nbif_v6_3_1_init_registers(struct amdgpu_device *adev) 401 { 402 uint32_t data; 403 404 data = RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF2_STRAP2); 405 data &= ~RCC_DEV0_EPF2_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F2_MASK; 406 WREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF2_STRAP2, data); 407 } 408 409 static u32 nbif_v6_3_1_get_rom_offset(struct amdgpu_device *adev) 410 { 411 u32 data, rom_offset; 412 413 data = RREG32_SOC15(NBIO, 0, regREGS_ROM_OFFSET_CTRL); 414 rom_offset = REG_GET_FIELD(data, REGS_ROM_OFFSET_CTRL, ROM_OFFSET); 415 416 return rom_offset; 417 } 418 419 #ifdef CONFIG_PCIEASPM 420 static void nbif_v6_3_1_program_ltr(struct amdgpu_device *adev) 421 { 422 uint32_t def, data; 423 u16 devctl2; 424 425 def = RREG32_SOC15(NBIO, 0, regRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL); 426 data = 0x35EB; 427 data &= ~RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK; 428 data &= ~RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK; 429 if (def != data) 430 WREG32_SOC15(NBIO, 0, regRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL, data); 431 432 def = data = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP2); 433 data &= ~RCC_STRAP0_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK; 434 if (def != data) 435 WREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP2, data); 436 437 pcie_capability_read_word(adev->pdev, PCI_EXP_DEVCTL2, &devctl2); 438 439 if (adev->pdev->ltr_path == (devctl2 & PCI_EXP_DEVCTL2_LTR_EN)) 440 return; 441 442 if (adev->pdev->ltr_path) 443 pcie_capability_set_word(adev->pdev, PCI_EXP_DEVCTL2, PCI_EXP_DEVCTL2_LTR_EN); 444 else 445 pcie_capability_clear_word(adev->pdev, PCI_EXP_DEVCTL2, PCI_EXP_DEVCTL2_LTR_EN); 446 } 447 #endif 448 449 static void nbif_v6_3_1_program_aspm(struct amdgpu_device *adev) 450 { 451 #ifdef CONFIG_PCIEASPM 452 uint32_t def, data; 453 u16 devctl2, ltr; 454 455 def = data = RREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL); 456 data &= ~PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK; 457 data &= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK; 458 data |= PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK; 459 if (def != data) 460 WREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL, data); 461 462 def = data = RREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL7); 463 data |= PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN_MASK; 464 if (def != data) 465 WREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL7, data); 466 467 def = data = RREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL3); 468 data |= PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK; 469 if (def != data) 470 WREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL3, data); 471 472 def = data = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP3); 473 data &= ~RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK; 474 data &= ~RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK; 475 if (def != data) 476 WREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP3, data); 477 478 def = data = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP5); 479 data &= ~RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK; 480 if (def != data) 481 WREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP5, data); 482 483 pcie_capability_read_word(adev->pdev, PCI_EXP_DEVCTL2, &devctl2); 484 data = def = devctl2; 485 data &= ~PCI_EXP_DEVCTL2_LTR_EN; 486 if (def != data) 487 pcie_capability_set_word(adev->pdev, PCI_EXP_DEVCTL2, (u16)data); 488 489 ltr = pci_find_ext_capability(adev->pdev, PCI_EXT_CAP_ID_LTR); 490 491 if (ltr) { 492 pci_write_config_dword(adev->pdev, ltr + PCI_LTR_MAX_SNOOP_LAT, 0x10011001); 493 } 494 495 #if 0 496 /* regPSWUSP0_PCIE_LC_CNTL2 should be replace by PCIE_LC_CNTL2 or someone else ? */ 497 def = data = RREG32_SOC15(NBIO, 0, regPSWUSP0_PCIE_LC_CNTL2); 498 data |= PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK | 499 PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK; 500 data &= ~PSWUSP0_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK; 501 if (def != data) 502 WREG32_SOC15(NBIO, 0, regPSWUSP0_PCIE_LC_CNTL2, data); 503 #endif 504 def = data = RREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL4); 505 data |= PCIE_LC_CNTL4__LC_L1_POWERDOWN_MASK; 506 if (def != data) 507 WREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL4, data); 508 509 def = data = RREG32_SOC15(PCIE, 0, regPCIE_LC_RXRECOVER_RXSTANDBY_CNTL); 510 data |= PCIE_LC_RXRECOVER_RXSTANDBY_CNTL__LC_RX_L0S_STANDBY_EN_MASK; 511 if (def != data) 512 WREG32_SOC15(PCIE, 0, regPCIE_LC_RXRECOVER_RXSTANDBY_CNTL, data); 513 514 nbif_v6_3_1_program_ltr(adev); 515 516 def = data = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP3); 517 data |= 0x5DE0 << RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT; 518 data |= 0x0010 << RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT; 519 if (def != data) 520 WREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP3, data); 521 522 def = data = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP5); 523 data |= 0x0010 << RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT; 524 if (def != data) 525 WREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP5, data); 526 527 def = data = RREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL); 528 data |= 0x0 << PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT; 529 data |= 0x9 << PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT; 530 data &= ~PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK; 531 if (def != data) 532 WREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL, data); 533 534 def = data = RREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL3); 535 data &= ~PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK; 536 if (def != data) 537 WREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL3, data); 538 #endif 539 } 540 541 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE) 542 543 static void nbif_v6_3_1_set_reg_remap(struct amdgpu_device *adev) 544 { 545 if (!amdgpu_sriov_vf(adev) && (PAGE_SIZE <= 4096)) { 546 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; 547 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; 548 } else { 549 adev->rmmio_remap.reg_offset = SOC15_REG_OFFSET(NBIO, 0, 550 regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL) << 2; 551 adev->rmmio_remap.bus_addr = 0; 552 } 553 } 554 555 const struct amdgpu_nbio_funcs nbif_v6_3_1_funcs = { 556 .get_hdp_flush_req_offset = nbif_v6_3_1_get_hdp_flush_req_offset, 557 .get_hdp_flush_done_offset = nbif_v6_3_1_get_hdp_flush_done_offset, 558 .get_pcie_index_offset = nbif_v6_3_1_get_pcie_index_offset, 559 .get_pcie_data_offset = nbif_v6_3_1_get_pcie_data_offset, 560 .get_rev_id = nbif_v6_3_1_get_rev_id, 561 .mc_access_enable = nbif_v6_3_1_mc_access_enable, 562 .get_memsize = nbif_v6_3_1_get_memsize, 563 .sdma_doorbell_range = nbif_v6_3_1_sdma_doorbell_range, 564 .vcn_doorbell_range = nbif_v6_3_1_vcn_doorbell_range, 565 .vpe_doorbell_range = nbif_v6_3_1_vpe_doorbell_range, 566 .gc_doorbell_init = nbif_v6_3_1_gc_doorbell_init, 567 .enable_doorbell_aperture = nbif_v6_3_1_enable_doorbell_aperture, 568 .enable_doorbell_selfring_aperture = nbif_v6_3_1_enable_doorbell_selfring_aperture, 569 .ih_doorbell_range = nbif_v6_3_1_ih_doorbell_range, 570 .update_medium_grain_clock_gating = nbif_v6_3_1_update_medium_grain_clock_gating, 571 .update_medium_grain_light_sleep = nbif_v6_3_1_update_medium_grain_light_sleep, 572 .get_clockgating_state = nbif_v6_3_1_get_clockgating_state, 573 .ih_control = nbif_v6_3_1_ih_control, 574 .init_registers = nbif_v6_3_1_init_registers, 575 .remap_hdp_registers = nbif_v6_3_1_remap_hdp_registers, 576 .get_rom_offset = nbif_v6_3_1_get_rom_offset, 577 .program_aspm = nbif_v6_3_1_program_aspm, 578 .set_reg_remap = nbif_v6_3_1_set_reg_remap, 579 }; 580 581 582 static int nbif_v6_3_1_set_ras_err_event_athub_irq_state(struct amdgpu_device *adev, 583 struct amdgpu_irq_src *src, 584 unsigned type, 585 enum amdgpu_interrupt_state state) 586 { 587 /* The ras_controller_irq enablement should be done in psp bl when it 588 * tries to enable ras feature. Driver only need to set the correct interrupt 589 * vector for bare-metal and sriov use case respectively 590 */ 591 uint32_t bif_doorbell_int_cntl; 592 593 bif_doorbell_int_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_DOORBELL_INT_CNTL); 594 bif_doorbell_int_cntl = REG_SET_FIELD(bif_doorbell_int_cntl, 595 BIF_BX0_BIF_DOORBELL_INT_CNTL, 596 RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE, 597 (state == AMDGPU_IRQ_STATE_ENABLE) ? 0 : 1); 598 WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_DOORBELL_INT_CNTL, bif_doorbell_int_cntl); 599 600 return 0; 601 } 602 603 static int nbif_v6_3_1_process_err_event_athub_irq(struct amdgpu_device *adev, 604 struct amdgpu_irq_src *source, 605 struct amdgpu_iv_entry *entry) 606 { 607 /* By design, the ih cookie for err_event_athub_irq should be written 608 * to bif ring. since bif ring is not enabled, just leave process callback 609 * as a dummy one. 610 */ 611 return 0; 612 } 613 614 static const struct amdgpu_irq_src_funcs nbif_v6_3_1_ras_err_event_athub_irq_funcs = { 615 .set = nbif_v6_3_1_set_ras_err_event_athub_irq_state, 616 .process = nbif_v6_3_1_process_err_event_athub_irq, 617 }; 618 619 static void nbif_v6_3_1_handle_ras_err_event_athub_intr_no_bifring(struct amdgpu_device *adev) 620 { 621 uint32_t bif_doorbell_int_cntl; 622 623 bif_doorbell_int_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_DOORBELL_INT_CNTL); 624 if (REG_GET_FIELD(bif_doorbell_int_cntl, 625 BIF_BX0_BIF_DOORBELL_INT_CNTL, 626 RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS)) { 627 /* driver has to clear the interrupt status when bif ring is disabled */ 628 bif_doorbell_int_cntl = REG_SET_FIELD(bif_doorbell_int_cntl, 629 BIF_BX0_BIF_DOORBELL_INT_CNTL, 630 RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR, 1); 631 WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_DOORBELL_INT_CNTL, bif_doorbell_int_cntl); 632 amdgpu_ras_global_ras_isr(adev); 633 } 634 } 635 636 static int nbif_v6_3_1_init_ras_err_event_athub_interrupt(struct amdgpu_device *adev) 637 { 638 int r; 639 640 /* init the irq funcs */ 641 adev->nbio.ras_err_event_athub_irq.funcs = 642 &nbif_v6_3_1_ras_err_event_athub_irq_funcs; 643 adev->nbio.ras_err_event_athub_irq.num_types = 1; 644 645 /* register ras err event athub interrupt 646 * nbif v6_3_1 uses the same irq source as nbio v7_4 647 */ 648 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_BIF, 649 NBIF_7_4__SRCID__ERREVENT_ATHUB_INTERRUPT, 650 &adev->nbio.ras_err_event_athub_irq); 651 652 return r; 653 } 654 655 struct amdgpu_nbio_ras nbif_v6_3_1_ras = { 656 .handle_ras_err_event_athub_intr_no_bifring = 657 nbif_v6_3_1_handle_ras_err_event_athub_intr_no_bifring, 658 .init_ras_err_event_athub_interrupt = 659 nbif_v6_3_1_init_ras_err_event_athub_interrupt, 660 }; 661