1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "amdgpu.h" 24 #include "nbif_v6_3_1.h" 25 26 #include "nbif/nbif_6_3_1_offset.h" 27 #include "nbif/nbif_6_3_1_sh_mask.h" 28 #include "pcie/pcie_6_1_0_offset.h" 29 #include "pcie/pcie_6_1_0_sh_mask.h" 30 #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h" 31 #include <uapi/linux/kfd_ioctl.h> 32 33 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL_nbif_4_10 0x4f0aeb 34 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL_nbif_4_10_BASE_IDX 3 35 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL1_nbif_4_10 0x4f0aec 36 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL1_nbif_4_10_BASE_IDX 3 37 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL_nbif_4_10 0x4f0aed 38 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL_nbif_4_10_BASE_IDX 3 39 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL1_nbif_4_10 0x4f0aee 40 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL1_nbif_4_10_BASE_IDX 3 41 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL_nbif_4_10 0x4f0aef 42 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL_nbif_4_10_BASE_IDX 3 43 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1_nbif_4_10 0x4f0af0 44 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1_nbif_4_10_BASE_IDX 3 45 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL_nbif_4_10 0x4f0af1 46 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL_nbif_4_10_BASE_IDX 3 47 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL1_nbif_4_10 0x4f0af2 48 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL1_nbif_4_10_BASE_IDX 3 49 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL_nbif_4_10 0x4f0af3 50 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL_nbif_4_10_BASE_IDX 3 51 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL1_nbif_4_10 0x4f0af4 52 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL1_nbif_4_10_BASE_IDX 3 53 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL_nbif_4_10 0x4f0af5 54 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL_nbif_4_10_BASE_IDX 3 55 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL1_nbif_4_10 0x4f0af6 56 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL1_nbif_4_10_BASE_IDX 3 57 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_nbif_4_10 0x0021 58 #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_nbif_4_10_BASE_IDX 2 59 60 #define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_nbio_7_11_5 0x8e13 61 #define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_nbio_7_11_5_BASE_IDX 5 62 #define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_nbio_7_11_5 0x8e14 63 #define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_nbio_7_11_5_BASE_IDX 5 64 #define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL_nbio_7_11_5 0x8e15 65 #define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL_nbio_7_11_5_BASE_IDX 5 66 67 #define regBIF_BX1_REMAP_HDP_MEM_FLUSH_CNTL_nbio_7_11_5 0x012d 68 #define regBIF_BX1_REMAP_HDP_MEM_FLUSH_CNTL_nbio_7_11_5_BASE_IDX 2 69 #define regBIF_BX1_REMAP_HDP_REG_FLUSH_CNTL_nbio_7_11_5 0x012e 70 #define regBIF_BX1_REMAP_HDP_REG_FLUSH_CNTL_nbio_7_11_5_BASE_IDX 2 71 72 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP0_nbio_7_11_5 0x0021 73 #define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP0_nbio_7_11_5_BASE_IDX 2 74 75 #define regBIF_BX1_BIF_FB_EN_nbio_7_11_5 0x0100 76 #define regBIF_BX1_BIF_FB_EN_nbio_7_11_5_BASE_IDX 2 77 78 #define regBIF_BX1_INTERRUPT_CNTL_nbio_7_11_5 0x00f1 79 #define regBIF_BX1_INTERRUPT_CNTL_nbio_7_11_5_BASE_IDX 2 80 #define regBIF_BX1_INTERRUPT_CNTL2_nbio_7_11_5 0x00f2 81 #define regBIF_BX1_INTERRUPT_CNTL2_nbio_7_11_5_BASE_IDX 2 82 83 #define regBIF_BX_PF1_GPU_HDP_FLUSH_REQ_nbio_7_11_5 0x0106 84 #define regBIF_BX_PF1_GPU_HDP_FLUSH_REQ_nbio_7_11_5_BASE_IDX 2 85 #define regBIF_BX_PF1_GPU_HDP_FLUSH_DONE_nbio_7_11_5 0x0107 86 #define regBIF_BX_PF1_GPU_HDP_FLUSH_DONE_nbio_7_11_5_BASE_IDX 2 87 88 #define regBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL_nbio_7_11_5 0x00f7 89 #define regBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL_nbio_7_11_5_BASE_IDX 2 90 91 //BIF_BX1_BIF_FB_EN 92 #define BIF_BX1_BIF_FB_EN__FB_READ_EN__SHIFT_nbio_7_11_5 0x0 93 #define BIF_BX1_BIF_FB_EN__FB_WRITE_EN__SHIFT_nbio_7_11_5 0x1 94 #define BIF_BX1_BIF_FB_EN__FB_READ_EN_MASK_nbio_7_11_5 0x00000001L 95 #define BIF_BX1_BIF_FB_EN__FB_WRITE_EN_MASK_nbio_7_11_5 0x00000002L 96 97 static void nbif_v6_3_1_remap_hdp_registers(struct amdgpu_device *adev) 98 { 99 if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 5)) { 100 WREG32_SOC15(NBIO, 0, regBIF_BX1_REMAP_HDP_MEM_FLUSH_CNTL_nbio_7_11_5, 101 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL); 102 WREG32_SOC15(NBIO, 0, regBIF_BX1_REMAP_HDP_REG_FLUSH_CNTL_nbio_7_11_5, 103 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL); 104 } else { 105 WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL, 106 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL); 107 WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL, 108 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL); 109 } 110 } 111 112 static u32 nbif_v6_3_1_get_rev_id(struct amdgpu_device *adev) 113 { 114 u32 tmp; 115 116 if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 4)) 117 tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_nbif_4_10); 118 else if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 5)) 119 tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP1_RCC_DEV0_EPF0_STRAP0_nbio_7_11_5); 120 else 121 tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0); 122 123 tmp &= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK; 124 tmp >>= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT; 125 126 return tmp; 127 } 128 129 static void nbif_v6_3_1_mc_access_enable(struct amdgpu_device *adev, bool enable) 130 { 131 if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 5)) { 132 if (enable) 133 WREG32_SOC15(NBIO, 0, regBIF_BX1_BIF_FB_EN_nbio_7_11_5, 134 BIF_BX1_BIF_FB_EN__FB_READ_EN_MASK_nbio_7_11_5 | 135 BIF_BX1_BIF_FB_EN__FB_WRITE_EN_MASK_nbio_7_11_5); 136 else 137 WREG32_SOC15(NBIO, 0, regBIF_BX1_BIF_FB_EN_nbio_7_11_5, 0); 138 } else { 139 if (enable) 140 WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN, 141 BIF_BX0_BIF_FB_EN__FB_READ_EN_MASK | 142 BIF_BX0_BIF_FB_EN__FB_WRITE_EN_MASK); 143 else 144 WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN, 0); 145 } 146 } 147 148 static u32 nbif_v6_3_1_get_memsize(struct amdgpu_device *adev) 149 { 150 return RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE); 151 } 152 153 static void nbif_v6_3_1_sdma_doorbell_range(struct amdgpu_device *adev, 154 int instance, bool use_doorbell, 155 int doorbell_index, 156 int doorbell_size) 157 { 158 u32 doorbell_range; 159 if (instance == 0) { 160 if (amdgpu_ip_version(adev, NBIO_HWIP, 0) >= IP_VERSION(7, 11, 4)) 161 doorbell_range = RREG32_SOC15(NBIO, 0, 162 regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL_nbif_4_10); 163 else 164 doorbell_range = RREG32_SOC15(NBIO, 0, 165 regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL); 166 167 if (use_doorbell) { 168 doorbell_range = REG_SET_FIELD(doorbell_range, 169 GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL, 170 S2A_DOORBELL_PORT2_ENABLE, 171 0x1); 172 doorbell_range = REG_SET_FIELD(doorbell_range, 173 GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL, 174 S2A_DOORBELL_PORT2_AWID, 175 0xe); 176 doorbell_range = REG_SET_FIELD(doorbell_range, 177 GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL, 178 S2A_DOORBELL_PORT2_RANGE_OFFSET, 179 doorbell_index); 180 doorbell_range = REG_SET_FIELD(doorbell_range, 181 GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL, 182 S2A_DOORBELL_PORT2_RANGE_SIZE, 183 doorbell_size); 184 doorbell_range = REG_SET_FIELD(doorbell_range, 185 GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL, 186 S2A_DOORBELL_PORT2_AWADDR_31_28_VALUE, 187 0x3); 188 } else 189 doorbell_range = REG_SET_FIELD(doorbell_range, 190 GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL, 191 S2A_DOORBELL_PORT2_RANGE_SIZE, 192 0); 193 194 if (amdgpu_ip_version(adev, NBIO_HWIP, 0) >= IP_VERSION(7, 11, 4)) 195 WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL_nbif_4_10, doorbell_range); 196 else 197 WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL, doorbell_range); 198 } 199 } 200 201 static void nbif_v6_3_1_vcn_doorbell_range(struct amdgpu_device *adev, 202 bool use_doorbell, int doorbell_index, 203 int instance) 204 { 205 u32 doorbell_range; 206 207 if (instance) { 208 if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 4)) 209 return; 210 doorbell_range = RREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL); 211 } else { 212 doorbell_range = RREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL); 213 } 214 215 if (use_doorbell) { 216 doorbell_range = REG_SET_FIELD(doorbell_range, 217 GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL, 218 S2A_DOORBELL_PORT4_ENABLE, 219 0x1); 220 doorbell_range = REG_SET_FIELD(doorbell_range, 221 GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL, 222 S2A_DOORBELL_PORT4_AWID, 223 instance ? 0x7 : 0x4); 224 doorbell_range = REG_SET_FIELD(doorbell_range, 225 GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL, 226 S2A_DOORBELL_PORT4_RANGE_OFFSET, 227 doorbell_index); 228 doorbell_range = REG_SET_FIELD(doorbell_range, 229 GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL, 230 S2A_DOORBELL_PORT4_RANGE_SIZE, 231 8); 232 doorbell_range = REG_SET_FIELD(doorbell_range, 233 GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL, 234 S2A_DOORBELL_PORT4_AWADDR_31_28_VALUE, 235 instance ? 0x7 : 0x4); 236 } else 237 doorbell_range = REG_SET_FIELD(doorbell_range, 238 GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL, 239 S2A_DOORBELL_PORT4_RANGE_SIZE, 240 0); 241 242 if (amdgpu_ip_version(adev, NBIO_HWIP, 0) >= IP_VERSION(7, 11, 4)) 243 WREG32_SOC15(NBIO, 0, 244 regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL_nbif_4_10, 245 doorbell_range); 246 else 247 if (instance) 248 WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL, doorbell_range); 249 else 250 WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL, doorbell_range); 251 } 252 253 static void nbif_v6_3_1_vpe_doorbell_range(struct amdgpu_device *adev, 254 int instance, bool use_doorbell, 255 int doorbell_index, 256 int doorbell_size) 257 { 258 if (instance) 259 return; 260 261 u32 doorbell_range = RREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL); 262 263 if (use_doorbell) { 264 doorbell_range = REG_SET_FIELD(doorbell_range, 265 GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL, 266 S2A_DOORBELL_PORT5_ENABLE, 267 0x1); 268 doorbell_range = REG_SET_FIELD(doorbell_range, 269 GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL, 270 S2A_DOORBELL_PORT5_AWID, 271 0xf); 272 doorbell_range = REG_SET_FIELD(doorbell_range, 273 GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL, 274 S2A_DOORBELL_PORT5_RANGE_OFFSET, 275 doorbell_index); 276 doorbell_range = REG_SET_FIELD(doorbell_range, 277 GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL, 278 S2A_DOORBELL_PORT5_RANGE_SIZE, 279 doorbell_size); 280 doorbell_range = REG_SET_FIELD(doorbell_range, 281 GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL, 282 S2A_DOORBELL_PORT5_AWADDR_31_28_VALUE, 283 0xf); 284 } else { 285 doorbell_range = REG_SET_FIELD(doorbell_range, 286 GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL, 287 S2A_DOORBELL_PORT5_RANGE_SIZE, 288 0); 289 } 290 291 if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 4) || 292 amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 5)) { 293 WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL_nbif_4_10, doorbell_range); 294 } else { 295 WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL, doorbell_range); 296 } 297 298 } 299 300 static void nbif_v6_3_1_gc_doorbell_init(struct amdgpu_device *adev) 301 { 302 if (amdgpu_ip_version(adev, NBIO_HWIP, 0) >= IP_VERSION(7, 11, 4)) { 303 WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL_nbif_4_10, 0x30000007); 304 WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL_nbif_4_10, 0x3000000d); 305 } else { 306 WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL, 0x30000007); 307 WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL, 0x3000000d); 308 } 309 } 310 311 static void nbif_v6_3_1_enable_doorbell_aperture(struct amdgpu_device *adev, 312 bool enable) 313 { 314 WREG32_FIELD15_PREREG(NBIO, 0, RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN, 315 BIF_DOORBELL_APER_EN, enable ? 1 : 0); 316 } 317 318 static void 319 nbif_v6_3_1_enable_doorbell_selfring_aperture(struct amdgpu_device *adev, 320 bool enable) 321 { 322 u32 tmp = 0; 323 324 if (enable) { 325 tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, 326 DOORBELL_SELFRING_GPA_APER_EN, 1) | 327 REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, 328 DOORBELL_SELFRING_GPA_APER_MODE, 1) | 329 REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, 330 DOORBELL_SELFRING_GPA_APER_SIZE, 0); 331 332 WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW, 333 lower_32_bits(adev->doorbell.base)); 334 WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH, 335 upper_32_bits(adev->doorbell.base)); 336 } 337 338 WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, tmp); 339 } 340 341 static void nbif_v6_3_1_ih_doorbell_range(struct amdgpu_device *adev, 342 bool use_doorbell, int doorbell_index) 343 { 344 u32 ih_doorbell_range; 345 346 if (amdgpu_ip_version(adev, NBIO_HWIP, 0) >= IP_VERSION(7, 11, 4)) 347 ih_doorbell_range = RREG32_SOC15(NBIO, 0, 348 regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL_nbif_4_10); 349 else 350 ih_doorbell_range = RREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL); 351 352 if (use_doorbell) { 353 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 354 GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL, 355 S2A_DOORBELL_PORT1_ENABLE, 356 0x1); 357 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 358 GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL, 359 S2A_DOORBELL_PORT1_AWID, 360 0x0); 361 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 362 GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL, 363 S2A_DOORBELL_PORT1_RANGE_OFFSET, 364 doorbell_index); 365 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 366 GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL, 367 S2A_DOORBELL_PORT1_RANGE_SIZE, 368 2); 369 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 370 GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL, 371 S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE, 372 0x0); 373 } else 374 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 375 GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL, 376 S2A_DOORBELL_PORT1_RANGE_SIZE, 377 0); 378 379 if (amdgpu_ip_version(adev, NBIO_HWIP, 0) >= IP_VERSION(7, 11, 4)) 380 WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL_nbif_4_10, 381 ih_doorbell_range); 382 else 383 WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL, ih_doorbell_range); 384 } 385 386 static void nbif_v6_3_1_ih_control(struct amdgpu_device *adev) 387 { 388 u32 interrupt_cntl; 389 390 /* setup interrupt control */ 391 if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 5)) 392 WREG32_SOC15(NBIO, 0, regBIF_BX1_INTERRUPT_CNTL2_nbio_7_11_5, 393 adev->dummy_page_addr >> 8); 394 else 395 WREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL2, adev->dummy_page_addr >> 8); 396 397 interrupt_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX1_INTERRUPT_CNTL_nbio_7_11_5); 398 /* 399 * BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi 400 * BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN 401 */ 402 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL, 403 IH_DUMMY_RD_OVERRIDE, 0); 404 405 /* BIF_BX0_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */ 406 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL, 407 IH_REQ_NONSNOOP_EN, 0); 408 409 if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 5)) 410 WREG32_SOC15(NBIO, 0, regBIF_BX1_INTERRUPT_CNTL_nbio_7_11_5, interrupt_cntl); 411 else 412 WREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL, interrupt_cntl); 413 } 414 415 static void 416 nbif_v6_3_1_update_medium_grain_clock_gating(struct amdgpu_device *adev, 417 bool enable) 418 { 419 } 420 421 static void 422 nbif_v6_3_1_update_medium_grain_light_sleep(struct amdgpu_device *adev, 423 bool enable) 424 { 425 } 426 427 static void 428 nbif_v6_3_1_get_clockgating_state(struct amdgpu_device *adev, 429 u64 *flags) 430 { 431 } 432 433 static u32 nbif_v6_3_1_get_hdp_flush_req_offset(struct amdgpu_device *adev) 434 { 435 if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 5)) 436 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF1_GPU_HDP_FLUSH_REQ_nbio_7_11_5); 437 else 438 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_REQ); 439 } 440 441 static u32 nbif_v6_3_1_get_hdp_flush_done_offset(struct amdgpu_device *adev) 442 { 443 if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 5)) 444 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF1_GPU_HDP_FLUSH_DONE_nbio_7_11_5); 445 else 446 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_DONE); 447 } 448 449 static u32 nbif_v6_3_1_get_pcie_index_offset(struct amdgpu_device *adev) 450 { 451 if (amdgpu_ip_version(adev, NBIO_HWIP, 0) >= IP_VERSION(7, 11, 4)) 452 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_INDEX); 453 else 454 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_INDEX); 455 } 456 457 static u32 nbif_v6_3_1_get_pcie_data_offset(struct amdgpu_device *adev) 458 { 459 if (amdgpu_ip_version(adev, NBIO_HWIP, 0) >= IP_VERSION(7, 11, 4)) 460 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_DATA); 461 else 462 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_DATA); 463 } 464 465 const struct nbio_hdp_flush_reg nbif_v6_3_1_hdp_flush_reg = { 466 .ref_and_mask_cp0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK, 467 .ref_and_mask_cp1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1_MASK, 468 .ref_and_mask_cp2 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2_MASK, 469 .ref_and_mask_cp3 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3_MASK, 470 .ref_and_mask_cp4 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4_MASK, 471 .ref_and_mask_cp5 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5_MASK, 472 .ref_and_mask_cp6 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6_MASK, 473 .ref_and_mask_cp7 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7_MASK, 474 .ref_and_mask_cp8 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8_MASK, 475 .ref_and_mask_cp9 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9_MASK, 476 .ref_and_mask_sdma0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK, 477 .ref_and_mask_sdma1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK, 478 }; 479 480 static void nbif_v6_3_1_init_registers(struct amdgpu_device *adev) 481 { 482 uint32_t data; 483 484 data = RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF2_STRAP2); 485 data &= ~RCC_DEV0_EPF2_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F2_MASK; 486 WREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF2_STRAP2, data); 487 } 488 489 static u32 nbif_v6_3_1_get_rom_offset(struct amdgpu_device *adev) 490 { 491 u32 data, rom_offset; 492 493 data = RREG32_SOC15(NBIO, 0, regREGS_ROM_OFFSET_CTRL); 494 rom_offset = REG_GET_FIELD(data, REGS_ROM_OFFSET_CTRL, ROM_OFFSET); 495 496 return rom_offset; 497 } 498 499 #ifdef CONFIG_PCIEASPM 500 static void nbif_v6_3_1_program_ltr(struct amdgpu_device *adev) 501 { 502 uint32_t def, data; 503 504 def = RREG32_SOC15(NBIO, 0, regRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL); 505 data = 0x35EB; 506 data &= ~RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK; 507 data &= ~RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK; 508 if (def != data) 509 WREG32_SOC15(NBIO, 0, regRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL, data); 510 511 def = data = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP2); 512 data &= ~RCC_STRAP0_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK; 513 if (def != data) 514 WREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP2, data); 515 516 pcie_capability_set_word(adev->pdev, PCI_EXP_DEVCTL2, 517 PCI_EXP_DEVCTL2_LTR_EN); 518 } 519 #endif 520 521 static void nbif_v6_3_1_program_aspm(struct amdgpu_device *adev) 522 { 523 #ifdef CONFIG_PCIEASPM 524 uint32_t def, data; 525 u16 ltr; 526 527 def = data = RREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL); 528 data &= ~PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK; 529 data &= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK; 530 data |= PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK; 531 if (def != data) 532 WREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL, data); 533 534 def = data = RREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL7); 535 data |= PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN_MASK; 536 if (def != data) 537 WREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL7, data); 538 539 def = data = RREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL3); 540 data |= PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK; 541 if (def != data) 542 WREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL3, data); 543 544 def = data = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP3); 545 data &= ~RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK; 546 data &= ~RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK; 547 if (def != data) 548 WREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP3, data); 549 550 def = data = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP5); 551 data &= ~RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK; 552 if (def != data) 553 WREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP5, data); 554 555 pcie_capability_clear_word(adev->pdev, PCI_EXP_DEVCTL2, 556 PCI_EXP_DEVCTL2_LTR_EN); 557 558 ltr = pci_find_ext_capability(adev->pdev, PCI_EXT_CAP_ID_LTR); 559 560 if (ltr) { 561 pci_write_config_dword(adev->pdev, ltr + PCI_LTR_MAX_SNOOP_LAT, 0x10011001); 562 } 563 564 def = data = RREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL2); 565 data |= PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK | 566 PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK; 567 data &= ~PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK; 568 if (def != data) 569 WREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL2, data); 570 571 def = data = RREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL4); 572 data |= PCIE_LC_CNTL4__LC_L1_POWERDOWN_MASK; 573 if (def != data) 574 WREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL4, data); 575 576 def = data = RREG32_SOC15(PCIE, 0, regPCIE_LC_RXRECOVER_RXSTANDBY_CNTL); 577 data |= PCIE_LC_RXRECOVER_RXSTANDBY_CNTL__LC_RX_L0S_STANDBY_EN_MASK; 578 if (def != data) 579 WREG32_SOC15(PCIE, 0, regPCIE_LC_RXRECOVER_RXSTANDBY_CNTL, data); 580 581 /* 582 * Do not enable endpoint LTR unless the Root Complex and every 583 * upstream switch support it. 584 */ 585 if (adev->pdev->ltr_path) 586 nbif_v6_3_1_program_ltr(adev); 587 588 def = data = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP3); 589 data |= 0x5DE0 << RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT; 590 data |= 0x0010 << RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT; 591 if (def != data) 592 WREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP3, data); 593 594 def = data = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP5); 595 data |= 0x0010 << RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT; 596 if (def != data) 597 WREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP5, data); 598 599 def = data = RREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL); 600 data |= 0x0 << PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT; 601 data |= 0x9 << PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT; 602 data &= ~PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK; 603 if (def != data) 604 WREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL, data); 605 606 def = data = RREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL3); 607 data &= ~PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK; 608 if (def != data) 609 WREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL3, data); 610 #endif 611 } 612 613 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE) 614 615 static void nbif_v6_3_1_set_reg_remap(struct amdgpu_device *adev) 616 { 617 if (!amdgpu_sriov_vf(adev) && (PAGE_SIZE <= 4096)) { 618 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; 619 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; 620 } else { 621 if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 5)) 622 adev->rmmio_remap.reg_offset = SOC15_REG_OFFSET(NBIO, 0, 623 regBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL_nbio_7_11_5) << 2; 624 else 625 adev->rmmio_remap.reg_offset = SOC15_REG_OFFSET(NBIO, 0, 626 regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL) << 2; 627 adev->rmmio_remap.bus_addr = 0; 628 } 629 } 630 631 const struct amdgpu_nbio_funcs nbif_v6_3_1_funcs = { 632 .get_hdp_flush_req_offset = nbif_v6_3_1_get_hdp_flush_req_offset, 633 .get_hdp_flush_done_offset = nbif_v6_3_1_get_hdp_flush_done_offset, 634 .get_pcie_index_offset = nbif_v6_3_1_get_pcie_index_offset, 635 .get_pcie_data_offset = nbif_v6_3_1_get_pcie_data_offset, 636 .get_rev_id = nbif_v6_3_1_get_rev_id, 637 .mc_access_enable = nbif_v6_3_1_mc_access_enable, 638 .get_memsize = nbif_v6_3_1_get_memsize, 639 .sdma_doorbell_range = nbif_v6_3_1_sdma_doorbell_range, 640 .vcn_doorbell_range = nbif_v6_3_1_vcn_doorbell_range, 641 .vpe_doorbell_range = nbif_v6_3_1_vpe_doorbell_range, 642 .gc_doorbell_init = nbif_v6_3_1_gc_doorbell_init, 643 .enable_doorbell_aperture = nbif_v6_3_1_enable_doorbell_aperture, 644 .enable_doorbell_selfring_aperture = nbif_v6_3_1_enable_doorbell_selfring_aperture, 645 .ih_doorbell_range = nbif_v6_3_1_ih_doorbell_range, 646 .update_medium_grain_clock_gating = nbif_v6_3_1_update_medium_grain_clock_gating, 647 .update_medium_grain_light_sleep = nbif_v6_3_1_update_medium_grain_light_sleep, 648 .get_clockgating_state = nbif_v6_3_1_get_clockgating_state, 649 .ih_control = nbif_v6_3_1_ih_control, 650 .init_registers = nbif_v6_3_1_init_registers, 651 .remap_hdp_registers = nbif_v6_3_1_remap_hdp_registers, 652 .get_rom_offset = nbif_v6_3_1_get_rom_offset, 653 .program_aspm = nbif_v6_3_1_program_aspm, 654 .set_reg_remap = nbif_v6_3_1_set_reg_remap, 655 }; 656 657 658 static int nbif_v6_3_1_set_ras_err_event_athub_irq_state(struct amdgpu_device *adev, 659 struct amdgpu_irq_src *src, 660 unsigned type, 661 enum amdgpu_interrupt_state state) 662 { 663 /* The ras_controller_irq enablement should be done in psp bl when it 664 * tries to enable ras feature. Driver only need to set the correct interrupt 665 * vector for bare-metal and sriov use case respectively 666 */ 667 uint32_t bif_doorbell_int_cntl; 668 669 bif_doorbell_int_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_DOORBELL_INT_CNTL); 670 bif_doorbell_int_cntl = REG_SET_FIELD(bif_doorbell_int_cntl, 671 BIF_BX0_BIF_DOORBELL_INT_CNTL, 672 RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE, 673 (state == AMDGPU_IRQ_STATE_ENABLE) ? 0 : 1); 674 WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_DOORBELL_INT_CNTL, bif_doorbell_int_cntl); 675 676 return 0; 677 } 678 679 static int nbif_v6_3_1_process_err_event_athub_irq(struct amdgpu_device *adev, 680 struct amdgpu_irq_src *source, 681 struct amdgpu_iv_entry *entry) 682 { 683 /* By design, the ih cookie for err_event_athub_irq should be written 684 * to bif ring. since bif ring is not enabled, just leave process callback 685 * as a dummy one. 686 */ 687 return 0; 688 } 689 690 static const struct amdgpu_irq_src_funcs nbif_v6_3_1_ras_err_event_athub_irq_funcs = { 691 .set = nbif_v6_3_1_set_ras_err_event_athub_irq_state, 692 .process = nbif_v6_3_1_process_err_event_athub_irq, 693 }; 694 695 static void nbif_v6_3_1_handle_ras_err_event_athub_intr_no_bifring(struct amdgpu_device *adev) 696 { 697 uint32_t bif_doorbell_int_cntl; 698 699 bif_doorbell_int_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_DOORBELL_INT_CNTL); 700 if (REG_GET_FIELD(bif_doorbell_int_cntl, 701 BIF_BX0_BIF_DOORBELL_INT_CNTL, 702 RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS)) { 703 /* driver has to clear the interrupt status when bif ring is disabled */ 704 bif_doorbell_int_cntl = REG_SET_FIELD(bif_doorbell_int_cntl, 705 BIF_BX0_BIF_DOORBELL_INT_CNTL, 706 RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR, 1); 707 WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_DOORBELL_INT_CNTL, bif_doorbell_int_cntl); 708 amdgpu_ras_global_ras_isr(adev); 709 } 710 } 711 712 static int nbif_v6_3_1_init_ras_err_event_athub_interrupt(struct amdgpu_device *adev) 713 { 714 int r; 715 716 /* init the irq funcs */ 717 adev->nbio.ras_err_event_athub_irq.funcs = 718 &nbif_v6_3_1_ras_err_event_athub_irq_funcs; 719 adev->nbio.ras_err_event_athub_irq.num_types = 1; 720 721 /* register ras err event athub interrupt 722 * nbif v6_3_1 uses the same irq source as nbio v7_4 723 */ 724 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_BIF, 725 NBIF_7_4__SRCID__ERREVENT_ATHUB_INTERRUPT, 726 &adev->nbio.ras_err_event_athub_irq); 727 728 return r; 729 } 730 731 struct amdgpu_nbio_ras nbif_v6_3_1_ras = { 732 .handle_ras_err_event_athub_intr_no_bifring = 733 nbif_v6_3_1_handle_ras_err_event_athub_intr_no_bifring, 734 .init_ras_err_event_athub_interrupt = 735 nbif_v6_3_1_init_ras_err_event_athub_interrupt, 736 }; 737