1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "amdgpu.h" 24 #include "amdgpu_atombios.h" 25 #include "nbif_v6_3_1.h" 26 27 #include "nbif/nbif_6_3_1_offset.h" 28 #include "nbif/nbif_6_3_1_sh_mask.h" 29 #include "pcie/pcie_6_1_0_offset.h" 30 #include "pcie/pcie_6_1_0_sh_mask.h" 31 #include <uapi/linux/kfd_ioctl.h> 32 33 static void nbif_v6_3_1_remap_hdp_registers(struct amdgpu_device *adev) 34 { 35 WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL, 36 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL); 37 WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL, 38 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL); 39 } 40 41 static u32 nbif_v6_3_1_get_rev_id(struct amdgpu_device *adev) 42 { 43 u32 tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0); 44 45 tmp &= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK; 46 tmp >>= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT; 47 48 return tmp; 49 } 50 51 static void nbif_v6_3_1_mc_access_enable(struct amdgpu_device *adev, bool enable) 52 { 53 if (enable) 54 WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN, 55 BIF_BX0_BIF_FB_EN__FB_READ_EN_MASK | 56 BIF_BX0_BIF_FB_EN__FB_WRITE_EN_MASK); 57 else 58 WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN, 0); 59 } 60 61 static u32 nbif_v6_3_1_get_memsize(struct amdgpu_device *adev) 62 { 63 return RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE); 64 } 65 66 static void nbif_v6_3_1_sdma_doorbell_range(struct amdgpu_device *adev, 67 int instance, bool use_doorbell, 68 int doorbell_index, 69 int doorbell_size) 70 { 71 if (instance == 0) { 72 u32 doorbell_range = RREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL); 73 74 if (use_doorbell) { 75 doorbell_range = REG_SET_FIELD(doorbell_range, 76 GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL, 77 S2A_DOORBELL_PORT2_ENABLE, 78 0x1); 79 doorbell_range = REG_SET_FIELD(doorbell_range, 80 GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL, 81 S2A_DOORBELL_PORT2_AWID, 82 0xe); 83 doorbell_range = REG_SET_FIELD(doorbell_range, 84 GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL, 85 S2A_DOORBELL_PORT2_RANGE_OFFSET, 86 doorbell_index); 87 doorbell_range = REG_SET_FIELD(doorbell_range, 88 GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL, 89 S2A_DOORBELL_PORT2_RANGE_SIZE, 90 doorbell_size); 91 doorbell_range = REG_SET_FIELD(doorbell_range, 92 GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL, 93 S2A_DOORBELL_PORT2_AWADDR_31_28_VALUE, 94 0x3); 95 } else 96 doorbell_range = REG_SET_FIELD(doorbell_range, 97 GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL, 98 S2A_DOORBELL_PORT2_RANGE_SIZE, 99 0); 100 101 WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL, doorbell_range); 102 } 103 } 104 105 static void nbif_v6_3_1_vcn_doorbell_range(struct amdgpu_device *adev, 106 bool use_doorbell, int doorbell_index, 107 int instance) 108 { 109 u32 doorbell_range; 110 111 if (instance) 112 doorbell_range = RREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL); 113 else 114 doorbell_range = RREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL); 115 116 if (use_doorbell) { 117 doorbell_range = REG_SET_FIELD(doorbell_range, 118 GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL, 119 S2A_DOORBELL_PORT4_ENABLE, 120 0x1); 121 doorbell_range = REG_SET_FIELD(doorbell_range, 122 GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL, 123 S2A_DOORBELL_PORT4_AWID, 124 instance ? 0x7 : 0x4); 125 doorbell_range = REG_SET_FIELD(doorbell_range, 126 GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL, 127 S2A_DOORBELL_PORT4_RANGE_OFFSET, 128 doorbell_index); 129 doorbell_range = REG_SET_FIELD(doorbell_range, 130 GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL, 131 S2A_DOORBELL_PORT4_RANGE_SIZE, 132 8); 133 doorbell_range = REG_SET_FIELD(doorbell_range, 134 GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL, 135 S2A_DOORBELL_PORT4_AWADDR_31_28_VALUE, 136 instance ? 0x7 : 0x4); 137 } else 138 doorbell_range = REG_SET_FIELD(doorbell_range, 139 GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL, 140 S2A_DOORBELL_PORT4_RANGE_SIZE, 141 0); 142 143 if (instance) 144 WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL, doorbell_range); 145 else 146 WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL, doorbell_range); 147 } 148 149 static void nbif_v6_3_1_gc_doorbell_init(struct amdgpu_device *adev) 150 { 151 WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL, 0x30000007); 152 WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL, 0x3000000d); 153 } 154 155 static void nbif_v6_3_1_enable_doorbell_aperture(struct amdgpu_device *adev, 156 bool enable) 157 { 158 WREG32_FIELD15_PREREG(NBIO, 0, RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN, 159 BIF_DOORBELL_APER_EN, enable ? 1 : 0); 160 } 161 162 static void 163 nbif_v6_3_1_enable_doorbell_selfring_aperture(struct amdgpu_device *adev, 164 bool enable) 165 { 166 u32 tmp = 0; 167 168 if (enable) { 169 tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, 170 DOORBELL_SELFRING_GPA_APER_EN, 1) | 171 REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, 172 DOORBELL_SELFRING_GPA_APER_MODE, 1) | 173 REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, 174 DOORBELL_SELFRING_GPA_APER_SIZE, 0); 175 176 WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW, 177 lower_32_bits(adev->doorbell.base)); 178 WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH, 179 upper_32_bits(adev->doorbell.base)); 180 } 181 182 WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, tmp); 183 } 184 185 static void nbif_v6_3_1_ih_doorbell_range(struct amdgpu_device *adev, 186 bool use_doorbell, int doorbell_index) 187 { 188 u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL); 189 190 if (use_doorbell) { 191 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 192 GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL, 193 S2A_DOORBELL_PORT1_ENABLE, 194 0x1); 195 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 196 GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL, 197 S2A_DOORBELL_PORT1_AWID, 198 0x0); 199 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 200 GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL, 201 S2A_DOORBELL_PORT1_RANGE_OFFSET, 202 doorbell_index); 203 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 204 GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL, 205 S2A_DOORBELL_PORT1_RANGE_SIZE, 206 2); 207 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 208 GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL, 209 S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE, 210 0x0); 211 } else 212 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 213 GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL, 214 S2A_DOORBELL_PORT1_RANGE_SIZE, 215 0); 216 217 WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL, ih_doorbell_range); 218 } 219 220 static void nbif_v6_3_1_ih_control(struct amdgpu_device *adev) 221 { 222 u32 interrupt_cntl; 223 224 /* setup interrupt control */ 225 WREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL2, adev->dummy_page_addr >> 8); 226 227 interrupt_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL); 228 /* 229 * BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi 230 * BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN 231 */ 232 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL, 233 IH_DUMMY_RD_OVERRIDE, 0); 234 235 /* BIF_BX0_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */ 236 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL, 237 IH_REQ_NONSNOOP_EN, 0); 238 239 WREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL, interrupt_cntl); 240 } 241 242 static void 243 nbif_v6_3_1_update_medium_grain_clock_gating(struct amdgpu_device *adev, 244 bool enable) 245 { 246 } 247 248 static void 249 nbif_v6_3_1_update_medium_grain_light_sleep(struct amdgpu_device *adev, 250 bool enable) 251 { 252 } 253 254 static void 255 nbif_v6_3_1_get_clockgating_state(struct amdgpu_device *adev, 256 u64 *flags) 257 { 258 } 259 260 static u32 nbif_v6_3_1_get_hdp_flush_req_offset(struct amdgpu_device *adev) 261 { 262 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_REQ); 263 } 264 265 static u32 nbif_v6_3_1_get_hdp_flush_done_offset(struct amdgpu_device *adev) 266 { 267 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_DONE); 268 } 269 270 static u32 nbif_v6_3_1_get_pcie_index_offset(struct amdgpu_device *adev) 271 { 272 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_INDEX); 273 } 274 275 static u32 nbif_v6_3_1_get_pcie_data_offset(struct amdgpu_device *adev) 276 { 277 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_DATA); 278 } 279 280 const struct nbio_hdp_flush_reg nbif_v6_3_1_hdp_flush_reg = { 281 .ref_and_mask_cp0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK, 282 .ref_and_mask_cp1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1_MASK, 283 .ref_and_mask_cp2 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2_MASK, 284 .ref_and_mask_cp3 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3_MASK, 285 .ref_and_mask_cp4 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4_MASK, 286 .ref_and_mask_cp5 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5_MASK, 287 .ref_and_mask_cp6 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6_MASK, 288 .ref_and_mask_cp7 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7_MASK, 289 .ref_and_mask_cp8 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8_MASK, 290 .ref_and_mask_cp9 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9_MASK, 291 .ref_and_mask_sdma0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK, 292 .ref_and_mask_sdma1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK, 293 }; 294 295 static void nbif_v6_3_1_init_registers(struct amdgpu_device *adev) 296 { 297 uint32_t data; 298 299 data = RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF2_STRAP2); 300 data &= ~RCC_DEV0_EPF2_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F2_MASK; 301 WREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF2_STRAP2, data); 302 } 303 304 static u32 nbif_v6_3_1_get_rom_offset(struct amdgpu_device *adev) 305 { 306 u32 data, rom_offset; 307 308 data = RREG32_SOC15(NBIO, 0, regREGS_ROM_OFFSET_CTRL); 309 rom_offset = REG_GET_FIELD(data, REGS_ROM_OFFSET_CTRL, ROM_OFFSET); 310 311 return rom_offset; 312 } 313 314 #ifdef CONFIG_PCIEASPM 315 static void nbif_v6_3_1_program_ltr(struct amdgpu_device *adev) 316 { 317 uint32_t def, data; 318 u16 devctl2; 319 320 def = RREG32_SOC15(NBIO, 0, regRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL); 321 data = 0x35EB; 322 data &= ~RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK; 323 data &= ~RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK; 324 if (def != data) 325 WREG32_SOC15(NBIO, 0, regRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL, data); 326 327 def = data = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP2); 328 data &= ~RCC_STRAP0_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK; 329 if (def != data) 330 WREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP2, data); 331 332 pcie_capability_read_word(adev->pdev, PCI_EXP_DEVCTL2, &devctl2); 333 334 if (adev->pdev->ltr_path == (devctl2 & PCI_EXP_DEVCTL2_LTR_EN)) 335 return; 336 337 if (adev->pdev->ltr_path) 338 pcie_capability_set_word(adev->pdev, PCI_EXP_DEVCTL2, PCI_EXP_DEVCTL2_LTR_EN); 339 else 340 pcie_capability_clear_word(adev->pdev, PCI_EXP_DEVCTL2, PCI_EXP_DEVCTL2_LTR_EN); 341 } 342 #endif 343 344 static void nbif_v6_3_1_program_aspm(struct amdgpu_device *adev) 345 { 346 #ifdef CONFIG_PCIEASPM 347 uint32_t def, data; 348 349 def = data = RREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL); 350 data &= ~PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK; 351 data &= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK; 352 data |= PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK; 353 if (def != data) 354 WREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL, data); 355 356 def = data = RREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL7); 357 data |= PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN_MASK; 358 if (def != data) 359 WREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL7, data); 360 361 def = data = RREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL3); 362 data |= PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK; 363 if (def != data) 364 WREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL3, data); 365 366 def = data = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP3); 367 data &= ~RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK; 368 data &= ~RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK; 369 if (def != data) 370 WREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP3, data); 371 372 def = data = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP5); 373 data &= ~RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK; 374 if (def != data) 375 WREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP5, data); 376 377 def = data = RREG32_SOC15(NBIO, 0, regBIF_CFG_DEV0_EPF0_DEVICE_CNTL2); 378 data &= ~BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK; 379 if (def != data) 380 WREG32_SOC15(NBIO, 0, regBIF_CFG_DEV0_EPF0_DEVICE_CNTL2, data); 381 382 WREG32_SOC15(NBIO, 0, regBIF_CFG_DEV0_EPF0_PCIE_LTR_CAP, 0x10011001); 383 384 #if 0 385 /* regPSWUSP0_PCIE_LC_CNTL2 should be replace by PCIE_LC_CNTL2 or someone else ? */ 386 def = data = RREG32_SOC15(NBIO, 0, regPSWUSP0_PCIE_LC_CNTL2); 387 data |= PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK | 388 PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK; 389 data &= ~PSWUSP0_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK; 390 if (def != data) 391 WREG32_SOC15(NBIO, 0, regPSWUSP0_PCIE_LC_CNTL2, data); 392 #endif 393 def = data = RREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL4); 394 data |= PCIE_LC_CNTL4__LC_L1_POWERDOWN_MASK; 395 if (def != data) 396 WREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL4, data); 397 398 def = data = RREG32_SOC15(PCIE, 0, regPCIE_LC_RXRECOVER_RXSTANDBY_CNTL); 399 data |= PCIE_LC_RXRECOVER_RXSTANDBY_CNTL__LC_RX_L0S_STANDBY_EN_MASK; 400 if (def != data) 401 WREG32_SOC15(PCIE, 0, regPCIE_LC_RXRECOVER_RXSTANDBY_CNTL, data); 402 403 nbif_v6_3_1_program_ltr(adev); 404 405 def = data = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP3); 406 data |= 0x5DE0 << RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT; 407 data |= 0x0010 << RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT; 408 if (def != data) 409 WREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP3, data); 410 411 def = data = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP5); 412 data |= 0x0010 << RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT; 413 if (def != data) 414 WREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP5, data); 415 416 def = data = RREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL); 417 data |= 0x0 << PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT; 418 data |= 0x9 << PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT; 419 data &= ~PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK; 420 if (def != data) 421 WREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL, data); 422 423 def = data = RREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL3); 424 data &= ~PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK; 425 if (def != data) 426 WREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL3, data); 427 #endif 428 } 429 430 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE) 431 432 static void nbif_v6_3_1_set_reg_remap(struct amdgpu_device *adev) 433 { 434 if (!amdgpu_sriov_vf(adev) && (PAGE_SIZE <= 4096)) { 435 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; 436 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; 437 } else { 438 adev->rmmio_remap.reg_offset = SOC15_REG_OFFSET(NBIO, 0, 439 regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL) << 2; 440 adev->rmmio_remap.bus_addr = 0; 441 } 442 } 443 444 const struct amdgpu_nbio_funcs nbif_v6_3_1_funcs = { 445 .get_hdp_flush_req_offset = nbif_v6_3_1_get_hdp_flush_req_offset, 446 .get_hdp_flush_done_offset = nbif_v6_3_1_get_hdp_flush_done_offset, 447 .get_pcie_index_offset = nbif_v6_3_1_get_pcie_index_offset, 448 .get_pcie_data_offset = nbif_v6_3_1_get_pcie_data_offset, 449 .get_rev_id = nbif_v6_3_1_get_rev_id, 450 .mc_access_enable = nbif_v6_3_1_mc_access_enable, 451 .get_memsize = nbif_v6_3_1_get_memsize, 452 .sdma_doorbell_range = nbif_v6_3_1_sdma_doorbell_range, 453 .vcn_doorbell_range = nbif_v6_3_1_vcn_doorbell_range, 454 .gc_doorbell_init = nbif_v6_3_1_gc_doorbell_init, 455 .enable_doorbell_aperture = nbif_v6_3_1_enable_doorbell_aperture, 456 .enable_doorbell_selfring_aperture = nbif_v6_3_1_enable_doorbell_selfring_aperture, 457 .ih_doorbell_range = nbif_v6_3_1_ih_doorbell_range, 458 .update_medium_grain_clock_gating = nbif_v6_3_1_update_medium_grain_clock_gating, 459 .update_medium_grain_light_sleep = nbif_v6_3_1_update_medium_grain_light_sleep, 460 .get_clockgating_state = nbif_v6_3_1_get_clockgating_state, 461 .ih_control = nbif_v6_3_1_ih_control, 462 .init_registers = nbif_v6_3_1_init_registers, 463 .remap_hdp_registers = nbif_v6_3_1_remap_hdp_registers, 464 .get_rom_offset = nbif_v6_3_1_get_rom_offset, 465 .program_aspm = nbif_v6_3_1_program_aspm, 466 .set_reg_remap = nbif_v6_3_1_set_reg_remap, 467 }; 468 469 470 static void nbif_v6_3_1_sriov_ih_doorbell_range(struct amdgpu_device *adev, 471 bool use_doorbell, int doorbell_index) 472 { 473 } 474 475 static void nbif_v6_3_1_sriov_sdma_doorbell_range(struct amdgpu_device *adev, 476 int instance, bool use_doorbell, 477 int doorbell_index, 478 int doorbell_size) 479 { 480 } 481 482 static void nbif_v6_3_1_sriov_vcn_doorbell_range(struct amdgpu_device *adev, 483 bool use_doorbell, 484 int doorbell_index, int instance) 485 { 486 } 487 488 static void nbif_v6_3_1_sriov_gc_doorbell_init(struct amdgpu_device *adev) 489 { 490 } 491 492 const struct amdgpu_nbio_funcs nbif_v6_3_1_sriov_funcs = { 493 .get_hdp_flush_req_offset = nbif_v6_3_1_get_hdp_flush_req_offset, 494 .get_hdp_flush_done_offset = nbif_v6_3_1_get_hdp_flush_done_offset, 495 .get_pcie_index_offset = nbif_v6_3_1_get_pcie_index_offset, 496 .get_pcie_data_offset = nbif_v6_3_1_get_pcie_data_offset, 497 .get_rev_id = nbif_v6_3_1_get_rev_id, 498 .mc_access_enable = nbif_v6_3_1_mc_access_enable, 499 .get_memsize = nbif_v6_3_1_get_memsize, 500 .sdma_doorbell_range = nbif_v6_3_1_sriov_sdma_doorbell_range, 501 .vcn_doorbell_range = nbif_v6_3_1_sriov_vcn_doorbell_range, 502 .gc_doorbell_init = nbif_v6_3_1_sriov_gc_doorbell_init, 503 .enable_doorbell_aperture = nbif_v6_3_1_enable_doorbell_aperture, 504 .enable_doorbell_selfring_aperture = nbif_v6_3_1_enable_doorbell_selfring_aperture, 505 .ih_doorbell_range = nbif_v6_3_1_sriov_ih_doorbell_range, 506 .update_medium_grain_clock_gating = nbif_v6_3_1_update_medium_grain_clock_gating, 507 .update_medium_grain_light_sleep = nbif_v6_3_1_update_medium_grain_light_sleep, 508 .get_clockgating_state = nbif_v6_3_1_get_clockgating_state, 509 .ih_control = nbif_v6_3_1_ih_control, 510 .init_registers = nbif_v6_3_1_init_registers, 511 .remap_hdp_registers = nbif_v6_3_1_remap_hdp_registers, 512 .get_rom_offset = nbif_v6_3_1_get_rom_offset, 513 .set_reg_remap = nbif_v6_3_1_set_reg_remap, 514 }; 515