1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "amdgpu.h" 24 #include "nbif_v6_3_1.h" 25 26 #include "nbif/nbif_6_3_1_offset.h" 27 #include "nbif/nbif_6_3_1_sh_mask.h" 28 #include "pcie/pcie_6_1_0_offset.h" 29 #include "pcie/pcie_6_1_0_sh_mask.h" 30 #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h" 31 #include <uapi/linux/kfd_ioctl.h> 32 33 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL_nbif_4_10 0x4f0aeb 34 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL_nbif_4_10_BASE_IDX 3 35 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL1_nbif_4_10 0x4f0aec 36 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL1_nbif_4_10_BASE_IDX 3 37 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL_nbif_4_10 0x4f0aed 38 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL_nbif_4_10_BASE_IDX 3 39 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL1_nbif_4_10 0x4f0aee 40 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL1_nbif_4_10_BASE_IDX 3 41 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL_nbif_4_10 0x4f0aef 42 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL_nbif_4_10_BASE_IDX 3 43 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1_nbif_4_10 0x4f0af0 44 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1_nbif_4_10_BASE_IDX 3 45 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL_nbif_4_10 0x4f0af1 46 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL_nbif_4_10_BASE_IDX 3 47 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL1_nbif_4_10 0x4f0af2 48 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL1_nbif_4_10_BASE_IDX 3 49 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL_nbif_4_10 0x4f0af3 50 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL_nbif_4_10_BASE_IDX 3 51 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL1_nbif_4_10 0x4f0af4 52 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL1_nbif_4_10_BASE_IDX 3 53 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL_nbif_4_10 0x4f0af5 54 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL_nbif_4_10_BASE_IDX 3 55 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL1_nbif_4_10 0x4f0af6 56 #define regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL1_nbif_4_10_BASE_IDX 3 57 58 static void nbif_v6_3_1_remap_hdp_registers(struct amdgpu_device *adev) 59 { 60 WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL, 61 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL); 62 WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL, 63 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL); 64 } 65 66 static u32 nbif_v6_3_1_get_rev_id(struct amdgpu_device *adev) 67 { 68 u32 tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0); 69 70 tmp &= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK; 71 tmp >>= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT; 72 73 return tmp; 74 } 75 76 static void nbif_v6_3_1_mc_access_enable(struct amdgpu_device *adev, bool enable) 77 { 78 if (enable) 79 WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN, 80 BIF_BX0_BIF_FB_EN__FB_READ_EN_MASK | 81 BIF_BX0_BIF_FB_EN__FB_WRITE_EN_MASK); 82 else 83 WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN, 0); 84 } 85 86 static u32 nbif_v6_3_1_get_memsize(struct amdgpu_device *adev) 87 { 88 return RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE); 89 } 90 91 static void nbif_v6_3_1_sdma_doorbell_range(struct amdgpu_device *adev, 92 int instance, bool use_doorbell, 93 int doorbell_index, 94 int doorbell_size) 95 { 96 if (instance == 0) { 97 u32 doorbell_range = RREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL); 98 99 if (use_doorbell) { 100 doorbell_range = REG_SET_FIELD(doorbell_range, 101 GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL, 102 S2A_DOORBELL_PORT2_ENABLE, 103 0x1); 104 doorbell_range = REG_SET_FIELD(doorbell_range, 105 GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL, 106 S2A_DOORBELL_PORT2_AWID, 107 0xe); 108 doorbell_range = REG_SET_FIELD(doorbell_range, 109 GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL, 110 S2A_DOORBELL_PORT2_RANGE_OFFSET, 111 doorbell_index); 112 doorbell_range = REG_SET_FIELD(doorbell_range, 113 GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL, 114 S2A_DOORBELL_PORT2_RANGE_SIZE, 115 doorbell_size); 116 doorbell_range = REG_SET_FIELD(doorbell_range, 117 GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL, 118 S2A_DOORBELL_PORT2_AWADDR_31_28_VALUE, 119 0x3); 120 } else 121 doorbell_range = REG_SET_FIELD(doorbell_range, 122 GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL, 123 S2A_DOORBELL_PORT2_RANGE_SIZE, 124 0); 125 126 if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 4)) { 127 WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL_nbif_4_10, doorbell_range); 128 } else { 129 WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL, doorbell_range); 130 } 131 } 132 } 133 134 static void nbif_v6_3_1_vcn_doorbell_range(struct amdgpu_device *adev, 135 bool use_doorbell, int doorbell_index, 136 int instance) 137 { 138 u32 doorbell_range; 139 140 if (instance) 141 doorbell_range = RREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL); 142 else 143 doorbell_range = RREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL); 144 145 if (use_doorbell) { 146 doorbell_range = REG_SET_FIELD(doorbell_range, 147 GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL, 148 S2A_DOORBELL_PORT4_ENABLE, 149 0x1); 150 doorbell_range = REG_SET_FIELD(doorbell_range, 151 GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL, 152 S2A_DOORBELL_PORT4_AWID, 153 instance ? 0x7 : 0x4); 154 doorbell_range = REG_SET_FIELD(doorbell_range, 155 GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL, 156 S2A_DOORBELL_PORT4_RANGE_OFFSET, 157 doorbell_index); 158 doorbell_range = REG_SET_FIELD(doorbell_range, 159 GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL, 160 S2A_DOORBELL_PORT4_RANGE_SIZE, 161 8); 162 doorbell_range = REG_SET_FIELD(doorbell_range, 163 GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL, 164 S2A_DOORBELL_PORT4_AWADDR_31_28_VALUE, 165 instance ? 0x7 : 0x4); 166 } else 167 doorbell_range = REG_SET_FIELD(doorbell_range, 168 GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL, 169 S2A_DOORBELL_PORT4_RANGE_SIZE, 170 0); 171 172 if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 4)) { 173 if (instance) 174 WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL_nbif_4_10, doorbell_range); 175 else 176 WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL_nbif_4_10, doorbell_range); 177 } else { 178 if (instance) 179 WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL, doorbell_range); 180 else 181 WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL, doorbell_range); 182 } 183 } 184 185 static void nbif_v6_3_1_gc_doorbell_init(struct amdgpu_device *adev) 186 { 187 if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 4)) { 188 WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL_nbif_4_10, 0x30000007); 189 WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL_nbif_4_10, 0x3000000d); 190 } else { 191 WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL, 0x30000007); 192 WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL, 0x3000000d); 193 } 194 } 195 196 static void nbif_v6_3_1_enable_doorbell_aperture(struct amdgpu_device *adev, 197 bool enable) 198 { 199 WREG32_FIELD15_PREREG(NBIO, 0, RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN, 200 BIF_DOORBELL_APER_EN, enable ? 1 : 0); 201 } 202 203 static void 204 nbif_v6_3_1_enable_doorbell_selfring_aperture(struct amdgpu_device *adev, 205 bool enable) 206 { 207 u32 tmp = 0; 208 209 if (enable) { 210 tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, 211 DOORBELL_SELFRING_GPA_APER_EN, 1) | 212 REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, 213 DOORBELL_SELFRING_GPA_APER_MODE, 1) | 214 REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, 215 DOORBELL_SELFRING_GPA_APER_SIZE, 0); 216 217 WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW, 218 lower_32_bits(adev->doorbell.base)); 219 WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH, 220 upper_32_bits(adev->doorbell.base)); 221 } 222 223 WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, tmp); 224 } 225 226 static void nbif_v6_3_1_ih_doorbell_range(struct amdgpu_device *adev, 227 bool use_doorbell, int doorbell_index) 228 { 229 u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL); 230 231 if (use_doorbell) { 232 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 233 GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL, 234 S2A_DOORBELL_PORT1_ENABLE, 235 0x1); 236 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 237 GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL, 238 S2A_DOORBELL_PORT1_AWID, 239 0x0); 240 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 241 GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL, 242 S2A_DOORBELL_PORT1_RANGE_OFFSET, 243 doorbell_index); 244 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 245 GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL, 246 S2A_DOORBELL_PORT1_RANGE_SIZE, 247 2); 248 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 249 GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL, 250 S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE, 251 0x0); 252 } else 253 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, 254 GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL, 255 S2A_DOORBELL_PORT1_RANGE_SIZE, 256 0); 257 258 if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 4)) { 259 WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL_nbif_4_10, ih_doorbell_range); 260 } else { 261 WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL, ih_doorbell_range); 262 } 263 } 264 265 static void nbif_v6_3_1_ih_control(struct amdgpu_device *adev) 266 { 267 u32 interrupt_cntl; 268 269 /* setup interrupt control */ 270 WREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL2, adev->dummy_page_addr >> 8); 271 272 interrupt_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL); 273 /* 274 * BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi 275 * BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN 276 */ 277 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL, 278 IH_DUMMY_RD_OVERRIDE, 0); 279 280 /* BIF_BX0_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */ 281 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL, 282 IH_REQ_NONSNOOP_EN, 0); 283 284 WREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL, interrupt_cntl); 285 } 286 287 static void 288 nbif_v6_3_1_update_medium_grain_clock_gating(struct amdgpu_device *adev, 289 bool enable) 290 { 291 } 292 293 static void 294 nbif_v6_3_1_update_medium_grain_light_sleep(struct amdgpu_device *adev, 295 bool enable) 296 { 297 } 298 299 static void 300 nbif_v6_3_1_get_clockgating_state(struct amdgpu_device *adev, 301 u64 *flags) 302 { 303 } 304 305 static u32 nbif_v6_3_1_get_hdp_flush_req_offset(struct amdgpu_device *adev) 306 { 307 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_REQ); 308 } 309 310 static u32 nbif_v6_3_1_get_hdp_flush_done_offset(struct amdgpu_device *adev) 311 { 312 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_DONE); 313 } 314 315 static u32 nbif_v6_3_1_get_pcie_index_offset(struct amdgpu_device *adev) 316 { 317 if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 4)) { 318 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_INDEX); 319 } 320 else { 321 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_INDEX); 322 } 323 } 324 325 static u32 nbif_v6_3_1_get_pcie_data_offset(struct amdgpu_device *adev) 326 { 327 if (amdgpu_ip_version(adev, NBIO_HWIP, 0) == IP_VERSION(7, 11, 4)) 328 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_DATA); 329 else 330 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_DATA); 331 } 332 333 const struct nbio_hdp_flush_reg nbif_v6_3_1_hdp_flush_reg = { 334 .ref_and_mask_cp0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK, 335 .ref_and_mask_cp1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1_MASK, 336 .ref_and_mask_cp2 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2_MASK, 337 .ref_and_mask_cp3 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3_MASK, 338 .ref_and_mask_cp4 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4_MASK, 339 .ref_and_mask_cp5 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5_MASK, 340 .ref_and_mask_cp6 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6_MASK, 341 .ref_and_mask_cp7 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7_MASK, 342 .ref_and_mask_cp8 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8_MASK, 343 .ref_and_mask_cp9 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9_MASK, 344 .ref_and_mask_sdma0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK, 345 .ref_and_mask_sdma1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK, 346 }; 347 348 static void nbif_v6_3_1_init_registers(struct amdgpu_device *adev) 349 { 350 uint32_t data; 351 352 data = RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF2_STRAP2); 353 data &= ~RCC_DEV0_EPF2_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F2_MASK; 354 WREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF2_STRAP2, data); 355 } 356 357 static u32 nbif_v6_3_1_get_rom_offset(struct amdgpu_device *adev) 358 { 359 u32 data, rom_offset; 360 361 data = RREG32_SOC15(NBIO, 0, regREGS_ROM_OFFSET_CTRL); 362 rom_offset = REG_GET_FIELD(data, REGS_ROM_OFFSET_CTRL, ROM_OFFSET); 363 364 return rom_offset; 365 } 366 367 #ifdef CONFIG_PCIEASPM 368 static void nbif_v6_3_1_program_ltr(struct amdgpu_device *adev) 369 { 370 uint32_t def, data; 371 u16 devctl2; 372 373 def = RREG32_SOC15(NBIO, 0, regRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL); 374 data = 0x35EB; 375 data &= ~RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK; 376 data &= ~RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK; 377 if (def != data) 378 WREG32_SOC15(NBIO, 0, regRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL, data); 379 380 def = data = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP2); 381 data &= ~RCC_STRAP0_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK; 382 if (def != data) 383 WREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP2, data); 384 385 pcie_capability_read_word(adev->pdev, PCI_EXP_DEVCTL2, &devctl2); 386 387 if (adev->pdev->ltr_path == (devctl2 & PCI_EXP_DEVCTL2_LTR_EN)) 388 return; 389 390 if (adev->pdev->ltr_path) 391 pcie_capability_set_word(adev->pdev, PCI_EXP_DEVCTL2, PCI_EXP_DEVCTL2_LTR_EN); 392 else 393 pcie_capability_clear_word(adev->pdev, PCI_EXP_DEVCTL2, PCI_EXP_DEVCTL2_LTR_EN); 394 } 395 #endif 396 397 static void nbif_v6_3_1_program_aspm(struct amdgpu_device *adev) 398 { 399 #ifdef CONFIG_PCIEASPM 400 uint32_t def, data; 401 u16 devctl2, ltr; 402 403 def = data = RREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL); 404 data &= ~PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK; 405 data &= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK; 406 data |= PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK; 407 if (def != data) 408 WREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL, data); 409 410 def = data = RREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL7); 411 data |= PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN_MASK; 412 if (def != data) 413 WREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL7, data); 414 415 def = data = RREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL3); 416 data |= PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK; 417 if (def != data) 418 WREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL3, data); 419 420 def = data = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP3); 421 data &= ~RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK; 422 data &= ~RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK; 423 if (def != data) 424 WREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP3, data); 425 426 def = data = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP5); 427 data &= ~RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK; 428 if (def != data) 429 WREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP5, data); 430 431 pcie_capability_read_word(adev->pdev, PCI_EXP_DEVCTL2, &devctl2); 432 data = def = devctl2; 433 data &= ~PCI_EXP_DEVCTL2_LTR_EN; 434 if (def != data) 435 pcie_capability_set_word(adev->pdev, PCI_EXP_DEVCTL2, (u16)data); 436 437 ltr = pci_find_ext_capability(adev->pdev, PCI_EXT_CAP_ID_LTR); 438 439 if (ltr) { 440 pci_write_config_dword(adev->pdev, ltr + PCI_LTR_MAX_SNOOP_LAT, 0x10011001); 441 } 442 443 #if 0 444 /* regPSWUSP0_PCIE_LC_CNTL2 should be replace by PCIE_LC_CNTL2 or someone else ? */ 445 def = data = RREG32_SOC15(NBIO, 0, regPSWUSP0_PCIE_LC_CNTL2); 446 data |= PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK | 447 PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK; 448 data &= ~PSWUSP0_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK; 449 if (def != data) 450 WREG32_SOC15(NBIO, 0, regPSWUSP0_PCIE_LC_CNTL2, data); 451 #endif 452 def = data = RREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL4); 453 data |= PCIE_LC_CNTL4__LC_L1_POWERDOWN_MASK; 454 if (def != data) 455 WREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL4, data); 456 457 def = data = RREG32_SOC15(PCIE, 0, regPCIE_LC_RXRECOVER_RXSTANDBY_CNTL); 458 data |= PCIE_LC_RXRECOVER_RXSTANDBY_CNTL__LC_RX_L0S_STANDBY_EN_MASK; 459 if (def != data) 460 WREG32_SOC15(PCIE, 0, regPCIE_LC_RXRECOVER_RXSTANDBY_CNTL, data); 461 462 nbif_v6_3_1_program_ltr(adev); 463 464 def = data = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP3); 465 data |= 0x5DE0 << RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT; 466 data |= 0x0010 << RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT; 467 if (def != data) 468 WREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP3, data); 469 470 def = data = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP5); 471 data |= 0x0010 << RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT; 472 if (def != data) 473 WREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP5, data); 474 475 def = data = RREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL); 476 data |= 0x0 << PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT; 477 data |= 0x9 << PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT; 478 data &= ~PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK; 479 if (def != data) 480 WREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL, data); 481 482 def = data = RREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL3); 483 data &= ~PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK; 484 if (def != data) 485 WREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL3, data); 486 #endif 487 } 488 489 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE) 490 491 static void nbif_v6_3_1_set_reg_remap(struct amdgpu_device *adev) 492 { 493 if (!amdgpu_sriov_vf(adev) && (PAGE_SIZE <= 4096)) { 494 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; 495 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; 496 } else { 497 adev->rmmio_remap.reg_offset = SOC15_REG_OFFSET(NBIO, 0, 498 regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL) << 2; 499 adev->rmmio_remap.bus_addr = 0; 500 } 501 } 502 503 const struct amdgpu_nbio_funcs nbif_v6_3_1_funcs = { 504 .get_hdp_flush_req_offset = nbif_v6_3_1_get_hdp_flush_req_offset, 505 .get_hdp_flush_done_offset = nbif_v6_3_1_get_hdp_flush_done_offset, 506 .get_pcie_index_offset = nbif_v6_3_1_get_pcie_index_offset, 507 .get_pcie_data_offset = nbif_v6_3_1_get_pcie_data_offset, 508 .get_rev_id = nbif_v6_3_1_get_rev_id, 509 .mc_access_enable = nbif_v6_3_1_mc_access_enable, 510 .get_memsize = nbif_v6_3_1_get_memsize, 511 .sdma_doorbell_range = nbif_v6_3_1_sdma_doorbell_range, 512 .vcn_doorbell_range = nbif_v6_3_1_vcn_doorbell_range, 513 .gc_doorbell_init = nbif_v6_3_1_gc_doorbell_init, 514 .enable_doorbell_aperture = nbif_v6_3_1_enable_doorbell_aperture, 515 .enable_doorbell_selfring_aperture = nbif_v6_3_1_enable_doorbell_selfring_aperture, 516 .ih_doorbell_range = nbif_v6_3_1_ih_doorbell_range, 517 .update_medium_grain_clock_gating = nbif_v6_3_1_update_medium_grain_clock_gating, 518 .update_medium_grain_light_sleep = nbif_v6_3_1_update_medium_grain_light_sleep, 519 .get_clockgating_state = nbif_v6_3_1_get_clockgating_state, 520 .ih_control = nbif_v6_3_1_ih_control, 521 .init_registers = nbif_v6_3_1_init_registers, 522 .remap_hdp_registers = nbif_v6_3_1_remap_hdp_registers, 523 .get_rom_offset = nbif_v6_3_1_get_rom_offset, 524 .program_aspm = nbif_v6_3_1_program_aspm, 525 .set_reg_remap = nbif_v6_3_1_set_reg_remap, 526 }; 527 528 529 static int nbif_v6_3_1_set_ras_err_event_athub_irq_state(struct amdgpu_device *adev, 530 struct amdgpu_irq_src *src, 531 unsigned type, 532 enum amdgpu_interrupt_state state) 533 { 534 /* The ras_controller_irq enablement should be done in psp bl when it 535 * tries to enable ras feature. Driver only need to set the correct interrupt 536 * vector for bare-metal and sriov use case respectively 537 */ 538 uint32_t bif_doorbell_int_cntl; 539 540 bif_doorbell_int_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_DOORBELL_INT_CNTL); 541 bif_doorbell_int_cntl = REG_SET_FIELD(bif_doorbell_int_cntl, 542 BIF_BX0_BIF_DOORBELL_INT_CNTL, 543 RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE, 544 (state == AMDGPU_IRQ_STATE_ENABLE) ? 0 : 1); 545 WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_DOORBELL_INT_CNTL, bif_doorbell_int_cntl); 546 547 return 0; 548 } 549 550 static int nbif_v6_3_1_process_err_event_athub_irq(struct amdgpu_device *adev, 551 struct amdgpu_irq_src *source, 552 struct amdgpu_iv_entry *entry) 553 { 554 /* By design, the ih cookie for err_event_athub_irq should be written 555 * to bif ring. since bif ring is not enabled, just leave process callback 556 * as a dummy one. 557 */ 558 return 0; 559 } 560 561 static const struct amdgpu_irq_src_funcs nbif_v6_3_1_ras_err_event_athub_irq_funcs = { 562 .set = nbif_v6_3_1_set_ras_err_event_athub_irq_state, 563 .process = nbif_v6_3_1_process_err_event_athub_irq, 564 }; 565 566 static void nbif_v6_3_1_handle_ras_err_event_athub_intr_no_bifring(struct amdgpu_device *adev) 567 { 568 uint32_t bif_doorbell_int_cntl; 569 570 bif_doorbell_int_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_DOORBELL_INT_CNTL); 571 if (REG_GET_FIELD(bif_doorbell_int_cntl, 572 BIF_BX0_BIF_DOORBELL_INT_CNTL, 573 RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS)) { 574 /* driver has to clear the interrupt status when bif ring is disabled */ 575 bif_doorbell_int_cntl = REG_SET_FIELD(bif_doorbell_int_cntl, 576 BIF_BX0_BIF_DOORBELL_INT_CNTL, 577 RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR, 1); 578 WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_DOORBELL_INT_CNTL, bif_doorbell_int_cntl); 579 amdgpu_ras_global_ras_isr(adev); 580 } 581 } 582 583 static int nbif_v6_3_1_init_ras_err_event_athub_interrupt(struct amdgpu_device *adev) 584 { 585 int r; 586 587 /* init the irq funcs */ 588 adev->nbio.ras_err_event_athub_irq.funcs = 589 &nbif_v6_3_1_ras_err_event_athub_irq_funcs; 590 adev->nbio.ras_err_event_athub_irq.num_types = 1; 591 592 /* register ras err event athub interrupt 593 * nbif v6_3_1 uses the same irq source as nbio v7_4 594 */ 595 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_BIF, 596 NBIF_7_4__SRCID__ERREVENT_ATHUB_INTERRUPT, 597 &adev->nbio.ras_err_event_athub_irq); 598 599 return r; 600 } 601 602 struct amdgpu_nbio_ras nbif_v6_3_1_ras = { 603 .handle_ras_err_event_athub_intr_no_bifring = 604 nbif_v6_3_1_handle_ras_err_event_athub_intr_no_bifring, 605 .init_ras_err_event_athub_interrupt = 606 nbif_v6_3_1_init_ras_err_event_athub_interrupt, 607 }; 608