1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "amdgpu.h" 24 #include "amdgpu_ras.h" 25 #include "mmhub_v9_4.h" 26 27 #include "mmhub/mmhub_9_4_1_offset.h" 28 #include "mmhub/mmhub_9_4_1_sh_mask.h" 29 #include "mmhub/mmhub_9_4_1_default.h" 30 #include "athub/athub_1_0_offset.h" 31 #include "athub/athub_1_0_sh_mask.h" 32 #include "vega10_enum.h" 33 #include "soc15.h" 34 #include "soc15_common.h" 35 36 #define MMHUB_NUM_INSTANCES 2 37 #define MMHUB_INSTANCE_REGISTER_OFFSET 0x3000 38 39 static u64 mmhub_v9_4_get_fb_location(struct amdgpu_device *adev) 40 { 41 /* The base should be same b/t 2 mmhubs on Acrturus. Read one here. */ 42 u64 base = RREG32_SOC15(MMHUB, 0, mmVMSHAREDVC0_MC_VM_FB_LOCATION_BASE); 43 u64 top = RREG32_SOC15(MMHUB, 0, mmVMSHAREDVC0_MC_VM_FB_LOCATION_TOP); 44 45 base &= VMSHAREDVC0_MC_VM_FB_LOCATION_BASE__FB_BASE_MASK; 46 base <<= 24; 47 48 top &= VMSHAREDVC0_MC_VM_FB_LOCATION_TOP__FB_TOP_MASK; 49 top <<= 24; 50 51 adev->gmc.fb_start = base; 52 adev->gmc.fb_end = top; 53 54 return base; 55 } 56 57 static void mmhub_v9_4_setup_hubid_vm_pt_regs(struct amdgpu_device *adev, int hubid, 58 uint32_t vmid, uint64_t value) 59 { 60 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)]; 61 62 WREG32_SOC15_OFFSET(MMHUB, 0, 63 mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, 64 hub->ctx_addr_distance * vmid + hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 65 lower_32_bits(value)); 66 67 WREG32_SOC15_OFFSET(MMHUB, 0, 68 mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, 69 hub->ctx_addr_distance * vmid + hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 70 upper_32_bits(value)); 71 72 } 73 74 static void mmhub_v9_4_init_gart_aperture_regs(struct amdgpu_device *adev, 75 int hubid) 76 { 77 uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); 78 79 mmhub_v9_4_setup_hubid_vm_pt_regs(adev, hubid, 0, pt_base); 80 81 WREG32_SOC15_OFFSET(MMHUB, 0, 82 mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, 83 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 84 (u32)(adev->gmc.gart_start >> 12)); 85 WREG32_SOC15_OFFSET(MMHUB, 0, 86 mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, 87 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 88 (u32)(adev->gmc.gart_start >> 44)); 89 90 WREG32_SOC15_OFFSET(MMHUB, 0, 91 mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, 92 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 93 (u32)(adev->gmc.gart_end >> 12)); 94 WREG32_SOC15_OFFSET(MMHUB, 0, 95 mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, 96 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 97 (u32)(adev->gmc.gart_end >> 44)); 98 } 99 100 static void mmhub_v9_4_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid, 101 uint64_t page_table_base) 102 { 103 int i; 104 105 for (i = 0; i < MMHUB_NUM_INSTANCES; i++) 106 mmhub_v9_4_setup_hubid_vm_pt_regs(adev, i, vmid, 107 page_table_base); 108 } 109 110 static void mmhub_v9_4_init_system_aperture_regs(struct amdgpu_device *adev, 111 int hubid) 112 { 113 uint64_t value; 114 uint32_t tmp; 115 116 /* Program the AGP BAR */ 117 WREG32_SOC15_OFFSET(MMHUB, 0, mmVMSHAREDVC0_MC_VM_AGP_BASE, 118 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 119 0); 120 WREG32_SOC15_OFFSET(MMHUB, 0, mmVMSHAREDVC0_MC_VM_AGP_TOP, 121 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 122 adev->gmc.agp_end >> 24); 123 WREG32_SOC15_OFFSET(MMHUB, 0, mmVMSHAREDVC0_MC_VM_AGP_BOT, 124 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 125 adev->gmc.agp_start >> 24); 126 127 if (!amdgpu_sriov_vf(adev)) { 128 /* Program the system aperture low logical page number. */ 129 WREG32_SOC15_OFFSET( 130 MMHUB, 0, mmVMSHAREDVC0_MC_VM_SYSTEM_APERTURE_LOW_ADDR, 131 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 132 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); 133 WREG32_SOC15_OFFSET( 134 MMHUB, 0, mmVMSHAREDVC0_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, 135 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 136 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); 137 138 /* Set default page address. */ 139 value = amdgpu_gmc_vram_mc2pa(adev, adev->mem_scratch.gpu_addr); 140 WREG32_SOC15_OFFSET( 141 MMHUB, 0, 142 mmVMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 143 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 144 (u32)(value >> 12)); 145 WREG32_SOC15_OFFSET( 146 MMHUB, 0, 147 mmVMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 148 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 149 (u32)(value >> 44)); 150 151 /* Program "protection fault". */ 152 WREG32_SOC15_OFFSET( 153 MMHUB, 0, 154 mmVML2PF0_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, 155 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 156 (u32)(adev->dummy_page_addr >> 12)); 157 WREG32_SOC15_OFFSET( 158 MMHUB, 0, 159 mmVML2PF0_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, 160 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 161 (u32)((u64)adev->dummy_page_addr >> 44)); 162 163 tmp = RREG32_SOC15_OFFSET( 164 MMHUB, 0, mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL2, 165 hubid * MMHUB_INSTANCE_REGISTER_OFFSET); 166 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL2, 167 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); 168 WREG32_SOC15_OFFSET(MMHUB, 0, 169 mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL2, 170 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 171 tmp); 172 } 173 } 174 175 static void mmhub_v9_4_init_tlb_regs(struct amdgpu_device *adev, int hubid) 176 { 177 uint32_t tmp; 178 179 /* Setup TLB control */ 180 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, 181 mmVMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL, 182 hubid * MMHUB_INSTANCE_REGISTER_OFFSET); 183 184 tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL, 185 ENABLE_L1_TLB, 1); 186 tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL, 187 SYSTEM_ACCESS_MODE, 3); 188 tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL, 189 ENABLE_ADVANCED_DRIVER_MODEL, 1); 190 tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL, 191 SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); 192 tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL, 193 MTYPE, MTYPE_UC);/* XXX for emulation. */ 194 tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL, 195 ATC_EN, 1); 196 197 WREG32_SOC15_OFFSET(MMHUB, 0, mmVMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL, 198 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp); 199 } 200 201 /* Set snoop bit for SDMA so that SDMA writes probe-invalidates RW lines */ 202 static void mmhub_v9_4_init_snoop_override_regs(struct amdgpu_device *adev, int hubid) 203 { 204 uint32_t tmp; 205 int i; 206 uint32_t distance = mmDAGB1_WRCLI_GPU_SNOOP_OVERRIDE - 207 mmDAGB0_WRCLI_GPU_SNOOP_OVERRIDE; 208 uint32_t huboffset = hubid * MMHUB_INSTANCE_REGISTER_OFFSET; 209 210 for (i = 0; i < 5 - (2 * hubid); i++) { 211 /* DAGB instances 0 to 4 are in hub0 and 5 to 7 are in hub1 */ 212 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, 213 mmDAGB0_WRCLI_GPU_SNOOP_OVERRIDE, 214 huboffset + i * distance); 215 tmp |= (1 << 15); /* SDMA client is BIT15 */ 216 WREG32_SOC15_OFFSET(MMHUB, 0, 217 mmDAGB0_WRCLI_GPU_SNOOP_OVERRIDE, 218 huboffset + i * distance, tmp); 219 220 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, 221 mmDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE, 222 huboffset + i * distance); 223 tmp |= (1 << 15); 224 WREG32_SOC15_OFFSET(MMHUB, 0, 225 mmDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE, 226 huboffset + i * distance, tmp); 227 } 228 229 } 230 231 static void mmhub_v9_4_init_cache_regs(struct amdgpu_device *adev, int hubid) 232 { 233 uint32_t tmp; 234 235 /* Setup L2 cache */ 236 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL, 237 hubid * MMHUB_INSTANCE_REGISTER_OFFSET); 238 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL, 239 ENABLE_L2_CACHE, 1); 240 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL, 241 ENABLE_L2_FRAGMENT_PROCESSING, 1); 242 /* XXX for emulation, Refer to closed source code.*/ 243 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL, 244 L2_PDE0_CACHE_TAG_GENERATION_MODE, 0); 245 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL, 246 PDE_FAULT_CLASSIFICATION, 0); 247 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL, 248 CONTEXT1_IDENTITY_ACCESS_MODE, 1); 249 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL, 250 IDENTITY_MODE_FRAGMENT_SIZE, 0); 251 WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL, 252 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp); 253 254 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL2, 255 hubid * MMHUB_INSTANCE_REGISTER_OFFSET); 256 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL2, 257 INVALIDATE_ALL_L1_TLBS, 1); 258 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL2, 259 INVALIDATE_L2_CACHE, 1); 260 WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL2, 261 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp); 262 263 tmp = mmVML2PF0_VM_L2_CNTL3_DEFAULT; 264 if (adev->gmc.translate_further) { 265 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL3, BANK_SELECT, 12); 266 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL3, 267 L2_CACHE_BIGK_FRAGMENT_SIZE, 9); 268 } else { 269 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL3, BANK_SELECT, 9); 270 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL3, 271 L2_CACHE_BIGK_FRAGMENT_SIZE, 6); 272 } 273 WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL3, 274 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp); 275 276 tmp = mmVML2PF0_VM_L2_CNTL4_DEFAULT; 277 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL4, 278 VMC_TAP_PDE_REQUEST_PHYSICAL, 0); 279 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL4, 280 VMC_TAP_PTE_REQUEST_PHYSICAL, 0); 281 WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL4, 282 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp); 283 } 284 285 static void mmhub_v9_4_enable_system_domain(struct amdgpu_device *adev, 286 int hubid) 287 { 288 uint32_t tmp; 289 290 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVML2VC0_VM_CONTEXT0_CNTL, 291 hubid * MMHUB_INSTANCE_REGISTER_OFFSET); 292 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 293 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); 294 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT0_CNTL, 295 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0); 296 WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2VC0_VM_CONTEXT0_CNTL, 297 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp); 298 } 299 300 static void mmhub_v9_4_disable_identity_aperture(struct amdgpu_device *adev, 301 int hubid) 302 { 303 WREG32_SOC15_OFFSET(MMHUB, 0, 304 mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32, 305 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 0XFFFFFFFF); 306 WREG32_SOC15_OFFSET(MMHUB, 0, 307 mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32, 308 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 0x0000000F); 309 310 WREG32_SOC15_OFFSET(MMHUB, 0, 311 mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 312 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 0); 313 WREG32_SOC15_OFFSET(MMHUB, 0, 314 mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 315 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 0); 316 317 WREG32_SOC15_OFFSET(MMHUB, 0, 318 mmVML2PF0_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 319 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 0); 320 WREG32_SOC15_OFFSET(MMHUB, 0, 321 mmVML2PF0_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 322 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 0); 323 } 324 325 static void mmhub_v9_4_setup_vmid_config(struct amdgpu_device *adev, int hubid) 326 { 327 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)]; 328 unsigned int num_level, block_size; 329 uint32_t tmp; 330 int i; 331 332 num_level = adev->vm_manager.num_level; 333 block_size = adev->vm_manager.block_size; 334 if (adev->gmc.translate_further) 335 num_level -= 1; 336 else 337 block_size -= 9; 338 339 for (i = 0; i <= 14; i++) { 340 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVML2VC0_VM_CONTEXT1_CNTL, 341 hubid * MMHUB_INSTANCE_REGISTER_OFFSET + i * hub->ctx_distance); 342 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL, 343 ENABLE_CONTEXT, 1); 344 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL, 345 PAGE_TABLE_DEPTH, 346 num_level); 347 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL, 348 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 349 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL, 350 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 351 1); 352 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL, 353 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 354 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL, 355 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 356 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL, 357 READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 358 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL, 359 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 360 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL, 361 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 362 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL, 363 PAGE_TABLE_BLOCK_SIZE, 364 block_size); 365 /* Send no-retry XNACK on fault to suppress VM fault storm. */ 366 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL, 367 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 368 !adev->gmc.noretry); 369 WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2VC0_VM_CONTEXT1_CNTL, 370 hubid * MMHUB_INSTANCE_REGISTER_OFFSET + 371 i * hub->ctx_distance, tmp); 372 WREG32_SOC15_OFFSET(MMHUB, 0, 373 mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, 374 hubid * MMHUB_INSTANCE_REGISTER_OFFSET + 375 i * hub->ctx_addr_distance, 0); 376 WREG32_SOC15_OFFSET(MMHUB, 0, 377 mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, 378 hubid * MMHUB_INSTANCE_REGISTER_OFFSET + 379 i * hub->ctx_addr_distance, 0); 380 WREG32_SOC15_OFFSET(MMHUB, 0, 381 mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, 382 hubid * MMHUB_INSTANCE_REGISTER_OFFSET + 383 i * hub->ctx_addr_distance, 384 lower_32_bits(adev->vm_manager.max_pfn - 1)); 385 WREG32_SOC15_OFFSET(MMHUB, 0, 386 mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, 387 hubid * MMHUB_INSTANCE_REGISTER_OFFSET + 388 i * hub->ctx_addr_distance, 389 upper_32_bits(adev->vm_manager.max_pfn - 1)); 390 } 391 } 392 393 static void mmhub_v9_4_program_invalidation(struct amdgpu_device *adev, 394 int hubid) 395 { 396 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)]; 397 unsigned i; 398 399 for (i = 0; i < 18; ++i) { 400 WREG32_SOC15_OFFSET(MMHUB, 0, 401 mmVML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32, 402 hubid * MMHUB_INSTANCE_REGISTER_OFFSET + 403 i * hub->eng_addr_distance, 404 0xffffffff); 405 WREG32_SOC15_OFFSET(MMHUB, 0, 406 mmVML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_HI32, 407 hubid * MMHUB_INSTANCE_REGISTER_OFFSET + 408 i * hub->eng_addr_distance, 409 0x1f); 410 } 411 } 412 413 static int mmhub_v9_4_gart_enable(struct amdgpu_device *adev) 414 { 415 int i; 416 417 for (i = 0; i < MMHUB_NUM_INSTANCES; i++) { 418 /* GART Enable. */ 419 mmhub_v9_4_init_gart_aperture_regs(adev, i); 420 mmhub_v9_4_init_system_aperture_regs(adev, i); 421 mmhub_v9_4_init_tlb_regs(adev, i); 422 if (!amdgpu_sriov_vf(adev)) 423 mmhub_v9_4_init_cache_regs(adev, i); 424 425 mmhub_v9_4_init_snoop_override_regs(adev, i); 426 mmhub_v9_4_enable_system_domain(adev, i); 427 if (!amdgpu_sriov_vf(adev)) 428 mmhub_v9_4_disable_identity_aperture(adev, i); 429 mmhub_v9_4_setup_vmid_config(adev, i); 430 mmhub_v9_4_program_invalidation(adev, i); 431 } 432 433 return 0; 434 } 435 436 static void mmhub_v9_4_gart_disable(struct amdgpu_device *adev) 437 { 438 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)]; 439 u32 tmp; 440 u32 i, j; 441 442 for (j = 0; j < MMHUB_NUM_INSTANCES; j++) { 443 /* Disable all tables */ 444 for (i = 0; i < AMDGPU_NUM_VMID; i++) 445 WREG32_SOC15_OFFSET(MMHUB, 0, 446 mmVML2VC0_VM_CONTEXT0_CNTL, 447 j * MMHUB_INSTANCE_REGISTER_OFFSET + 448 i * hub->ctx_distance, 0); 449 450 /* Setup TLB control */ 451 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, 452 mmVMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL, 453 j * MMHUB_INSTANCE_REGISTER_OFFSET); 454 tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL, 455 ENABLE_L1_TLB, 0); 456 tmp = REG_SET_FIELD(tmp, 457 VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL, 458 ENABLE_ADVANCED_DRIVER_MODEL, 0); 459 WREG32_SOC15_OFFSET(MMHUB, 0, 460 mmVMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL, 461 j * MMHUB_INSTANCE_REGISTER_OFFSET, tmp); 462 463 /* Setup L2 cache */ 464 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL, 465 j * MMHUB_INSTANCE_REGISTER_OFFSET); 466 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL, 467 ENABLE_L2_CACHE, 0); 468 WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL, 469 j * MMHUB_INSTANCE_REGISTER_OFFSET, tmp); 470 WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL3, 471 j * MMHUB_INSTANCE_REGISTER_OFFSET, 0); 472 } 473 } 474 475 /** 476 * mmhub_v9_4_set_fault_enable_default - update GART/VM fault handling 477 * 478 * @adev: amdgpu_device pointer 479 * @value: true redirects VM faults to the default page 480 */ 481 static void mmhub_v9_4_set_fault_enable_default(struct amdgpu_device *adev, bool value) 482 { 483 u32 tmp; 484 int i; 485 486 for (i = 0; i < MMHUB_NUM_INSTANCES; i++) { 487 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, 488 mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL, 489 i * MMHUB_INSTANCE_REGISTER_OFFSET); 490 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL, 491 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 492 value); 493 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL, 494 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 495 value); 496 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL, 497 PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, 498 value); 499 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL, 500 PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, 501 value); 502 tmp = REG_SET_FIELD(tmp, 503 VML2PF0_VM_L2_PROTECTION_FAULT_CNTL, 504 TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT, 505 value); 506 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL, 507 NACK_PROTECTION_FAULT_ENABLE_DEFAULT, 508 value); 509 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL, 510 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 511 value); 512 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL, 513 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 514 value); 515 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL, 516 READ_PROTECTION_FAULT_ENABLE_DEFAULT, 517 value); 518 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL, 519 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 520 value); 521 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL, 522 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 523 value); 524 if (!value) { 525 tmp = REG_SET_FIELD(tmp, 526 VML2PF0_VM_L2_PROTECTION_FAULT_CNTL, 527 CRASH_ON_NO_RETRY_FAULT, 1); 528 tmp = REG_SET_FIELD(tmp, 529 VML2PF0_VM_L2_PROTECTION_FAULT_CNTL, 530 CRASH_ON_RETRY_FAULT, 1); 531 } 532 533 WREG32_SOC15_OFFSET(MMHUB, 0, 534 mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL, 535 i * MMHUB_INSTANCE_REGISTER_OFFSET, tmp); 536 } 537 } 538 539 static void mmhub_v9_4_init(struct amdgpu_device *adev) 540 { 541 struct amdgpu_vmhub *hub[MMHUB_NUM_INSTANCES] = { 542 &adev->vmhub[AMDGPU_MMHUB0(0)], &adev->vmhub[AMDGPU_MMHUB1(0)]}; 543 int i; 544 545 for (i = 0; i < MMHUB_NUM_INSTANCES; i++) { 546 hub[i]->ctx0_ptb_addr_lo32 = 547 SOC15_REG_OFFSET(MMHUB, 0, 548 mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32) + 549 i * MMHUB_INSTANCE_REGISTER_OFFSET; 550 hub[i]->ctx0_ptb_addr_hi32 = 551 SOC15_REG_OFFSET(MMHUB, 0, 552 mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32) + 553 i * MMHUB_INSTANCE_REGISTER_OFFSET; 554 hub[i]->vm_inv_eng0_sem = 555 SOC15_REG_OFFSET(MMHUB, 0, 556 mmVML2VC0_VM_INVALIDATE_ENG0_SEM) + 557 i * MMHUB_INSTANCE_REGISTER_OFFSET; 558 hub[i]->vm_inv_eng0_req = 559 SOC15_REG_OFFSET(MMHUB, 0, 560 mmVML2VC0_VM_INVALIDATE_ENG0_REQ) + 561 i * MMHUB_INSTANCE_REGISTER_OFFSET; 562 hub[i]->vm_inv_eng0_ack = 563 SOC15_REG_OFFSET(MMHUB, 0, 564 mmVML2VC0_VM_INVALIDATE_ENG0_ACK) + 565 i * MMHUB_INSTANCE_REGISTER_OFFSET; 566 hub[i]->vm_context0_cntl = 567 SOC15_REG_OFFSET(MMHUB, 0, 568 mmVML2VC0_VM_CONTEXT0_CNTL) + 569 i * MMHUB_INSTANCE_REGISTER_OFFSET; 570 hub[i]->vm_l2_pro_fault_status = 571 SOC15_REG_OFFSET(MMHUB, 0, 572 mmVML2PF0_VM_L2_PROTECTION_FAULT_STATUS) + 573 i * MMHUB_INSTANCE_REGISTER_OFFSET; 574 hub[i]->vm_l2_pro_fault_cntl = 575 SOC15_REG_OFFSET(MMHUB, 0, 576 mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL) + 577 i * MMHUB_INSTANCE_REGISTER_OFFSET; 578 579 hub[i]->ctx_distance = mmVML2VC0_VM_CONTEXT1_CNTL - 580 mmVML2VC0_VM_CONTEXT0_CNTL; 581 hub[i]->ctx_addr_distance = mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 - 582 mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32; 583 hub[i]->eng_distance = mmVML2VC0_VM_INVALIDATE_ENG1_REQ - 584 mmVML2VC0_VM_INVALIDATE_ENG0_REQ; 585 hub[i]->eng_addr_distance = mmVML2VC0_VM_INVALIDATE_ENG1_ADDR_RANGE_LO32 - 586 mmVML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32; 587 } 588 } 589 590 static void mmhub_v9_4_update_medium_grain_clock_gating(struct amdgpu_device *adev, 591 bool enable) 592 { 593 uint32_t def, data, def1, data1; 594 int i, j; 595 int dist = mmDAGB1_CNTL_MISC2 - mmDAGB0_CNTL_MISC2; 596 597 for (i = 0; i < MMHUB_NUM_INSTANCES; i++) { 598 def = data = RREG32_SOC15_OFFSET(MMHUB, 0, 599 mmATCL2_0_ATC_L2_MISC_CG, 600 i * MMHUB_INSTANCE_REGISTER_OFFSET); 601 602 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) 603 data |= ATCL2_0_ATC_L2_MISC_CG__ENABLE_MASK; 604 else 605 data &= ~ATCL2_0_ATC_L2_MISC_CG__ENABLE_MASK; 606 607 if (def != data) 608 WREG32_SOC15_OFFSET(MMHUB, 0, mmATCL2_0_ATC_L2_MISC_CG, 609 i * MMHUB_INSTANCE_REGISTER_OFFSET, data); 610 611 for (j = 0; j < 5; j++) { 612 def1 = data1 = RREG32_SOC15_OFFSET(MMHUB, 0, 613 mmDAGB0_CNTL_MISC2, 614 i * MMHUB_INSTANCE_REGISTER_OFFSET + 615 j * dist); 616 if (enable && 617 (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) { 618 data1 &= 619 ~(DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | 620 DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK | 621 DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | 622 DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK | 623 DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | 624 DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); 625 } else { 626 data1 |= 627 (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | 628 DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK | 629 DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | 630 DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK | 631 DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | 632 DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); 633 } 634 635 if (def1 != data1) 636 WREG32_SOC15_OFFSET(MMHUB, 0, 637 mmDAGB0_CNTL_MISC2, 638 i * MMHUB_INSTANCE_REGISTER_OFFSET + 639 j * dist, data1); 640 641 if (i == 1 && j == 3) 642 break; 643 } 644 } 645 } 646 647 static void mmhub_v9_4_update_medium_grain_light_sleep(struct amdgpu_device *adev, 648 bool enable) 649 { 650 uint32_t def, data; 651 int i; 652 653 for (i = 0; i < MMHUB_NUM_INSTANCES; i++) { 654 def = data = RREG32_SOC15_OFFSET(MMHUB, 0, 655 mmATCL2_0_ATC_L2_MISC_CG, 656 i * MMHUB_INSTANCE_REGISTER_OFFSET); 657 658 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) 659 data |= ATCL2_0_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK; 660 else 661 data &= ~ATCL2_0_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK; 662 663 if (def != data) 664 WREG32_SOC15_OFFSET(MMHUB, 0, mmATCL2_0_ATC_L2_MISC_CG, 665 i * MMHUB_INSTANCE_REGISTER_OFFSET, data); 666 } 667 } 668 669 static int mmhub_v9_4_set_clockgating(struct amdgpu_device *adev, 670 enum amd_clockgating_state state) 671 { 672 if (amdgpu_sriov_vf(adev)) 673 return 0; 674 675 switch (adev->asic_type) { 676 case CHIP_ARCTURUS: 677 mmhub_v9_4_update_medium_grain_clock_gating(adev, 678 state == AMD_CG_STATE_GATE); 679 mmhub_v9_4_update_medium_grain_light_sleep(adev, 680 state == AMD_CG_STATE_GATE); 681 break; 682 default: 683 break; 684 } 685 686 return 0; 687 } 688 689 static void mmhub_v9_4_get_clockgating(struct amdgpu_device *adev, u64 *flags) 690 { 691 u32 data, data1; 692 693 if (amdgpu_sriov_vf(adev)) 694 *flags = 0; 695 696 /* AMD_CG_SUPPORT_MC_MGCG */ 697 data = RREG32_SOC15(MMHUB, 0, mmATCL2_0_ATC_L2_MISC_CG); 698 699 data1 = RREG32_SOC15(MMHUB, 0, mmATCL2_0_ATC_L2_MISC_CG); 700 701 if ((data & ATCL2_0_ATC_L2_MISC_CG__ENABLE_MASK) && 702 !(data1 & (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | 703 DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK | 704 DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | 705 DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK | 706 DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | 707 DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK))) 708 *flags |= AMD_CG_SUPPORT_MC_MGCG; 709 710 /* AMD_CG_SUPPORT_MC_LS */ 711 if (data & ATCL2_0_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK) 712 *flags |= AMD_CG_SUPPORT_MC_LS; 713 } 714 715 static const struct soc15_ras_field_entry mmhub_v9_4_ras_fields[] = { 716 /* MMHUB Range 0 */ 717 { "MMEA0_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT), 718 SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT), 719 SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT), 720 }, 721 { "MMEA0_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT), 722 SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT), 723 SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT), 724 }, 725 { "MMEA0_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT), 726 SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT), 727 SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT), 728 }, 729 { "MMEA0_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT), 730 SOC15_REG_FIELD(MMEA0_EDC_CNT, RRET_TAGMEM_SEC_COUNT), 731 SOC15_REG_FIELD(MMEA0_EDC_CNT, RRET_TAGMEM_DED_COUNT), 732 }, 733 { "MMEA0_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT), 734 SOC15_REG_FIELD(MMEA0_EDC_CNT, WRET_TAGMEM_SEC_COUNT), 735 SOC15_REG_FIELD(MMEA0_EDC_CNT, WRET_TAGMEM_DED_COUNT), 736 }, 737 { "MMEA0_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT), 738 SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT), 739 0, 0, 740 }, 741 { "MMEA0_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT), 742 SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT), 743 0, 0, 744 }, 745 { "MMEA0_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT), 746 SOC15_REG_FIELD(MMEA0_EDC_CNT, IORD_CMDMEM_SED_COUNT), 747 0, 0, 748 }, 749 { "MMEA0_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT), 750 SOC15_REG_FIELD(MMEA0_EDC_CNT, IOWR_CMDMEM_SED_COUNT), 751 0, 0, 752 }, 753 { "MMEA0_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT), 754 SOC15_REG_FIELD(MMEA0_EDC_CNT, IOWR_DATAMEM_SED_COUNT), 755 0, 0, 756 }, 757 { "MMEA0_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2), 758 SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT), 759 SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT), 760 }, 761 { "MMEA0_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2), 762 SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT), 763 SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT), 764 }, 765 { "MMEA0_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2), 766 SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT), 767 SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT), 768 }, 769 { "MMEA0_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2), 770 SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT), 771 0, 0, 772 }, 773 { "MMEA0_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2), 774 SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT), 775 0, 0, 776 }, 777 { "MMEA0_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT3), 778 0, 0, 779 SOC15_REG_FIELD(MMEA0_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT), 780 }, 781 { "MMEA0_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT3), 782 0, 0, 783 SOC15_REG_FIELD(MMEA0_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT), 784 }, 785 { "MMEA0_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT3), 786 0, 0, 787 SOC15_REG_FIELD(MMEA0_EDC_CNT3, IORD_CMDMEM_DED_COUNT), 788 }, 789 { "MMEA0_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT3), 790 0, 0, 791 SOC15_REG_FIELD(MMEA0_EDC_CNT3, IOWR_CMDMEM_DED_COUNT), 792 }, 793 { "MMEA0_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT3), 794 0, 0, 795 SOC15_REG_FIELD(MMEA0_EDC_CNT3, IOWR_DATAMEM_DED_COUNT), 796 }, 797 { "MMEA0_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT3), 798 0, 0, 799 SOC15_REG_FIELD(MMEA0_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT), 800 }, 801 { "MMEA0_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT3), 802 0, 0, 803 SOC15_REG_FIELD(MMEA0_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT), 804 }, 805 { "MMEA0_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2), 806 SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D0MEM_SED_COUNT), 807 SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D0MEM_DED_COUNT), 808 }, 809 { "MMEA0_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2), 810 SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D1MEM_SED_COUNT), 811 SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D1MEM_DED_COUNT), 812 }, 813 { "MMEA0_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2), 814 SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D2MEM_SED_COUNT), 815 SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D2MEM_DED_COUNT), 816 }, 817 { "MMEA0_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2), 818 SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D3MEM_SED_COUNT), 819 SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D3MEM_DED_COUNT), 820 }, 821 822 /* MMHUB Range 1 */ 823 { "MMEA1_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT), 824 SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT), 825 SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT), 826 }, 827 { "MMEA1_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT), 828 SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT), 829 SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT), 830 }, 831 { "MMEA1_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT), 832 SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT), 833 SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT), 834 }, 835 { "MMEA1_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT), 836 SOC15_REG_FIELD(MMEA1_EDC_CNT, RRET_TAGMEM_SEC_COUNT), 837 SOC15_REG_FIELD(MMEA1_EDC_CNT, RRET_TAGMEM_DED_COUNT), 838 }, 839 { "MMEA1_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT), 840 SOC15_REG_FIELD(MMEA1_EDC_CNT, WRET_TAGMEM_SEC_COUNT), 841 SOC15_REG_FIELD(MMEA1_EDC_CNT, WRET_TAGMEM_DED_COUNT), 842 }, 843 { "MMEA1_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT), 844 SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT), 845 0, 0, 846 }, 847 { "MMEA1_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT), 848 SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT), 849 0, 0, 850 }, 851 { "MMEA1_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT), 852 SOC15_REG_FIELD(MMEA1_EDC_CNT, IORD_CMDMEM_SED_COUNT), 853 0, 0, 854 }, 855 { "MMEA1_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT), 856 SOC15_REG_FIELD(MMEA1_EDC_CNT, IOWR_CMDMEM_SED_COUNT), 857 0, 0, 858 }, 859 { "MMEA1_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT), 860 SOC15_REG_FIELD(MMEA1_EDC_CNT, IOWR_DATAMEM_SED_COUNT), 861 0, 0, 862 }, 863 { "MMEA1_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2), 864 SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT), 865 SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT), 866 }, 867 { "MMEA1_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2), 868 SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT), 869 SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT), 870 }, 871 { "MMEA1_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2), 872 SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT), 873 SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT), 874 }, 875 { "MMEA1_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2), 876 SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT), 877 0, 0, 878 }, 879 { "MMEA1_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2), 880 SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT), 881 0, 0, 882 }, 883 { "MMEA1_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT3), 884 0, 0, 885 SOC15_REG_FIELD(MMEA1_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT), 886 }, 887 { "MMEA1_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT3), 888 0, 0, 889 SOC15_REG_FIELD(MMEA1_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT), 890 }, 891 { "MMEA1_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT3), 892 0, 0, 893 SOC15_REG_FIELD(MMEA1_EDC_CNT3, IORD_CMDMEM_DED_COUNT), 894 }, 895 { "MMEA1_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT3), 896 0, 0, 897 SOC15_REG_FIELD(MMEA1_EDC_CNT3, IOWR_CMDMEM_DED_COUNT), 898 }, 899 { "MMEA1_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT3), 900 0, 0, 901 SOC15_REG_FIELD(MMEA1_EDC_CNT3, IOWR_DATAMEM_DED_COUNT), 902 }, 903 { "MMEA1_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT3), 904 0, 0, 905 SOC15_REG_FIELD(MMEA1_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT), 906 }, 907 { "MMEA1_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT3), 908 0, 0, 909 SOC15_REG_FIELD(MMEA1_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT), 910 }, 911 { "MMEA1_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2), 912 SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D0MEM_SED_COUNT), 913 SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D0MEM_DED_COUNT), 914 }, 915 { "MMEA1_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2), 916 SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D1MEM_SED_COUNT), 917 SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D1MEM_DED_COUNT), 918 }, 919 { "MMEA1_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2), 920 SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D2MEM_SED_COUNT), 921 SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D2MEM_DED_COUNT), 922 }, 923 { "MMEA1_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2), 924 SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D3MEM_SED_COUNT), 925 SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D3MEM_DED_COUNT), 926 }, 927 928 /* MMHAB Range 2*/ 929 { "MMEA2_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT), 930 SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT), 931 SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT), 932 }, 933 { "MMEA2_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT), 934 SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT), 935 SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT), 936 }, 937 { "MMEA2_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT), 938 SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT), 939 SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT), 940 }, 941 { "MMEA2_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT), 942 SOC15_REG_FIELD(MMEA2_EDC_CNT, RRET_TAGMEM_SEC_COUNT), 943 SOC15_REG_FIELD(MMEA2_EDC_CNT, RRET_TAGMEM_DED_COUNT), 944 }, 945 { "MMEA2_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT), 946 SOC15_REG_FIELD(MMEA2_EDC_CNT, WRET_TAGMEM_SEC_COUNT), 947 SOC15_REG_FIELD(MMEA2_EDC_CNT, WRET_TAGMEM_DED_COUNT), 948 }, 949 { "MMEA2_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT), 950 SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT), 951 0, 0, 952 }, 953 { "MMEA2_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT), 954 SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT), 955 0, 0, 956 }, 957 { "MMEA2_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT), 958 SOC15_REG_FIELD(MMEA2_EDC_CNT, IORD_CMDMEM_SED_COUNT), 959 0, 0, 960 }, 961 { "MMEA2_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT), 962 SOC15_REG_FIELD(MMEA2_EDC_CNT, IOWR_CMDMEM_SED_COUNT), 963 0, 0, 964 }, 965 { "MMEA2_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT), 966 SOC15_REG_FIELD(MMEA2_EDC_CNT, IOWR_DATAMEM_SED_COUNT), 967 0, 0, 968 }, 969 { "MMEA2_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT2), 970 SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT), 971 SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT), 972 }, 973 { "MMEA2_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT2), 974 SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT), 975 SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT), 976 }, 977 { "MMEA2_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT2), 978 SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT), 979 SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT), 980 }, 981 { "MMEA2_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT2), 982 SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT), 983 0, 0, 984 }, 985 { "MMEA2_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT2), 986 SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT), 987 0, 0, 988 }, 989 { "MMEA2_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT3), 990 0, 0, 991 SOC15_REG_FIELD(MMEA2_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT), 992 }, 993 { "MMEA2_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT3), 994 0, 0, 995 SOC15_REG_FIELD(MMEA2_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT), 996 }, 997 { "MMEA2_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT3), 998 0, 0, 999 SOC15_REG_FIELD(MMEA2_EDC_CNT3, IORD_CMDMEM_DED_COUNT), 1000 }, 1001 { "MMEA2_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT3), 1002 0, 0, 1003 SOC15_REG_FIELD(MMEA2_EDC_CNT3, IOWR_CMDMEM_DED_COUNT), 1004 }, 1005 { "MMEA2_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT3), 1006 0, 0, 1007 SOC15_REG_FIELD(MMEA2_EDC_CNT3, IOWR_DATAMEM_DED_COUNT), 1008 }, 1009 { "MMEA2_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT3), 1010 0, 0, 1011 SOC15_REG_FIELD(MMEA2_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT), 1012 }, 1013 { "MMEA2_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT3), 1014 0, 0, 1015 SOC15_REG_FIELD(MMEA2_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT), 1016 }, 1017 { "MMEA2_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT2), 1018 SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D0MEM_SED_COUNT), 1019 SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D0MEM_DED_COUNT), 1020 }, 1021 { "MMEA2_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT2), 1022 SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D1MEM_SED_COUNT), 1023 SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D1MEM_DED_COUNT), 1024 }, 1025 { "MMEA2_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT2), 1026 SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D2MEM_SED_COUNT), 1027 SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D2MEM_DED_COUNT), 1028 }, 1029 { "MMEA2_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT2), 1030 SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D3MEM_SED_COUNT), 1031 SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D3MEM_DED_COUNT), 1032 }, 1033 1034 /* MMHUB Rang 3 */ 1035 { "MMEA3_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT), 1036 SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT), 1037 SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT), 1038 }, 1039 { "MMEA3_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT), 1040 SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT), 1041 SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT), 1042 }, 1043 { "MMEA3_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT), 1044 SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT), 1045 SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT), 1046 }, 1047 { "MMEA3_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT), 1048 SOC15_REG_FIELD(MMEA3_EDC_CNT, RRET_TAGMEM_SEC_COUNT), 1049 SOC15_REG_FIELD(MMEA3_EDC_CNT, RRET_TAGMEM_DED_COUNT), 1050 }, 1051 { "MMEA3_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT), 1052 SOC15_REG_FIELD(MMEA3_EDC_CNT, WRET_TAGMEM_SEC_COUNT), 1053 SOC15_REG_FIELD(MMEA3_EDC_CNT, WRET_TAGMEM_DED_COUNT), 1054 }, 1055 { "MMEA3_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT), 1056 SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT), 1057 0, 0, 1058 }, 1059 { "MMEA3_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT), 1060 SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT), 1061 0, 0, 1062 }, 1063 { "MMEA3_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT), 1064 SOC15_REG_FIELD(MMEA3_EDC_CNT, IORD_CMDMEM_SED_COUNT), 1065 0, 0, 1066 }, 1067 { "MMEA3_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT), 1068 SOC15_REG_FIELD(MMEA3_EDC_CNT, IOWR_CMDMEM_SED_COUNT), 1069 0, 0, 1070 }, 1071 { "MMEA3_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT), 1072 SOC15_REG_FIELD(MMEA3_EDC_CNT, IOWR_DATAMEM_SED_COUNT), 1073 0, 0, 1074 }, 1075 { "MMEA3_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT2), 1076 SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT), 1077 SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT), 1078 }, 1079 { "MMEA3_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT2), 1080 SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT), 1081 SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT), 1082 }, 1083 { "MMEA3_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT2), 1084 SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT), 1085 SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT), 1086 }, 1087 { "MMEA3_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT2), 1088 SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT), 1089 0, 0, 1090 }, 1091 { "MMEA3_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT2), 1092 SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT), 1093 0, 0, 1094 }, 1095 { "MMEA3_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT3), 1096 0, 0, 1097 SOC15_REG_FIELD(MMEA3_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT), 1098 }, 1099 { "MMEA3_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT3), 1100 0, 0, 1101 SOC15_REG_FIELD(MMEA3_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT), 1102 }, 1103 { "MMEA3_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT3), 1104 0, 0, 1105 SOC15_REG_FIELD(MMEA3_EDC_CNT3, IORD_CMDMEM_DED_COUNT), 1106 }, 1107 { "MMEA3_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT3), 1108 0, 0, 1109 SOC15_REG_FIELD(MMEA3_EDC_CNT3, IOWR_CMDMEM_DED_COUNT), 1110 }, 1111 { "MMEA3_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT3), 1112 0, 0, 1113 SOC15_REG_FIELD(MMEA3_EDC_CNT3, IOWR_DATAMEM_DED_COUNT), 1114 }, 1115 { "MMEA3_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT3), 1116 0, 0, 1117 SOC15_REG_FIELD(MMEA3_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT), 1118 }, 1119 { "MMEA3_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT3), 1120 0, 0, 1121 SOC15_REG_FIELD(MMEA3_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT), 1122 }, 1123 { "MMEA3_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT2), 1124 SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D0MEM_SED_COUNT), 1125 SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D0MEM_DED_COUNT), 1126 }, 1127 { "MMEA3_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT2), 1128 SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D1MEM_SED_COUNT), 1129 SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D1MEM_DED_COUNT), 1130 }, 1131 { "MMEA3_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT2), 1132 SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D2MEM_SED_COUNT), 1133 SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D2MEM_DED_COUNT), 1134 }, 1135 { "MMEA3_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT2), 1136 SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D3MEM_SED_COUNT), 1137 SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D3MEM_DED_COUNT), 1138 }, 1139 1140 /* MMHUB Range 4 */ 1141 { "MMEA4_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT), 1142 SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT), 1143 SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT), 1144 }, 1145 { "MMEA4_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT), 1146 SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT), 1147 SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT), 1148 }, 1149 { "MMEA4_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT), 1150 SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT), 1151 SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT), 1152 }, 1153 { "MMEA4_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT), 1154 SOC15_REG_FIELD(MMEA4_EDC_CNT, RRET_TAGMEM_SEC_COUNT), 1155 SOC15_REG_FIELD(MMEA4_EDC_CNT, RRET_TAGMEM_DED_COUNT), 1156 }, 1157 { "MMEA4_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT), 1158 SOC15_REG_FIELD(MMEA4_EDC_CNT, WRET_TAGMEM_SEC_COUNT), 1159 SOC15_REG_FIELD(MMEA4_EDC_CNT, WRET_TAGMEM_DED_COUNT), 1160 }, 1161 { "MMEA4_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT), 1162 SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT), 1163 0, 0, 1164 }, 1165 { "MMEA4_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT), 1166 SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT), 1167 0, 0, 1168 }, 1169 { "MMEA4_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT), 1170 SOC15_REG_FIELD(MMEA4_EDC_CNT, IORD_CMDMEM_SED_COUNT), 1171 0, 0, 1172 }, 1173 { "MMEA4_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT), 1174 SOC15_REG_FIELD(MMEA4_EDC_CNT, IOWR_CMDMEM_SED_COUNT), 1175 0, 0, 1176 }, 1177 { "MMEA4_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT), 1178 SOC15_REG_FIELD(MMEA4_EDC_CNT, IOWR_DATAMEM_SED_COUNT), 1179 0, 0, 1180 }, 1181 { "MMEA4_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT2), 1182 SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT), 1183 SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT), 1184 }, 1185 { "MMEA4_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT2), 1186 SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT), 1187 SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT), 1188 }, 1189 { "MMEA4_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT2), 1190 SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT), 1191 SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT), 1192 }, 1193 { "MMEA4_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT2), 1194 SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT), 1195 0, 0, 1196 }, 1197 { "MMEA4_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT2), 1198 SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT), 1199 0, 0, 1200 }, 1201 { "MMEA4_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT3), 1202 0, 0, 1203 SOC15_REG_FIELD(MMEA4_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT), 1204 }, 1205 { "MMEA4_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT3), 1206 0, 0, 1207 SOC15_REG_FIELD(MMEA4_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT), 1208 }, 1209 { "MMEA4_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT3), 1210 0, 0, 1211 SOC15_REG_FIELD(MMEA4_EDC_CNT3, IORD_CMDMEM_DED_COUNT), 1212 }, 1213 { "MMEA4_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT3), 1214 0, 0, 1215 SOC15_REG_FIELD(MMEA4_EDC_CNT3, IOWR_CMDMEM_DED_COUNT), 1216 }, 1217 { "MMEA4_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT3), 1218 0, 0, 1219 SOC15_REG_FIELD(MMEA4_EDC_CNT3, IOWR_DATAMEM_DED_COUNT), 1220 }, 1221 { "MMEA4_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT3), 1222 0, 0, 1223 SOC15_REG_FIELD(MMEA4_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT), 1224 }, 1225 { "MMEA4_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT3), 1226 0, 0, 1227 SOC15_REG_FIELD(MMEA4_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT), 1228 }, 1229 { "MMEA4_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT2), 1230 SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D0MEM_SED_COUNT), 1231 SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D0MEM_DED_COUNT), 1232 }, 1233 { "MMEA4_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT2), 1234 SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D1MEM_SED_COUNT), 1235 SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D1MEM_DED_COUNT), 1236 }, 1237 { "MMEA4_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT2), 1238 SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D2MEM_SED_COUNT), 1239 SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D2MEM_DED_COUNT), 1240 }, 1241 { "MMEA4_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT2), 1242 SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D3MEM_SED_COUNT), 1243 SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D3MEM_DED_COUNT), 1244 }, 1245 1246 /* MMHUAB Range 5 */ 1247 { "MMEA5_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT), 1248 SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT), 1249 SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT), 1250 }, 1251 { "MMEA5_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT), 1252 SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT), 1253 SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT), 1254 }, 1255 { "MMEA5_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT), 1256 SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT), 1257 SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT), 1258 }, 1259 { "MMEA5_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT), 1260 SOC15_REG_FIELD(MMEA5_EDC_CNT, RRET_TAGMEM_SEC_COUNT), 1261 SOC15_REG_FIELD(MMEA5_EDC_CNT, RRET_TAGMEM_DED_COUNT), 1262 }, 1263 { "MMEA5_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT), 1264 SOC15_REG_FIELD(MMEA5_EDC_CNT, WRET_TAGMEM_SEC_COUNT), 1265 SOC15_REG_FIELD(MMEA5_EDC_CNT, WRET_TAGMEM_DED_COUNT), 1266 }, 1267 { "MMEA5_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT), 1268 SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT), 1269 0, 0, 1270 }, 1271 { "MMEA5_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT), 1272 SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT), 1273 0, 0, 1274 }, 1275 { "MMEA5_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT), 1276 SOC15_REG_FIELD(MMEA5_EDC_CNT, IORD_CMDMEM_SED_COUNT), 1277 0, 0, 1278 }, 1279 { "MMEA5_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT), 1280 SOC15_REG_FIELD(MMEA5_EDC_CNT, IOWR_CMDMEM_SED_COUNT), 1281 0, 0, 1282 }, 1283 { "MMEA5_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT), 1284 SOC15_REG_FIELD(MMEA5_EDC_CNT, IOWR_DATAMEM_SED_COUNT), 1285 0, 0, 1286 }, 1287 { "MMEA5_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT2), 1288 SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT), 1289 SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT), 1290 }, 1291 { "MMEA5_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT2), 1292 SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT), 1293 SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT), 1294 }, 1295 { "MMEA5_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT2), 1296 SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT), 1297 SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT), 1298 }, 1299 { "MMEA5_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT2), 1300 SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT), 1301 0, 0, 1302 }, 1303 { "MMEA5_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT2), 1304 SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT), 1305 0, 0, 1306 }, 1307 { "MMEA5_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT3), 1308 0, 0, 1309 SOC15_REG_FIELD(MMEA5_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT), 1310 }, 1311 { "MMEA5_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT3), 1312 0, 0, 1313 SOC15_REG_FIELD(MMEA5_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT), 1314 }, 1315 { "MMEA5_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT3), 1316 0, 0, 1317 SOC15_REG_FIELD(MMEA5_EDC_CNT3, IORD_CMDMEM_DED_COUNT), 1318 }, 1319 { "MMEA5_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT3), 1320 0, 0, 1321 SOC15_REG_FIELD(MMEA5_EDC_CNT3, IOWR_CMDMEM_DED_COUNT), 1322 }, 1323 { "MMEA5_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT3), 1324 0, 0, 1325 SOC15_REG_FIELD(MMEA5_EDC_CNT3, IOWR_DATAMEM_DED_COUNT), 1326 }, 1327 { "MMEA5_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT3), 1328 0, 0, 1329 SOC15_REG_FIELD(MMEA5_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT), 1330 }, 1331 { "MMEA5_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT3), 1332 0, 0, 1333 SOC15_REG_FIELD(MMEA5_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT), 1334 }, 1335 { "MMEA5_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT2), 1336 SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D0MEM_SED_COUNT), 1337 SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D0MEM_DED_COUNT), 1338 }, 1339 { "MMEA5_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT2), 1340 SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D1MEM_SED_COUNT), 1341 SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D1MEM_DED_COUNT), 1342 }, 1343 { "MMEA5_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT2), 1344 SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D2MEM_SED_COUNT), 1345 SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D2MEM_DED_COUNT), 1346 }, 1347 { "MMEA5_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT2), 1348 SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D3MEM_SED_COUNT), 1349 SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D3MEM_DED_COUNT), 1350 }, 1351 1352 /* MMHUB Range 6 */ 1353 { "MMEA6_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT), 1354 SOC15_REG_FIELD(MMEA6_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT), 1355 SOC15_REG_FIELD(MMEA6_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT), 1356 }, 1357 { "MMEA6_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT), 1358 SOC15_REG_FIELD(MMEA6_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT), 1359 SOC15_REG_FIELD(MMEA6_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT), 1360 }, 1361 { "MMEA6_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT), 1362 SOC15_REG_FIELD(MMEA6_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT), 1363 SOC15_REG_FIELD(MMEA6_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT), 1364 }, 1365 { "MMEA6_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT), 1366 SOC15_REG_FIELD(MMEA6_EDC_CNT, RRET_TAGMEM_SEC_COUNT), 1367 SOC15_REG_FIELD(MMEA6_EDC_CNT, RRET_TAGMEM_DED_COUNT), 1368 }, 1369 { "MMEA6_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT), 1370 SOC15_REG_FIELD(MMEA6_EDC_CNT, WRET_TAGMEM_SEC_COUNT), 1371 SOC15_REG_FIELD(MMEA6_EDC_CNT, WRET_TAGMEM_DED_COUNT), 1372 }, 1373 { "MMEA6_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT), 1374 SOC15_REG_FIELD(MMEA6_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT), 1375 0, 0, 1376 }, 1377 { "MMEA6_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT), 1378 SOC15_REG_FIELD(MMEA6_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT), 1379 0, 0, 1380 }, 1381 { "MMEA6_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT), 1382 SOC15_REG_FIELD(MMEA6_EDC_CNT, IORD_CMDMEM_SED_COUNT), 1383 0, 0, 1384 }, 1385 { "MMEA6_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT), 1386 SOC15_REG_FIELD(MMEA6_EDC_CNT, IOWR_CMDMEM_SED_COUNT), 1387 0, 0, 1388 }, 1389 { "MMEA6_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT), 1390 SOC15_REG_FIELD(MMEA6_EDC_CNT, IOWR_DATAMEM_SED_COUNT), 1391 0, 0, 1392 }, 1393 { "MMEA6_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT2), 1394 SOC15_REG_FIELD(MMEA6_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT), 1395 SOC15_REG_FIELD(MMEA6_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT), 1396 }, 1397 { "MMEA6_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT2), 1398 SOC15_REG_FIELD(MMEA6_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT), 1399 SOC15_REG_FIELD(MMEA6_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT), 1400 }, 1401 { "MMEA6_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT2), 1402 SOC15_REG_FIELD(MMEA6_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT), 1403 SOC15_REG_FIELD(MMEA6_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT), 1404 }, 1405 { "MMEA6_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT2), 1406 SOC15_REG_FIELD(MMEA6_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT), 1407 0, 0, 1408 }, 1409 { "MMEA6_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT2), 1410 SOC15_REG_FIELD(MMEA6_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT), 1411 0, 0, 1412 }, 1413 { "MMEA6_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT3), 1414 0, 0, 1415 SOC15_REG_FIELD(MMEA6_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT), 1416 }, 1417 { "MMEA6_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT3), 1418 0, 0, 1419 SOC15_REG_FIELD(MMEA6_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT), 1420 }, 1421 { "MMEA6_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT3), 1422 0, 0, 1423 SOC15_REG_FIELD(MMEA6_EDC_CNT3, IORD_CMDMEM_DED_COUNT), 1424 }, 1425 { "MMEA6_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT3), 1426 0, 0, 1427 SOC15_REG_FIELD(MMEA6_EDC_CNT3, IOWR_CMDMEM_DED_COUNT), 1428 }, 1429 { "MMEA6_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT3), 1430 0, 0, 1431 SOC15_REG_FIELD(MMEA6_EDC_CNT3, IOWR_DATAMEM_DED_COUNT), 1432 }, 1433 { "MMEA6_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT3), 1434 0, 0, 1435 SOC15_REG_FIELD(MMEA6_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT), 1436 }, 1437 { "MMEA6_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT3), 1438 0, 0, 1439 SOC15_REG_FIELD(MMEA6_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT), 1440 }, 1441 { "MMEA6_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT2), 1442 SOC15_REG_FIELD(MMEA6_EDC_CNT2, MAM_D0MEM_SED_COUNT), 1443 SOC15_REG_FIELD(MMEA6_EDC_CNT2, MAM_D0MEM_DED_COUNT), 1444 }, 1445 { "MMEA6_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT2), 1446 SOC15_REG_FIELD(MMEA6_EDC_CNT2, MAM_D1MEM_SED_COUNT), 1447 SOC15_REG_FIELD(MMEA6_EDC_CNT2, MAM_D1MEM_DED_COUNT), 1448 }, 1449 { "MMEA6_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT2), 1450 SOC15_REG_FIELD(MMEA6_EDC_CNT2, MAM_D2MEM_SED_COUNT), 1451 SOC15_REG_FIELD(MMEA6_EDC_CNT2, MAM_D2MEM_DED_COUNT), 1452 }, 1453 { "MMEA6_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT2), 1454 SOC15_REG_FIELD(MMEA6_EDC_CNT2, MAM_D3MEM_SED_COUNT), 1455 SOC15_REG_FIELD(MMEA6_EDC_CNT2, MAM_D3MEM_DED_COUNT), 1456 }, 1457 1458 /* MMHUB Range 7*/ 1459 { "MMEA7_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT), 1460 SOC15_REG_FIELD(MMEA7_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT), 1461 SOC15_REG_FIELD(MMEA7_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT), 1462 }, 1463 { "MMEA7_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT), 1464 SOC15_REG_FIELD(MMEA7_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT), 1465 SOC15_REG_FIELD(MMEA7_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT), 1466 }, 1467 { "MMEA7_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT), 1468 SOC15_REG_FIELD(MMEA7_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT), 1469 SOC15_REG_FIELD(MMEA7_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT), 1470 }, 1471 { "MMEA7_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT), 1472 SOC15_REG_FIELD(MMEA7_EDC_CNT, RRET_TAGMEM_SEC_COUNT), 1473 SOC15_REG_FIELD(MMEA7_EDC_CNT, RRET_TAGMEM_DED_COUNT), 1474 }, 1475 { "MMEA7_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT), 1476 SOC15_REG_FIELD(MMEA7_EDC_CNT, WRET_TAGMEM_SEC_COUNT), 1477 SOC15_REG_FIELD(MMEA7_EDC_CNT, WRET_TAGMEM_DED_COUNT), 1478 }, 1479 { "MMEA7_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT), 1480 SOC15_REG_FIELD(MMEA7_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT), 1481 0, 0, 1482 }, 1483 { "MMEA7_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT), 1484 SOC15_REG_FIELD(MMEA7_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT), 1485 0, 0, 1486 }, 1487 { "MMEA7_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT), 1488 SOC15_REG_FIELD(MMEA7_EDC_CNT, IORD_CMDMEM_SED_COUNT), 1489 0, 0, 1490 }, 1491 { "MMEA7_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT), 1492 SOC15_REG_FIELD(MMEA7_EDC_CNT, IOWR_CMDMEM_SED_COUNT), 1493 0, 0, 1494 }, 1495 { "MMEA7_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT), 1496 SOC15_REG_FIELD(MMEA7_EDC_CNT, IOWR_DATAMEM_SED_COUNT), 1497 0, 0, 1498 }, 1499 { "MMEA7_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT2), 1500 SOC15_REG_FIELD(MMEA7_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT), 1501 SOC15_REG_FIELD(MMEA7_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT), 1502 }, 1503 { "MMEA7_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT2), 1504 SOC15_REG_FIELD(MMEA7_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT), 1505 SOC15_REG_FIELD(MMEA7_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT), 1506 }, 1507 { "MMEA7_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT2), 1508 SOC15_REG_FIELD(MMEA7_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT), 1509 SOC15_REG_FIELD(MMEA7_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT), 1510 }, 1511 { "MMEA7_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT2), 1512 SOC15_REG_FIELD(MMEA7_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT), 1513 0, 0, 1514 }, 1515 { "MMEA7_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT2), 1516 SOC15_REG_FIELD(MMEA7_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT), 1517 0, 0, 1518 }, 1519 { "MMEA7_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT3), 1520 0, 0, 1521 SOC15_REG_FIELD(MMEA7_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT), 1522 }, 1523 { "MMEA7_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT3), 1524 0, 0, 1525 SOC15_REG_FIELD(MMEA7_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT), 1526 }, 1527 { "MMEA7_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT3), 1528 0, 0, 1529 SOC15_REG_FIELD(MMEA7_EDC_CNT3, IORD_CMDMEM_DED_COUNT), 1530 }, 1531 { "MMEA7_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT3), 1532 0, 0, 1533 SOC15_REG_FIELD(MMEA7_EDC_CNT3, IOWR_CMDMEM_DED_COUNT), 1534 }, 1535 { "MMEA7_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT3), 1536 0, 0, 1537 SOC15_REG_FIELD(MMEA7_EDC_CNT3, IOWR_DATAMEM_DED_COUNT), 1538 }, 1539 { "MMEA7_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT3), 1540 0, 0, 1541 SOC15_REG_FIELD(MMEA7_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT), 1542 }, 1543 { "MMEA7_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT3), 1544 0, 0, 1545 SOC15_REG_FIELD(MMEA7_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT), 1546 }, 1547 { "MMEA7_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT2), 1548 SOC15_REG_FIELD(MMEA7_EDC_CNT2, MAM_D0MEM_SED_COUNT), 1549 SOC15_REG_FIELD(MMEA7_EDC_CNT2, MAM_D0MEM_DED_COUNT), 1550 }, 1551 { "MMEA7_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT2), 1552 SOC15_REG_FIELD(MMEA7_EDC_CNT2, MAM_D1MEM_SED_COUNT), 1553 SOC15_REG_FIELD(MMEA7_EDC_CNT2, MAM_D1MEM_DED_COUNT), 1554 }, 1555 { "MMEA7_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT2), 1556 SOC15_REG_FIELD(MMEA7_EDC_CNT2, MAM_D2MEM_SED_COUNT), 1557 SOC15_REG_FIELD(MMEA7_EDC_CNT2, MAM_D2MEM_DED_COUNT), 1558 }, 1559 { "MMEA7_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT2), 1560 SOC15_REG_FIELD(MMEA7_EDC_CNT2, MAM_D3MEM_SED_COUNT), 1561 SOC15_REG_FIELD(MMEA7_EDC_CNT2, MAM_D3MEM_DED_COUNT), 1562 } 1563 }; 1564 1565 static const struct soc15_reg_entry mmhub_v9_4_edc_cnt_regs[] = { 1566 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT), 0, 0, 0 }, 1567 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2), 0, 0, 0 }, 1568 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT3), 0, 0, 0 }, 1569 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT), 0, 0, 0 }, 1570 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2), 0, 0, 0 }, 1571 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT3), 0, 0, 0 }, 1572 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT), 0, 0, 0 }, 1573 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT2), 0, 0, 0 }, 1574 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT3), 0, 0, 0 }, 1575 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT), 0, 0, 0 }, 1576 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT2), 0, 0, 0 }, 1577 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT3), 0, 0, 0 }, 1578 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT), 0, 0, 0 }, 1579 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT2), 0, 0, 0 }, 1580 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT3), 0, 0, 0 }, 1581 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT), 0, 0, 0 }, 1582 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT2), 0, 0, 0 }, 1583 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT3), 0, 0, 0 }, 1584 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT), 0, 0, 0 }, 1585 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT2), 0, 0, 0 }, 1586 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT3), 0, 0, 0 }, 1587 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT), 0, 0, 0 }, 1588 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT2), 0, 0, 0 }, 1589 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT3), 0, 0, 0 }, 1590 }; 1591 1592 static int mmhub_v9_4_get_ras_error_count(struct amdgpu_device *adev, 1593 const struct soc15_reg_entry *reg, 1594 uint32_t value, 1595 uint32_t *sec_count, 1596 uint32_t *ded_count) 1597 { 1598 uint32_t i; 1599 uint32_t sec_cnt, ded_cnt; 1600 1601 for (i = 0; i < ARRAY_SIZE(mmhub_v9_4_ras_fields); i++) { 1602 if (mmhub_v9_4_ras_fields[i].reg_offset != reg->reg_offset) 1603 continue; 1604 1605 sec_cnt = (value & 1606 mmhub_v9_4_ras_fields[i].sec_count_mask) >> 1607 mmhub_v9_4_ras_fields[i].sec_count_shift; 1608 if (sec_cnt) { 1609 dev_info(adev->dev, "MMHUB SubBlock %s, SEC %d\n", 1610 mmhub_v9_4_ras_fields[i].name, 1611 sec_cnt); 1612 *sec_count += sec_cnt; 1613 } 1614 1615 ded_cnt = (value & 1616 mmhub_v9_4_ras_fields[i].ded_count_mask) >> 1617 mmhub_v9_4_ras_fields[i].ded_count_shift; 1618 if (ded_cnt) { 1619 dev_info(adev->dev, "MMHUB SubBlock %s, DED %d\n", 1620 mmhub_v9_4_ras_fields[i].name, 1621 ded_cnt); 1622 *ded_count += ded_cnt; 1623 } 1624 } 1625 1626 return 0; 1627 } 1628 1629 static void mmhub_v9_4_query_ras_error_count(struct amdgpu_device *adev, 1630 void *ras_error_status) 1631 { 1632 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 1633 uint32_t sec_count = 0, ded_count = 0; 1634 uint32_t i; 1635 uint32_t reg_value; 1636 1637 err_data->ue_count = 0; 1638 err_data->ce_count = 0; 1639 1640 for (i = 0; i < ARRAY_SIZE(mmhub_v9_4_edc_cnt_regs); i++) { 1641 reg_value = 1642 RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v9_4_edc_cnt_regs[i])); 1643 if (reg_value) 1644 mmhub_v9_4_get_ras_error_count(adev, &mmhub_v9_4_edc_cnt_regs[i], 1645 reg_value, &sec_count, &ded_count); 1646 } 1647 1648 err_data->ce_count += sec_count; 1649 err_data->ue_count += ded_count; 1650 } 1651 1652 static void mmhub_v9_4_reset_ras_error_count(struct amdgpu_device *adev) 1653 { 1654 uint32_t i; 1655 1656 /* read back edc counter registers to reset the counters to 0 */ 1657 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__MMHUB)) { 1658 for (i = 0; i < ARRAY_SIZE(mmhub_v9_4_edc_cnt_regs); i++) 1659 RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v9_4_edc_cnt_regs[i])); 1660 } 1661 } 1662 1663 static const struct soc15_reg_entry mmhub_v9_4_err_status_regs[] = { 1664 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_ERR_STATUS), 0, 0, 0 }, 1665 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_ERR_STATUS), 0, 0, 0 }, 1666 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_ERR_STATUS), 0, 0, 0 }, 1667 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_ERR_STATUS), 0, 0, 0 }, 1668 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_ERR_STATUS), 0, 0, 0 }, 1669 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_ERR_STATUS), 0, 0, 0 }, 1670 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_ERR_STATUS), 0, 0, 0 }, 1671 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_ERR_STATUS), 0, 0, 0 }, 1672 }; 1673 1674 static void mmhub_v9_4_query_ras_error_status(struct amdgpu_device *adev) 1675 { 1676 int i; 1677 uint32_t reg_value; 1678 1679 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__MMHUB)) 1680 return; 1681 1682 for (i = 0; i < ARRAY_SIZE(mmhub_v9_4_err_status_regs); i++) { 1683 reg_value = 1684 RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v9_4_err_status_regs[i])); 1685 if (REG_GET_FIELD(reg_value, MMEA0_ERR_STATUS, SDP_RDRSP_STATUS) || 1686 REG_GET_FIELD(reg_value, MMEA0_ERR_STATUS, SDP_WRRSP_STATUS) || 1687 REG_GET_FIELD(reg_value, MMEA0_ERR_STATUS, SDP_RDRSP_DATAPARITY_ERROR)) { 1688 /* SDP read/write error/parity error in FUE_IS_FATAL mode 1689 * can cause system fatal error in arcturas. Harvest the error 1690 * status before GPU reset */ 1691 dev_warn(adev->dev, "MMHUB EA err detected at instance: %d, status: 0x%x!\n", 1692 i, reg_value); 1693 } 1694 } 1695 } 1696 1697 const struct amdgpu_ras_block_hw_ops mmhub_v9_4_ras_hw_ops = { 1698 .query_ras_error_count = mmhub_v9_4_query_ras_error_count, 1699 .reset_ras_error_count = mmhub_v9_4_reset_ras_error_count, 1700 .query_ras_error_status = mmhub_v9_4_query_ras_error_status, 1701 }; 1702 1703 struct amdgpu_mmhub_ras mmhub_v9_4_ras = { 1704 .ras_block = { 1705 .hw_ops = &mmhub_v9_4_ras_hw_ops, 1706 }, 1707 }; 1708 1709 const struct amdgpu_mmhub_funcs mmhub_v9_4_funcs = { 1710 .get_fb_location = mmhub_v9_4_get_fb_location, 1711 .init = mmhub_v9_4_init, 1712 .gart_enable = mmhub_v9_4_gart_enable, 1713 .set_fault_enable_default = mmhub_v9_4_set_fault_enable_default, 1714 .gart_disable = mmhub_v9_4_gart_disable, 1715 .set_clockgating = mmhub_v9_4_set_clockgating, 1716 .get_clockgating = mmhub_v9_4_get_clockgating, 1717 .setup_vm_pt_regs = mmhub_v9_4_setup_vm_pt_regs, 1718 }; 1719