1 /* 2 * Copyright 2025 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "amdgpu.h" 25 #include "mmhub_v4_2_0.h" 26 27 #include "mmhub/mmhub_4_2_0_offset.h" 28 #include "mmhub/mmhub_4_2_0_sh_mask.h" 29 30 #include "soc15_common.h" 31 #include "soc24_enum.h" 32 33 #define regMMVM_L2_CNTL3_DEFAULT 0x80100007 34 #define regMMVM_L2_CNTL4_DEFAULT 0x000000c1 35 #define regMMVM_L2_CNTL5_DEFAULT 0x00003fe0 36 37 static const char *mmhub_client_ids_v4_2_0[][2] = { 38 [0][0] = "VMC", 39 [2][0] = "MPNHT", 40 [7][0] = "MPIFOE", 41 [8][0] = "MPIO", 42 [11][0] = "JPEG0", 43 [12][0] = "VCN0", 44 [13][0] = "VCNU0", 45 [14][0] = "VSCH0", 46 [15][0] = "LSDMA", 47 [32+5][0] = "MPRAS", 48 [32+6][0] = "MP1", 49 [32+7][0] = "MP0", 50 [32+11][0] = "JPEG1", 51 [32+12][0] = "VCN1", 52 [32+13][0] = "VCNU1", 53 [32+14][0] = "VSCH1", 54 [2][1] = "MPNHT", 55 [3][1] = "DBGU0", 56 [7][1] = "MPIFOE", 57 [8][1] = "MPIO", 58 [10][1] = "UTCL2_NHT", 59 [11][1] = "JPEG0", 60 [12][1] = "VCN0", 61 [13][1] = "VCNU0", 62 [14][1] = "VSCH0", 63 [15][1] = "LSDMA", 64 [32+3][1] = "DBGU1", 65 [32+4][1] = "DBGU2", 66 [32+5][1] = "MPRAS", 67 [32+6][1] = "MP1", 68 [32+7][1] = "MP0", 69 [32+8][1] = "IH", 70 [32+11][1] = "JPEG1", 71 [32+12][1] = "VCN1", 72 [32+13][1] = "VCNU1", 73 [32+14][1] = "VSCH1", 74 }; 75 76 static int mmhub_v4_2_0_get_xgmi_info(struct amdgpu_device *adev) 77 { 78 u32 max_num_physical_nodes; 79 u32 max_physical_node_id; 80 u32 xgmi_lfb_cntl; 81 u32 max_region; 82 u64 seg_size; 83 84 /* limit this callback to A + A configuration only */ 85 if (!adev->gmc.xgmi.connected_to_cpu) 86 return 0; 87 88 xgmi_lfb_cntl = RREG32_SOC15(MMHUB, GET_INST(MMHUB, 0), 89 regMMMC_VM_XGMI_LFB_CNTL); 90 seg_size = REG_GET_FIELD( 91 RREG32_SOC15(MMHUB, GET_INST(MMHUB, 0), regMMMC_VM_XGMI_LFB_SIZE), 92 MMMC_VM_XGMI_LFB_SIZE, PF_LFB_SIZE) << 24; 93 max_region = 94 REG_GET_FIELD(xgmi_lfb_cntl, MMMC_VM_XGMI_LFB_CNTL, PF_MAX_REGION); 95 96 max_num_physical_nodes = 4; 97 max_physical_node_id = 3; 98 99 adev->gmc.xgmi.num_physical_nodes = max_region + 1; 100 101 if (adev->gmc.xgmi.num_physical_nodes > max_num_physical_nodes) 102 return -EINVAL; 103 104 adev->gmc.xgmi.physical_node_id = 105 REG_GET_FIELD(xgmi_lfb_cntl, MMMC_VM_XGMI_LFB_CNTL, PF_LFB_REGION); 106 107 if (adev->gmc.xgmi.physical_node_id > max_physical_node_id) 108 return -EINVAL; 109 110 adev->gmc.xgmi.node_segment_size = seg_size; 111 112 return 0; 113 } 114 115 static u64 mmhub_v4_2_0_get_fb_location(struct amdgpu_device *adev) 116 { 117 u64 base; 118 119 base = RREG32_SOC15(MMHUB, GET_INST(MMHUB, 0), 120 regMMMC_VM_FB_LOCATION_BASE_LO32); 121 base &= MMMC_VM_FB_LOCATION_BASE_LO32__FB_BASE_LO32_MASK; 122 base <<= 24; 123 124 base |= ((u64)(MMMC_VM_FB_LOCATION_BASE_HI32__FB_BASE_HI1_MASK & 125 RREG32_SOC15(MMHUB, GET_INST(MMHUB, 0), 126 regMMMC_VM_FB_LOCATION_BASE_HI32)) << 56); 127 128 return base; 129 } 130 131 static u64 mmhub_v4_2_0_get_mc_fb_offset(struct amdgpu_device *adev) 132 { 133 return (u64)RREG32_SOC15(MMHUB, GET_INST(MMHUB, 0), 134 regMMMC_VM_FB_OFFSET) << 24; 135 } 136 137 static void mmhub_v4_2_0_mid_setup_vm_pt_regs(struct amdgpu_device *adev, 138 uint32_t vmid, 139 uint64_t page_table_base, 140 uint32_t mid_mask) 141 { 142 struct amdgpu_vmhub *hub; 143 int i; 144 145 for_each_inst(i, mid_mask) { 146 hub = &adev->vmhub[AMDGPU_MMHUB0(i)]; 147 WREG32_SOC15_OFFSET(MMHUB, GET_INST(MMHUB, i), 148 regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, 149 hub->ctx_addr_distance * vmid, 150 lower_32_bits(page_table_base)); 151 152 WREG32_SOC15_OFFSET(MMHUB, GET_INST(MMHUB, i), 153 regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, 154 hub->ctx_addr_distance * vmid, 155 upper_32_bits(page_table_base)); 156 } 157 } 158 159 static void mmhub_v4_2_0_setup_vm_pt_regs(struct amdgpu_device *adev, 160 uint32_t vmid, 161 uint64_t page_table_base) 162 { 163 uint32_t mid_mask; 164 165 mid_mask = adev->aid_mask; 166 mmhub_v4_2_0_mid_setup_vm_pt_regs(adev, vmid, 167 page_table_base, 168 mid_mask); 169 } 170 171 static void mmhub_v4_2_0_mid_init_gart_aperture_regs(struct amdgpu_device *adev, 172 uint32_t mid_mask) 173 { 174 uint64_t pt_base; 175 int i; 176 177 if (adev->gmc.pdb0_bo) 178 pt_base = amdgpu_gmc_pd_addr(adev->gmc.pdb0_bo); 179 else 180 pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); 181 182 mmhub_v4_2_0_mid_setup_vm_pt_regs(adev, 0, pt_base, mid_mask); 183 184 for_each_inst(i, mid_mask) { 185 if (adev->gmc.pdb0_bo) { 186 WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), 187 regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, 188 (u32)(adev->gmc.fb_start >> 12)); 189 WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), 190 regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, 191 (u32)(adev->gmc.fb_start >> 44)); 192 193 WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), 194 regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, 195 (u32)(adev->gmc.gart_end >> 12)); 196 WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), 197 regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, 198 (u32)(adev->gmc.gart_end >> 44)); 199 } else { 200 WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), 201 regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, 202 (u32)(adev->gmc.gart_start >> 12)); 203 WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), 204 regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, 205 (u32)(adev->gmc.gart_start >> 44)); 206 207 WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), 208 regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, 209 (u32)(adev->gmc.gart_end >> 12)); 210 WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), 211 regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, 212 (u32)(adev->gmc.gart_end >> 44)); 213 } 214 } 215 } 216 217 static void mmhub_v4_2_0_mid_init_system_aperture_regs(struct amdgpu_device *adev, 218 uint32_t mid_mask) 219 { 220 uint64_t value; 221 uint32_t tmp; 222 int i; 223 224 /* 225 * the new L1 policy will block SRIOV guest from writing 226 * these regs, and they will be programed at host. 227 * so skip programing these regs. 228 */ 229 if (amdgpu_sriov_vf(adev)) 230 return; 231 232 for_each_inst(i, mid_mask) { 233 if (adev->gmc.pdb0_bo) { 234 /* Disable agp and system aperture 235 * when vmid0 page table is enabled */ 236 WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), 237 regMMMC_VM_FB_LOCATION_TOP_LO32, 0); 238 WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), 239 regMMMC_VM_FB_LOCATION_TOP_HI32, 0); 240 WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), 241 regMMMC_VM_FB_LOCATION_BASE_LO32, 242 0xFFFFFFFF); 243 WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), 244 regMMMC_VM_FB_LOCATION_BASE_HI32, 1); 245 WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), 246 regMMMC_VM_AGP_TOP_LO32, 0); 247 WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), 248 regMMMC_VM_AGP_TOP_HI32, 0); 249 WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), 250 regMMMC_VM_AGP_BOT_LO32, 251 0xFFFFFFFF); 252 WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), 253 regMMMC_VM_AGP_BOT_HI32, 1); 254 WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), 255 regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR_LO32, 256 0xFFFFFFFF); 257 WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), 258 regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR_HI32, 259 0x7F); 260 WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), 261 regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR_LO32, 0); 262 WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), 263 regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR_HI32, 0); 264 } else { 265 /* Program the AGP BAR */ 266 WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), 267 regMMMC_VM_AGP_BASE_LO32, 0); 268 WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), 269 regMMMC_VM_AGP_BASE_HI32, 0); 270 WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), 271 regMMMC_VM_AGP_BOT_LO32, 272 lower_32_bits(adev->gmc.agp_start >> 24)); 273 WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), 274 regMMMC_VM_AGP_BOT_HI32, 275 upper_32_bits(adev->gmc.agp_start >> 24)); 276 WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), 277 regMMMC_VM_AGP_TOP_LO32, 278 lower_32_bits(adev->gmc.agp_end >> 24)); 279 WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), 280 regMMMC_VM_AGP_TOP_HI32, 281 upper_32_bits(adev->gmc.agp_end >> 24)); 282 283 /* Program the system aperture low logical page number. */ 284 WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), 285 regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR_LO32, 286 lower_32_bits(min(adev->gmc.fb_start, 287 adev->gmc.agp_start) >> 18)); 288 WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), 289 regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR_HI32, 290 upper_32_bits(min(adev->gmc.fb_start, 291 adev->gmc.agp_start) >> 18)); 292 WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), 293 regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR_LO32, 294 lower_32_bits(max(adev->gmc.fb_end, 295 adev->gmc.agp_end) >> 18)); 296 WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), 297 regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR_HI32, 298 upper_32_bits(max(adev->gmc.fb_end, 299 adev->gmc.agp_end) >> 18)); 300 } 301 302 /* Set default page address. */ 303 value = amdgpu_gmc_vram_mc2pa(adev, adev->mem_scratch.gpu_addr); 304 WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), 305 regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 306 (u32)(value >> 12)); 307 WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), 308 regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 309 (u32)(value >> 44)); 310 311 /* Program "protection fault". */ 312 WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), 313 regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, 314 (u32)(adev->dummy_page_addr >> 12)); 315 WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), 316 regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, 317 (u32)((u64)adev->dummy_page_addr >> 44)); 318 319 tmp = RREG32_SOC15(MMHUB, GET_INST(MMHUB, i), 320 regMMVM_L2_PROTECTION_FAULT_CNTL2); 321 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2, 322 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); 323 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2, 324 ENABLE_RETRY_FAULT_INTERRUPT, 0x1); 325 WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), 326 regMMVM_L2_PROTECTION_FAULT_CNTL2, tmp); 327 } 328 } 329 330 static void mmhub_v4_2_0_mid_init_tlb_regs(struct amdgpu_device *adev, 331 uint32_t mid_mask) 332 { 333 uint32_t tmp; 334 int i; 335 336 for_each_inst(i, mid_mask) { 337 /* Setup TLB control */ 338 tmp = RREG32_SOC15(MMHUB, GET_INST(MMHUB, i), 339 regMMMC_VM_MX_L1_TLB_CNTL); 340 341 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); 342 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); 343 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, 344 ENABLE_ADVANCED_DRIVER_MODEL, 1); 345 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, 346 SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); 347 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0); 348 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, 349 MTYPE, MTYPE_UC); /* UC, uncached */ 350 351 WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), 352 regMMMC_VM_MX_L1_TLB_CNTL, tmp); 353 } 354 } 355 356 static void mmhub_v4_2_0_mid_init_cache_regs(struct amdgpu_device *adev, 357 uint32_t mid_mask) 358 { 359 uint32_t tmp; 360 int i; 361 362 /* These registers are not accessible to VF-SRIOV. 363 * The PF will program them instead. 364 */ 365 if (amdgpu_sriov_vf(adev)) 366 return; 367 368 for_each_inst(i, mid_mask) { 369 /* Setup L2 cache */ 370 tmp = RREG32_SOC15(MMHUB, GET_INST(MMHUB, i), regMMVM_L2_CNTL); 371 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1); 372 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0); 373 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, 374 ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1); 375 /* XXX for emulation, Refer to closed source code.*/ 376 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, 377 L2_PDE0_CACHE_TAG_GENERATION_MODE, 0); 378 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, 379 PDE_FAULT_CLASSIFICATION, 0); 380 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, 381 CONTEXT1_IDENTITY_ACCESS_MODE, 1); 382 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, 383 IDENTITY_MODE_FRAGMENT_SIZE, 0); 384 WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), regMMVM_L2_CNTL, tmp); 385 386 tmp = RREG32_SOC15(MMHUB, GET_INST(MMHUB, i), regMMVM_L2_CNTL2); 387 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, 388 INVALIDATE_ALL_L1_TLBS, 1); 389 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, 390 INVALIDATE_L2_CACHE, 1); 391 WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), regMMVM_L2_CNTL2, tmp); 392 393 tmp = regMMVM_L2_CNTL3_DEFAULT; 394 if (adev->gmc.translate_further) { 395 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12); 396 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, 397 L2_CACHE_BIGK_FRAGMENT_SIZE, 9); 398 } else { 399 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9); 400 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, 401 L2_CACHE_BIGK_FRAGMENT_SIZE, 6); 402 } 403 WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), regMMVM_L2_CNTL3, tmp); 404 405 tmp = regMMVM_L2_CNTL4_DEFAULT; 406 /* For AMD APP APUs setup WC memory */ 407 if (adev->gmc.xgmi.connected_to_cpu || adev->gmc.is_app_apu) { 408 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, 409 VMC_TAP_PDE_REQUEST_PHYSICAL, 1); 410 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, 411 VMC_TAP_PTE_REQUEST_PHYSICAL, 1); 412 } else { 413 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, 414 VMC_TAP_PDE_REQUEST_PHYSICAL, 0); 415 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, 416 VMC_TAP_PTE_REQUEST_PHYSICAL, 0); 417 } 418 WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), regMMVM_L2_CNTL4, tmp); 419 420 tmp = regMMVM_L2_CNTL5_DEFAULT; 421 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, 422 L2_CACHE_SMALLK_FRAGMENT_SIZE, 0); 423 WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), regMMVM_L2_CNTL5, tmp); 424 } 425 } 426 427 static void mmhub_v4_2_0_mid_enable_system_domain(struct amdgpu_device *adev, 428 uint32_t mid_mask) 429 { 430 uint32_t tmp; 431 int i; 432 433 for_each_inst(i, mid_mask) { 434 tmp = RREG32_SOC15(MMHUB, GET_INST(MMHUB, i), 435 regMMVM_CONTEXT0_CNTL); 436 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, 437 ENABLE_CONTEXT, 1); 438 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, 439 PAGE_TABLE_DEPTH, adev->gmc.vmid0_page_table_depth); 440 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, 441 PAGE_TABLE_BLOCK_SIZE, 442 adev->gmc.vmid0_page_table_block_size); 443 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, 444 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0); 445 WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), 446 regMMVM_CONTEXT0_CNTL, tmp); 447 } 448 } 449 450 static void mmhub_v4_2_0_mid_disable_identity_aperture(struct amdgpu_device *adev, 451 uint32_t mid_mask) 452 { 453 int i; 454 455 /* These registers are not accessible to VF-SRIOV. 456 * The PF will program them instead. 457 */ 458 if (amdgpu_sriov_vf(adev)) 459 return; 460 461 for_each_inst(i, mid_mask) { 462 WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), 463 regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32, 464 0xFFFFFFFF); 465 WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), 466 regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32, 467 0x00001FFF); 468 469 WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), 470 regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 471 0); 472 WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), 473 regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 474 0); 475 476 WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), 477 regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 478 0); 479 WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), 480 regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 481 0); 482 } 483 } 484 485 static void mmhub_v4_2_0_mid_setup_vmid_config(struct amdgpu_device *adev, 486 uint32_t mid_mask) 487 { 488 struct amdgpu_vmhub *hub; 489 uint32_t tmp; 490 int i, j; 491 492 for_each_inst(j, mid_mask) { 493 hub = &adev->vmhub[AMDGPU_MMHUB0(j)]; 494 for (i = 0; i <= 14; i++) { 495 tmp = RREG32_SOC15_OFFSET(MMHUB, GET_INST(MMHUB, j), 496 regMMVM_CONTEXT1_CNTL, 497 i * hub->ctx_distance); 498 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); 499 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 500 adev->vm_manager.num_level); 501 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 502 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 503 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 504 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 505 1); 506 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 507 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 508 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 509 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 510 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 511 READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 512 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 513 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 514 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 515 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 516 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 517 PAGE_TABLE_BLOCK_SIZE, 518 adev->vm_manager.block_size - 9); 519 /* Send no-retry XNACK on fault to suppress VM fault storm. */ 520 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 521 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 522 !adev->gmc.noretry); 523 WREG32_SOC15_OFFSET(MMHUB, GET_INST(MMHUB, j), regMMVM_CONTEXT1_CNTL, 524 i * hub->ctx_distance, tmp); 525 WREG32_SOC15_OFFSET(MMHUB, GET_INST(MMHUB, j), regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, 526 i * hub->ctx_addr_distance, 0); 527 WREG32_SOC15_OFFSET(MMHUB, GET_INST(MMHUB, j), regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, 528 i * hub->ctx_addr_distance, 0); 529 WREG32_SOC15_OFFSET(MMHUB, GET_INST(MMHUB, j), regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, 530 i * hub->ctx_addr_distance, 531 lower_32_bits(adev->vm_manager.max_pfn - 1)); 532 WREG32_SOC15_OFFSET(MMHUB, GET_INST(MMHUB, j), regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, 533 i * hub->ctx_addr_distance, 534 upper_32_bits(adev->vm_manager.max_pfn - 1)); 535 } 536 } 537 538 hub->vm_cntx_cntl = tmp; 539 } 540 541 static void mmhub_v4_2_0_mid_program_invalidation(struct amdgpu_device *adev, 542 uint32_t mid_mask) 543 { 544 struct amdgpu_vmhub *hub; 545 unsigned int i, j; 546 547 for_each_inst(j, mid_mask) { 548 hub = &adev->vmhub[AMDGPU_MMHUB0(j)]; 549 550 for (i = 0; i < 18; ++i) { 551 WREG32_SOC15_OFFSET(MMHUB, GET_INST(MMHUB, j), 552 regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32, 553 i * hub->eng_addr_distance, 0xffffffff); 554 WREG32_SOC15_OFFSET(MMHUB, GET_INST(MMHUB, j), 555 regMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32, 556 i * hub->eng_addr_distance, 0x3fff); 557 } 558 } 559 } 560 561 static int mmhub_v4_2_0_mid_gart_enable(struct amdgpu_device *adev, 562 uint32_t mid_mask) 563 { 564 /* GART Enable. */ 565 mmhub_v4_2_0_mid_init_gart_aperture_regs(adev, mid_mask); 566 mmhub_v4_2_0_mid_init_system_aperture_regs(adev, mid_mask); 567 mmhub_v4_2_0_mid_init_tlb_regs(adev, mid_mask); 568 mmhub_v4_2_0_mid_init_cache_regs(adev, mid_mask); 569 570 mmhub_v4_2_0_mid_enable_system_domain(adev, mid_mask); 571 mmhub_v4_2_0_mid_disable_identity_aperture(adev, mid_mask); 572 mmhub_v4_2_0_mid_setup_vmid_config(adev, mid_mask); 573 mmhub_v4_2_0_mid_program_invalidation(adev, mid_mask); 574 575 return 0; 576 } 577 static int mmhub_v4_2_0_gart_enable(struct amdgpu_device *adev) 578 { 579 uint32_t mid_mask; 580 581 mid_mask = adev->aid_mask; 582 return mmhub_v4_2_0_mid_gart_enable(adev, mid_mask); 583 } 584 585 static void mmhub_v4_2_0_mid_gart_disable(struct amdgpu_device *adev, 586 uint32_t mid_mask) 587 { 588 struct amdgpu_vmhub *hub; 589 u32 tmp; 590 u32 i, j; 591 592 for_each_inst(j, mid_mask) { 593 hub = &adev->vmhub[AMDGPU_MMHUB0(j)]; 594 /* Disable all tables */ 595 for (i = 0; i < 16; i++) 596 WREG32_SOC15_OFFSET(MMHUB, GET_INST(MMHUB, j), 597 regMMVM_CONTEXT0_CNTL, 598 i * hub->ctx_distance, 0); 599 600 /* Setup TLB control */ 601 tmp = RREG32_SOC15(MMHUB, GET_INST(MMHUB, j), 602 regMMMC_VM_MX_L1_TLB_CNTL); 603 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, 604 ENABLE_L1_TLB, 0); 605 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, 606 ENABLE_ADVANCED_DRIVER_MODEL, 0); 607 WREG32_SOC15(MMHUB, GET_INST(MMHUB, j), 608 regMMMC_VM_MX_L1_TLB_CNTL, tmp); 609 610 /* Setup L2 cache */ 611 tmp = RREG32_SOC15(MMHUB, GET_INST(MMHUB, j), regMMVM_L2_CNTL); 612 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0); 613 WREG32_SOC15(MMHUB, GET_INST(MMHUB, j), regMMVM_L2_CNTL, tmp); 614 WREG32_SOC15(MMHUB, GET_INST(MMHUB, j), regMMVM_L2_CNTL3, 0); 615 } 616 } 617 618 static void mmhub_v4_2_0_gart_disable(struct amdgpu_device *adev) 619 { 620 uint32_t mid_mask; 621 622 mid_mask = adev->aid_mask; 623 mmhub_v4_2_0_mid_gart_disable(adev, mid_mask); 624 } 625 626 static void 627 mmhub_v4_2_0_mid_set_fault_enable_default(struct amdgpu_device *adev, 628 bool value, uint32_t mid_mask) 629 { 630 u32 tmp; 631 int i; 632 633 /* These registers are not accessible to VF-SRIOV. 634 * The PF will program them instead. 635 */ 636 if (amdgpu_sriov_vf(adev)) 637 return; 638 639 for_each_inst(i, mid_mask) { 640 tmp = RREG32_SOC15(MMHUB, GET_INST(MMHUB, i), 641 regMMVM_L2_PROTECTION_FAULT_CNTL_LO32); 642 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL_LO32, 643 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 644 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL_LO32, 645 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); 646 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL_LO32, 647 PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value); 648 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL_LO32, 649 PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value); 650 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL_LO32, 651 TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT, 652 value); 653 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL_LO32, 654 NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value); 655 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL_LO32, 656 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 657 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL_LO32, 658 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); 659 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL_LO32, 660 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); 661 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL_LO32, 662 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 663 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL_LO32, 664 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 665 if (!value) { 666 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL_LO32, 667 CRASH_ON_NO_RETRY_FAULT, 1); 668 } 669 WREG32_SOC15(MMHUB, GET_INST(MMHUB, i), 670 regMMVM_L2_PROTECTION_FAULT_CNTL_LO32, tmp); 671 } 672 } 673 674 675 /** 676 * mmhub_v4_2_0_set_fault_enable_default - update GART/VM fault handling 677 * 678 * @adev: amdgpu_device pointer 679 * @value: true redirects VM faults to the default page 680 */ 681 static void 682 mmhub_v4_2_0_set_fault_enable_default(struct amdgpu_device *adev, 683 bool value) 684 { 685 uint32_t mid_mask; 686 687 mid_mask = adev->aid_mask; 688 mmhub_v4_2_0_mid_set_fault_enable_default(adev, value, mid_mask); 689 } 690 691 static uint32_t mmhub_v4_2_0_get_invalidate_req(unsigned int vmid, 692 uint32_t flush_type) 693 { 694 u32 req = 0; 695 696 /* invalidate using legacy mode on vmid*/ 697 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, 698 PER_VMID_INVALIDATE_REQ, 1 << vmid); 699 /* Only use legacy inv on mmhub side */ 700 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, 0); 701 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); 702 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); 703 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); 704 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); 705 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE3, 1); 706 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); 707 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, 708 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0); 709 710 return req; 711 } 712 713 /*TODO: l2 protection fault status is increased to 64bits. 714 * some critical fields like FED are moved to STATUS_HI32 */ 715 static void 716 mmhub_v4_2_0_print_l2_protection_fault_status(struct amdgpu_device *adev, 717 uint32_t status) 718 { 719 uint32_t cid, rw; 720 const char *mmhub_cid; 721 722 cid = REG_GET_FIELD(status, 723 MMVM_L2_PROTECTION_FAULT_STATUS_LO32, CID); 724 rw = REG_GET_FIELD(status, 725 MMVM_L2_PROTECTION_FAULT_STATUS_LO32, RW); 726 727 dev_err(adev->dev, 728 "MMVM_L2_PROTECTION_FAULT_STATUS_LO32:0x%08X\n", 729 status); 730 mmhub_cid = amdgpu_mmhub_client_name(&adev->mmhub, cid, rw); 731 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", 732 mmhub_cid ? mmhub_cid : "unknown", cid); 733 dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n", 734 REG_GET_FIELD(status, 735 MMVM_L2_PROTECTION_FAULT_STATUS_LO32, MORE_FAULTS)); 736 dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n", 737 REG_GET_FIELD(status, 738 MMVM_L2_PROTECTION_FAULT_STATUS_LO32, WALKER_ERROR)); 739 dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n", 740 REG_GET_FIELD(status, 741 MMVM_L2_PROTECTION_FAULT_STATUS_LO32, PERMISSION_FAULTS)); 742 dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n", 743 REG_GET_FIELD(status, 744 MMVM_L2_PROTECTION_FAULT_STATUS_LO32, MAPPING_ERROR)); 745 dev_err(adev->dev, "\t RW: 0x%x\n", rw); 746 } 747 748 749 static const struct amdgpu_vmhub_funcs mmhub_v4_2_0_vmhub_funcs = { 750 .print_l2_protection_fault_status = mmhub_v4_2_0_print_l2_protection_fault_status, 751 .get_invalidate_req = mmhub_v4_2_0_get_invalidate_req, 752 }; 753 754 static void mmhub_v4_2_0_mid_init(struct amdgpu_device *adev, 755 uint32_t mid_mask) 756 { 757 struct amdgpu_vmhub *hub; 758 int i; 759 760 for_each_inst(i, mid_mask) { 761 hub = &adev->vmhub[AMDGPU_MMHUB0(i)]; 762 763 hub->ctx0_ptb_addr_lo32 = 764 SOC15_REG_OFFSET(MMHUB, GET_INST(MMHUB, i), 765 regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32); 766 hub->ctx0_ptb_addr_hi32 = 767 SOC15_REG_OFFSET(MMHUB, GET_INST(MMHUB, i), 768 regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32); 769 hub->vm_inv_eng0_sem = 770 SOC15_REG_OFFSET(MMHUB, GET_INST(MMHUB, i), 771 regMMVM_INVALIDATE_ENG0_SEM); 772 hub->vm_inv_eng0_req = 773 SOC15_REG_OFFSET(MMHUB, GET_INST(MMHUB, i), 774 regMMVM_INVALIDATE_ENG0_REQ); 775 hub->vm_inv_eng0_ack = 776 SOC15_REG_OFFSET(MMHUB, GET_INST(MMHUB, i), 777 regMMVM_INVALIDATE_ENG0_ACK); 778 hub->vm_context0_cntl = 779 SOC15_REG_OFFSET(MMHUB, GET_INST(MMHUB, i), 780 regMMVM_CONTEXT0_CNTL); 781 /* TODO: add a new member to accomandate additional fault status/cntl reg */ 782 hub->vm_l2_pro_fault_status = 783 SOC15_REG_OFFSET(MMHUB, GET_INST(MMHUB, i), 784 regMMVM_L2_PROTECTION_FAULT_STATUS_LO32); 785 hub->vm_l2_pro_fault_cntl = 786 SOC15_REG_OFFSET(MMHUB, GET_INST(MMHUB, i), 787 regMMVM_L2_PROTECTION_FAULT_CNTL_LO32); 788 789 hub->ctx_distance = regMMVM_CONTEXT1_CNTL - regMMVM_CONTEXT0_CNTL; 790 hub->ctx_addr_distance = regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 - 791 regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32; 792 hub->eng_distance = regMMVM_INVALIDATE_ENG1_REQ - 793 regMMVM_INVALIDATE_ENG0_REQ; 794 hub->eng_addr_distance = regMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 - 795 regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32; 796 797 hub->vm_cntx_cntl_vm_fault = MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 798 MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 799 MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 800 MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 801 MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 802 MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 803 MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; 804 805 hub->vm_l2_bank_select_reserved_cid2 = 806 SOC15_REG_OFFSET(MMHUB, GET_INST(MMHUB, i), regMMVM_L2_BANK_SELECT_RESERVED_CID2); 807 808 hub->vm_contexts_disable = 809 SOC15_REG_OFFSET(MMHUB, GET_INST(MMHUB, i), regMMVM_CONTEXTS_DISABLE); 810 811 hub->vmhub_funcs = &mmhub_v4_2_0_vmhub_funcs; 812 } 813 } 814 815 static void mmhub_v4_2_0_init(struct amdgpu_device *adev) 816 { 817 uint32_t mid_mask; 818 819 mid_mask = adev->aid_mask; 820 mmhub_v4_2_0_mid_init(adev, mid_mask); 821 822 amdgpu_mmhub_init_client_info(&adev->mmhub, 823 mmhub_client_ids_v4_2_0, 824 ARRAY_SIZE(mmhub_client_ids_v4_2_0)); 825 } 826 827 static void 828 mmhub_v4_2_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 829 bool enable) 830 { 831 uint32_t def, data; 832 uint32_t def1, data1, def2 = 0, data2 = 0; 833 def = data = RREG32_SOC15(MMHUB, GET_INST(MMHUB, 0), regMM_ATC_L2_MISC_CG); 834 def1 = data1 = RREG32_SOC15(MMHUB, GET_INST(MMHUB, 0), regDAGB0_CNTL_MISC2); 835 def2 = data2 = RREG32_SOC15(MMHUB, GET_INST(MMHUB, 0), regDAGB1_CNTL_MISC2); 836 837 if (enable) { 838 data |= MM_ATC_L2_MISC_CG__ENABLE_MASK; 839 data1 &= ~(DAGB0_CNTL_MISC2__DISABLE_RDRET_TAP_CHAIN_FGCG_MASK | 840 DAGB0_CNTL_MISC2__DISABLE_WRRET_TAP_CHAIN_FGCG_MASK); 841 842 data2 &= ~(DAGB1_CNTL_MISC2__DISABLE_RDRET_TAP_CHAIN_FGCG_MASK | 843 DAGB1_CNTL_MISC2__DISABLE_WRRET_TAP_CHAIN_FGCG_MASK); 844 } else { 845 data &= ~MM_ATC_L2_MISC_CG__ENABLE_MASK; 846 data1 |= (DAGB0_CNTL_MISC2__DISABLE_RDRET_TAP_CHAIN_FGCG_MASK | 847 DAGB0_CNTL_MISC2__DISABLE_WRRET_TAP_CHAIN_FGCG_MASK); 848 849 data2 |= (DAGB1_CNTL_MISC2__DISABLE_RDRET_TAP_CHAIN_FGCG_MASK | 850 DAGB1_CNTL_MISC2__DISABLE_WRRET_TAP_CHAIN_FGCG_MASK); 851 } 852 853 if (def != data) 854 WREG32_SOC15(MMHUB, GET_INST(MMHUB, 0), regMM_ATC_L2_MISC_CG, data); 855 if (def1 != data1) 856 WREG32_SOC15(MMHUB, GET_INST(MMHUB, 0), regDAGB0_CNTL_MISC2, data1); 857 858 if (def2 != data2) 859 WREG32_SOC15(MMHUB, GET_INST(MMHUB, 0), regDAGB1_CNTL_MISC2, data2); 860 } 861 862 static void 863 mmhub_v4_2_0_update_medium_grain_light_sleep(struct amdgpu_device *adev, 864 bool enable) 865 { 866 uint32_t def, data; 867 868 def = data = RREG32_SOC15(MMHUB, GET_INST(MMHUB, 0), regMM_ATC_L2_MISC_CG); 869 870 if (enable) 871 data |= MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK; 872 else 873 data &= ~MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK; 874 875 if (def != data) 876 WREG32_SOC15(MMHUB, GET_INST(MMHUB, 0), regMM_ATC_L2_MISC_CG, data); 877 } 878 879 static int mmhub_v4_2_0_set_clockgating(struct amdgpu_device *adev, 880 enum amd_clockgating_state state) 881 { 882 if (amdgpu_sriov_vf(adev)) 883 return 0; 884 885 if (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG) 886 mmhub_v4_2_0_update_medium_grain_clock_gating(adev, 887 state == AMD_CG_STATE_GATE); 888 889 if (adev->cg_flags & AMD_CG_SUPPORT_MC_LS) 890 mmhub_v4_2_0_update_medium_grain_light_sleep(adev, 891 state == AMD_CG_STATE_GATE); 892 893 return 0; 894 } 895 896 static void mmhub_v4_2_0_get_clockgating(struct amdgpu_device *adev, u64 *flags) 897 { 898 int data; 899 900 if (amdgpu_sriov_vf(adev)) 901 *flags = 0; 902 903 data = RREG32_SOC15(MMHUB, GET_INST(MMHUB, 0), regMM_ATC_L2_MISC_CG); 904 905 /* AMD_CG_SUPPORT_MC_MGCG */ 906 if (data & MM_ATC_L2_MISC_CG__ENABLE_MASK) 907 *flags |= AMD_CG_SUPPORT_MC_MGCG; 908 909 /* AMD_CG_SUPPORT_MC_LS */ 910 if (data & MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK) 911 *flags |= AMD_CG_SUPPORT_MC_LS; 912 } 913 914 const struct amdgpu_mmhub_funcs mmhub_v4_2_0_funcs = { 915 .init = mmhub_v4_2_0_init, 916 .get_fb_location = mmhub_v4_2_0_get_fb_location, 917 .get_mc_fb_offset = mmhub_v4_2_0_get_mc_fb_offset, 918 .setup_vm_pt_regs = mmhub_v4_2_0_setup_vm_pt_regs, 919 .gart_enable = mmhub_v4_2_0_gart_enable, 920 .gart_disable = mmhub_v4_2_0_gart_disable, 921 .set_fault_enable_default = mmhub_v4_2_0_set_fault_enable_default, 922 .set_clockgating = mmhub_v4_2_0_set_clockgating, 923 .get_clockgating = mmhub_v4_2_0_get_clockgating, 924 .get_xgmi_info = mmhub_v4_2_0_get_xgmi_info, 925 }; 926 927 static int mmhub_v4_2_0_xcp_resume(void *handle, uint32_t inst_mask) 928 { 929 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 930 bool value; 931 932 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) 933 value = false; 934 else 935 value = true; 936 937 mmhub_v4_2_0_mid_set_fault_enable_default(adev, value, inst_mask); 938 939 if (!amdgpu_sriov_vf(adev)) 940 return mmhub_v4_2_0_mid_gart_enable(adev, inst_mask); 941 942 return 0; 943 } 944 945 static int mmhub_v4_2_0_xcp_suspend(void *handle, uint32_t inst_mask) 946 { 947 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 948 949 if (!amdgpu_sriov_vf(adev)) 950 mmhub_v4_2_0_mid_gart_disable(adev, inst_mask); 951 952 return 0; 953 } 954 955 struct amdgpu_xcp_ip_funcs mmhub_v4_2_0_xcp_funcs = { 956 .suspend = &mmhub_v4_2_0_xcp_suspend, 957 .resume = &mmhub_v4_2_0_xcp_resume 958 }; 959