1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "amdgpu.h" 25 #include "mmhub_v4_1_0.h" 26 27 #include "mmhub/mmhub_4_1_0_offset.h" 28 #include "mmhub/mmhub_4_1_0_sh_mask.h" 29 30 #include "soc15_common.h" 31 #include "soc24_enum.h" 32 33 #define regMMVM_L2_CNTL3_DEFAULT 0x80100007 34 #define regMMVM_L2_CNTL4_DEFAULT 0x000000c1 35 #define regMMVM_L2_CNTL5_DEFAULT 0x00003fe0 36 37 static const char *mmhub_client_ids_v4_1_0[][2] = { 38 [0][0] = "VMC", 39 [4][0] = "DCEDMC", 40 [6][0] = "MP0", 41 [7][0] = "MP1", 42 [8][0] = "MPIO", 43 [16][0] = "LSDMA", 44 [17][0] = "JPEG", 45 [19][0] = "VCNU", 46 [22][0] = "VSCH", 47 [23][0] = "HDP", 48 [32+23][0] = "VCNRD", 49 [3][1] = "DCEDWB", 50 [4][1] = "DCEDMC", 51 [6][1] = "MP0", 52 [7][1] = "MP1", 53 [8][1] = "MPIO", 54 [10][1] = "DBGU0", 55 [11][1] = "DBGU1", 56 [12][1] = "DBGUNBIO", 57 [14][1] = "XDP", 58 [15][1] = "OSSSYS", 59 [16][1] = "LSDMA", 60 [17][1] = "JPEG", 61 [18][1] = "VCNWR", 62 [19][1] = "VCNU", 63 [22][1] = "VSCH", 64 [23][1] = "HDP", 65 }; 66 67 static uint32_t mmhub_v4_1_0_get_invalidate_req(unsigned int vmid, 68 uint32_t flush_type) 69 { 70 u32 req = 0; 71 72 /* invalidate using legacy mode on vmid*/ 73 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, 74 PER_VMID_INVALIDATE_REQ, 1 << vmid); 75 /* Only use legacy inv on mmhub side */ 76 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, 0); 77 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); 78 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); 79 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); 80 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); 81 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); 82 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, 83 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0); 84 85 return req; 86 } 87 88 static void 89 mmhub_v4_1_0_print_l2_protection_fault_status(struct amdgpu_device *adev, 90 uint32_t status) 91 { 92 uint32_t cid, rw; 93 const char *mmhub_cid = NULL; 94 95 cid = REG_GET_FIELD(status, 96 MMVM_L2_PROTECTION_FAULT_STATUS_LO32, CID); 97 rw = REG_GET_FIELD(status, 98 MMVM_L2_PROTECTION_FAULT_STATUS_LO32, RW); 99 100 dev_err(adev->dev, 101 "MMVM_L2_PROTECTION_FAULT_STATUS_LO32:0x%08X\n", 102 status); 103 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { 104 case IP_VERSION(4, 1, 0): 105 mmhub_cid = mmhub_client_ids_v4_1_0[cid][rw]; 106 break; 107 default: 108 mmhub_cid = NULL; 109 break; 110 } 111 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", 112 mmhub_cid ? mmhub_cid : "unknown", cid); 113 dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n", 114 REG_GET_FIELD(status, 115 MMVM_L2_PROTECTION_FAULT_STATUS_LO32, MORE_FAULTS)); 116 dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n", 117 REG_GET_FIELD(status, 118 MMVM_L2_PROTECTION_FAULT_STATUS_LO32, WALKER_ERROR)); 119 dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n", 120 REG_GET_FIELD(status, 121 MMVM_L2_PROTECTION_FAULT_STATUS_LO32, PERMISSION_FAULTS)); 122 dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n", 123 REG_GET_FIELD(status, 124 MMVM_L2_PROTECTION_FAULT_STATUS_LO32, MAPPING_ERROR)); 125 dev_err(adev->dev, "\t RW: 0x%x\n", rw); 126 } 127 128 static void mmhub_v4_1_0_setup_vm_pt_regs(struct amdgpu_device *adev, 129 uint32_t vmid, uint64_t page_table_base) 130 { 131 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)]; 132 133 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, 134 hub->ctx_addr_distance * vmid, 135 lower_32_bits(page_table_base)); 136 137 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, 138 hub->ctx_addr_distance * vmid, 139 upper_32_bits(page_table_base)); 140 } 141 142 static void mmhub_v4_1_0_init_gart_aperture_regs(struct amdgpu_device *adev) 143 { 144 uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); 145 146 mmhub_v4_1_0_setup_vm_pt_regs(adev, 0, pt_base); 147 148 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, 149 (u32)(adev->gmc.gart_start >> 12)); 150 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, 151 (u32)(adev->gmc.gart_start >> 44)); 152 153 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, 154 (u32)(adev->gmc.gart_end >> 12)); 155 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, 156 (u32)(adev->gmc.gart_end >> 44)); 157 } 158 159 static void mmhub_v4_1_0_init_system_aperture_regs(struct amdgpu_device *adev) 160 { 161 uint64_t value; 162 uint32_t tmp; 163 164 /* 165 * the new L1 policy will block SRIOV guest from writing 166 * these regs, and they will be programed at host. 167 * so skip programing these regs. 168 */ 169 if (amdgpu_sriov_vf(adev)) 170 return; 171 172 /* Program the AGP BAR */ 173 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BASE, 0); 174 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); 175 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); 176 177 /* Program the system aperture low logical page number. */ 178 WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR, 179 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); 180 WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 181 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); 182 183 /* Set default page address. */ 184 value = adev->mem_scratch.gpu_addr - adev->gmc.vram_start + 185 adev->vm_manager.vram_base_offset; 186 WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 187 (u32)(value >> 12)); 188 WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 189 (u32)(value >> 44)); 190 191 /* Program "protection fault". */ 192 WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, 193 (u32)(adev->dummy_page_addr >> 12)); 194 WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, 195 (u32)((u64)adev->dummy_page_addr >> 44)); 196 197 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2); 198 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2, 199 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); 200 WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2, tmp); 201 } 202 203 static void mmhub_v4_1_0_init_tlb_regs(struct amdgpu_device *adev) 204 { 205 uint32_t tmp; 206 207 /* Setup TLB control */ 208 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); 209 210 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); 211 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); 212 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, 213 ENABLE_ADVANCED_DRIVER_MODEL, 1); 214 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, 215 SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); 216 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0); 217 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, 218 MTYPE, MTYPE_UC); /* UC, uncached */ 219 220 WREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL, tmp); 221 } 222 223 static void mmhub_v4_1_0_init_cache_regs(struct amdgpu_device *adev) 224 { 225 uint32_t tmp; 226 227 /* These registers are not accessible to VF-SRIOV. 228 * The PF will program them instead. 229 */ 230 if (amdgpu_sriov_vf(adev)) 231 return; 232 233 /* Setup L2 cache */ 234 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL); 235 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1); 236 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0); 237 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, 238 ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1); 239 /* XXX for emulation, Refer to closed source code.*/ 240 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE, 241 0); 242 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0); 243 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); 244 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0); 245 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL, tmp); 246 247 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2); 248 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); 249 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); 250 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2, tmp); 251 252 tmp = regMMVM_L2_CNTL3_DEFAULT; 253 if (adev->gmc.translate_further) { 254 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12); 255 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, 256 L2_CACHE_BIGK_FRAGMENT_SIZE, 9); 257 } else { 258 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9); 259 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, 260 L2_CACHE_BIGK_FRAGMENT_SIZE, 6); 261 } 262 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL3, tmp); 263 264 tmp = regMMVM_L2_CNTL4_DEFAULT; 265 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0); 266 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0); 267 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL4, tmp); 268 269 tmp = regMMVM_L2_CNTL5_DEFAULT; 270 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0); 271 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL5, tmp); 272 } 273 274 static void mmhub_v4_1_0_enable_system_domain(struct amdgpu_device *adev) 275 { 276 uint32_t tmp; 277 278 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL); 279 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 280 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); 281 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, 282 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0); 283 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL, tmp); 284 } 285 286 static void mmhub_v4_1_0_disable_identity_aperture(struct amdgpu_device *adev) 287 { 288 /* These registers are not accessible to VF-SRIOV. 289 * The PF will program them instead. 290 */ 291 if (amdgpu_sriov_vf(adev)) 292 return; 293 294 WREG32_SOC15(MMHUB, 0, 295 regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32, 296 0xFFFFFFFF); 297 WREG32_SOC15(MMHUB, 0, 298 regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32, 299 0x0000000F); 300 301 WREG32_SOC15(MMHUB, 0, 302 regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 0); 303 WREG32_SOC15(MMHUB, 0, 304 regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 0); 305 306 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 307 0); 308 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 309 0); 310 } 311 312 static void mmhub_v4_1_0_setup_vmid_config(struct amdgpu_device *adev) 313 { 314 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)]; 315 int i; 316 uint32_t tmp; 317 318 for (i = 0; i <= 14; i++) { 319 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL, i); 320 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); 321 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 322 adev->vm_manager.num_level); 323 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 324 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 325 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 326 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 327 1); 328 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 329 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 330 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 331 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 332 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 333 READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 334 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 335 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 336 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 337 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 338 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 339 PAGE_TABLE_BLOCK_SIZE, 340 adev->vm_manager.block_size - 9); 341 /* Send no-retry XNACK on fault to suppress VM fault storm. */ 342 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 343 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 344 !amdgpu_noretry); 345 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL, 346 i * hub->ctx_distance, tmp); 347 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, 348 i * hub->ctx_addr_distance, 0); 349 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, 350 i * hub->ctx_addr_distance, 0); 351 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, 352 i * hub->ctx_addr_distance, 353 lower_32_bits(adev->vm_manager.max_pfn - 1)); 354 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, 355 i * hub->ctx_addr_distance, 356 upper_32_bits(adev->vm_manager.max_pfn - 1)); 357 } 358 359 hub->vm_cntx_cntl = tmp; 360 } 361 362 static void mmhub_v4_1_0_program_invalidation(struct amdgpu_device *adev) 363 { 364 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)]; 365 unsigned i; 366 367 for (i = 0; i < 18; ++i) { 368 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32, 369 i * hub->eng_addr_distance, 0xffffffff); 370 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32, 371 i * hub->eng_addr_distance, 0x1f); 372 } 373 } 374 375 static int mmhub_v4_1_0_gart_enable(struct amdgpu_device *adev) 376 { 377 /* GART Enable. */ 378 mmhub_v4_1_0_init_gart_aperture_regs(adev); 379 mmhub_v4_1_0_init_system_aperture_regs(adev); 380 mmhub_v4_1_0_init_tlb_regs(adev); 381 mmhub_v4_1_0_init_cache_regs(adev); 382 383 mmhub_v4_1_0_enable_system_domain(adev); 384 mmhub_v4_1_0_disable_identity_aperture(adev); 385 mmhub_v4_1_0_setup_vmid_config(adev); 386 mmhub_v4_1_0_program_invalidation(adev); 387 388 return 0; 389 } 390 391 static void mmhub_v4_1_0_gart_disable(struct amdgpu_device *adev) 392 { 393 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)]; 394 u32 tmp; 395 u32 i; 396 397 /* Disable all tables */ 398 for (i = 0; i < 16; i++) 399 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_CNTL, 400 i * hub->ctx_distance, 0); 401 402 /* Setup TLB control */ 403 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); 404 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); 405 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, 406 ENABLE_ADVANCED_DRIVER_MODEL, 0); 407 WREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL, tmp); 408 409 /* Setup L2 cache */ 410 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL); 411 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0); 412 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL, tmp); 413 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL3, 0); 414 } 415 416 /** 417 * mmhub_v4_1_0_set_fault_enable_default - update GART/VM fault handling 418 * 419 * @adev: amdgpu_device pointer 420 * @value: true redirects VM faults to the default page 421 */ 422 static void 423 mmhub_v4_1_0_set_fault_enable_default(struct amdgpu_device *adev, bool value) 424 { 425 u32 tmp; 426 427 /* These registers are not accessible to VF-SRIOV. 428 * The PF will program them instead. 429 */ 430 if (amdgpu_sriov_vf(adev)) 431 return; 432 433 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL); 434 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 435 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 436 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 437 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); 438 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 439 PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value); 440 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 441 PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value); 442 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 443 TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT, 444 value); 445 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 446 NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value); 447 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 448 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 449 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 450 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); 451 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 452 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); 453 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 454 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 455 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 456 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 457 if (!value) { 458 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 459 CRASH_ON_NO_RETRY_FAULT, 1); 460 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 461 CRASH_ON_RETRY_FAULT, 1); 462 } 463 WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL, tmp); 464 } 465 466 static const struct amdgpu_vmhub_funcs mmhub_v4_1_0_vmhub_funcs = { 467 .print_l2_protection_fault_status = mmhub_v4_1_0_print_l2_protection_fault_status, 468 .get_invalidate_req = mmhub_v4_1_0_get_invalidate_req, 469 }; 470 471 static void mmhub_v4_1_0_init(struct amdgpu_device *adev) 472 { 473 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)]; 474 475 hub->ctx0_ptb_addr_lo32 = 476 SOC15_REG_OFFSET(MMHUB, 0, 477 regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32); 478 hub->ctx0_ptb_addr_hi32 = 479 SOC15_REG_OFFSET(MMHUB, 0, 480 regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32); 481 hub->vm_inv_eng0_sem = 482 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_SEM); 483 hub->vm_inv_eng0_req = 484 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_REQ); 485 hub->vm_inv_eng0_ack = 486 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ACK); 487 hub->vm_context0_cntl = 488 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_CNTL); 489 hub->vm_l2_pro_fault_status = 490 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_STATUS_LO32); 491 hub->vm_l2_pro_fault_cntl = 492 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL); 493 494 hub->ctx_distance = regMMVM_CONTEXT1_CNTL - regMMVM_CONTEXT0_CNTL; 495 hub->ctx_addr_distance = regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 - 496 regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32; 497 hub->eng_distance = regMMVM_INVALIDATE_ENG1_REQ - 498 regMMVM_INVALIDATE_ENG0_REQ; 499 hub->eng_addr_distance = regMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 - 500 regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32; 501 502 hub->vm_cntx_cntl_vm_fault = MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 503 MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 504 MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 505 MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 506 MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 507 MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 508 MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; 509 510 hub->vm_l2_bank_select_reserved_cid2 = 511 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_L2_BANK_SELECT_RESERVED_CID2); 512 513 hub->vm_contexts_disable = 514 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_CONTEXTS_DISABLE); 515 516 hub->vmhub_funcs = &mmhub_v4_1_0_vmhub_funcs; 517 } 518 519 static u64 mmhub_v4_1_0_get_fb_location(struct amdgpu_device *adev) 520 { 521 u64 base; 522 523 base = RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_LOCATION_BASE); 524 525 base &= MMMC_VM_FB_LOCATION_BASE__FB_BASE_MASK; 526 base <<= 24; 527 528 return base; 529 } 530 531 static u64 mmhub_v4_1_0_get_mc_fb_offset(struct amdgpu_device *adev) 532 { 533 return (u64)RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_OFFSET) << 24; 534 } 535 536 static void 537 mmhub_v4_1_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 538 bool enable) 539 { 540 #if 0 541 uint32_t def, data; 542 #endif 543 uint32_t def1, data1, def2 = 0, data2 = 0; 544 #if 0 545 def = data = RREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG); 546 #endif 547 def1 = data1 = RREG32_SOC15(MMHUB, 0, regDAGB0_CNTL_MISC2); 548 def2 = data2 = RREG32_SOC15(MMHUB, 0, regDAGB1_CNTL_MISC2); 549 550 if (enable) { 551 #if 0 552 data |= MM_ATC_L2_MISC_CG__ENABLE_MASK; 553 #endif 554 data1 &= ~(DAGB0_CNTL_MISC2__DISABLE_RDRET_TAP_CHAIN_FGCG_MASK | 555 DAGB0_CNTL_MISC2__DISABLE_WRRET_TAP_CHAIN_FGCG_MASK); 556 557 data2 &= ~(DAGB1_CNTL_MISC2__DISABLE_RDRET_TAP_CHAIN_FGCG_MASK | 558 DAGB1_CNTL_MISC2__DISABLE_WRRET_TAP_CHAIN_FGCG_MASK); 559 } else { 560 #if 0 561 data &= ~MM_ATC_L2_MISC_CG__ENABLE_MASK; 562 #endif 563 data1 |= (DAGB0_CNTL_MISC2__DISABLE_RDRET_TAP_CHAIN_FGCG_MASK | 564 DAGB0_CNTL_MISC2__DISABLE_WRRET_TAP_CHAIN_FGCG_MASK); 565 566 data2 |= (DAGB1_CNTL_MISC2__DISABLE_RDRET_TAP_CHAIN_FGCG_MASK | 567 DAGB1_CNTL_MISC2__DISABLE_WRRET_TAP_CHAIN_FGCG_MASK); 568 } 569 570 #if 0 571 if (def != data) 572 WREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG, data); 573 #endif 574 if (def1 != data1) 575 WREG32_SOC15(MMHUB, 0, regDAGB0_CNTL_MISC2, data1); 576 577 if (def2 != data2) 578 WREG32_SOC15(MMHUB, 0, regDAGB1_CNTL_MISC2, data2); 579 } 580 581 static void 582 mmhub_v4_1_0_update_medium_grain_light_sleep(struct amdgpu_device *adev, 583 bool enable) 584 { 585 #if 0 586 uint32_t def, data; 587 588 def = data = RREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG); 589 590 if (enable) 591 data |= MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK; 592 else 593 data &= ~MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK; 594 595 if (def != data) 596 WREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG, data); 597 #endif 598 } 599 600 static int mmhub_v4_1_0_set_clockgating(struct amdgpu_device *adev, 601 enum amd_clockgating_state state) 602 { 603 if (amdgpu_sriov_vf(adev)) 604 return 0; 605 606 if (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG) 607 mmhub_v4_1_0_update_medium_grain_clock_gating(adev, 608 state == AMD_CG_STATE_GATE); 609 610 if (adev->cg_flags & AMD_CG_SUPPORT_MC_LS) 611 mmhub_v4_1_0_update_medium_grain_light_sleep(adev, 612 state == AMD_CG_STATE_GATE); 613 614 return 0; 615 } 616 617 static void mmhub_v4_1_0_get_clockgating(struct amdgpu_device *adev, u64 *flags) 618 { 619 #if 0 620 int data; 621 622 if (amdgpu_sriov_vf(adev)) 623 *flags = 0; 624 625 data = RREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG); 626 627 /* AMD_CG_SUPPORT_MC_MGCG */ 628 if (data & MM_ATC_L2_MISC_CG__ENABLE_MASK) 629 *flags |= AMD_CG_SUPPORT_MC_MGCG; 630 631 /* AMD_CG_SUPPORT_MC_LS */ 632 if (data & MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK) 633 *flags |= AMD_CG_SUPPORT_MC_LS; 634 #endif 635 } 636 637 const struct amdgpu_mmhub_funcs mmhub_v4_1_0_funcs = { 638 .init = mmhub_v4_1_0_init, 639 .get_fb_location = mmhub_v4_1_0_get_fb_location, 640 .get_mc_fb_offset = mmhub_v4_1_0_get_mc_fb_offset, 641 .gart_enable = mmhub_v4_1_0_gart_enable, 642 .set_fault_enable_default = mmhub_v4_1_0_set_fault_enable_default, 643 .gart_disable = mmhub_v4_1_0_gart_disable, 644 .set_clockgating = mmhub_v4_1_0_set_clockgating, 645 .get_clockgating = mmhub_v4_1_0_get_clockgating, 646 .setup_vm_pt_regs = mmhub_v4_1_0_setup_vm_pt_regs, 647 }; 648