1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "amdgpu.h" 25 #include "mmhub_v3_3.h" 26 27 #include "mmhub/mmhub_3_3_0_offset.h" 28 #include "mmhub/mmhub_3_3_0_sh_mask.h" 29 30 #include "navi10_enum.h" 31 #include "soc15_common.h" 32 33 #define regMMVM_L2_CNTL3_DEFAULT 0x80100007 34 #define regMMVM_L2_CNTL4_DEFAULT 0x000000c1 35 #define regMMVM_L2_CNTL5_DEFAULT 0x00003fe0 36 37 static const char *mmhub_client_ids_v3_3[][2] = { 38 [0][0] = "VMC", 39 [4][0] = "DCEDMC", 40 [6][0] = "MP0", 41 [7][0] = "MP1", 42 [8][0] = "MPM", 43 [24][0] = "HDP", 44 [25][0] = "LSDMA", 45 [26][0] = "JPEG", 46 [27][0] = "VPE", 47 [29][0] = "VCNU", 48 [30][0] = "VCN", 49 [3][1] = "DCEDWB", 50 [4][1] = "DCEDMC", 51 [6][1] = "MP0", 52 [7][1] = "MP1", 53 [8][1] = "MPM", 54 [21][1] = "OSSSYS", 55 [24][1] = "HDP", 56 [25][1] = "LSDMA", 57 [26][1] = "JPEG", 58 [27][1] = "VPE", 59 [29][1] = "VCNU", 60 [30][1] = "VCN", 61 }; 62 63 static uint32_t mmhub_v3_3_get_invalidate_req(unsigned int vmid, 64 uint32_t flush_type) 65 { 66 u32 req = 0; 67 68 /* invalidate using legacy mode on vmid*/ 69 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, 70 PER_VMID_INVALIDATE_REQ, 1 << vmid); 71 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type ? : 1); 72 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); 73 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); 74 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); 75 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); 76 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); 77 req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, 78 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0); 79 80 return req; 81 } 82 83 static void 84 mmhub_v3_3_print_l2_protection_fault_status(struct amdgpu_device *adev, 85 uint32_t status) 86 { 87 uint32_t cid, rw; 88 const char *mmhub_cid = NULL; 89 90 cid = REG_GET_FIELD(status, 91 MMVM_L2_PROTECTION_FAULT_STATUS, CID); 92 rw = REG_GET_FIELD(status, 93 MMVM_L2_PROTECTION_FAULT_STATUS, RW); 94 95 dev_err(adev->dev, 96 "MMVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", 97 status); 98 99 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { 100 case IP_VERSION(3, 3, 0): 101 case IP_VERSION(3, 3, 1): 102 mmhub_cid = mmhub_client_ids_v3_3[cid][rw]; 103 break; 104 default: 105 mmhub_cid = NULL; 106 break; 107 } 108 109 if (!mmhub_cid && cid == 0x140) 110 mmhub_cid = "UMSCH"; 111 112 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", 113 mmhub_cid ? mmhub_cid : "unknown", cid); 114 dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n", 115 REG_GET_FIELD(status, 116 MMVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS)); 117 dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n", 118 REG_GET_FIELD(status, 119 MMVM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR)); 120 dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n", 121 REG_GET_FIELD(status, 122 MMVM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS)); 123 dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n", 124 REG_GET_FIELD(status, 125 MMVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR)); 126 dev_err(adev->dev, "\t RW: 0x%x\n", rw); 127 } 128 129 static void mmhub_v3_3_setup_vm_pt_regs(struct amdgpu_device *adev, 130 uint32_t vmid, 131 uint64_t page_table_base) 132 { 133 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)]; 134 135 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, 136 hub->ctx_addr_distance * vmid, 137 lower_32_bits(page_table_base)); 138 139 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, 140 hub->ctx_addr_distance * vmid, 141 upper_32_bits(page_table_base)); 142 143 } 144 145 static void mmhub_v3_3_init_gart_aperture_regs(struct amdgpu_device *adev) 146 { 147 uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); 148 149 mmhub_v3_3_setup_vm_pt_regs(adev, 0, pt_base); 150 151 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, 152 (u32)(adev->gmc.gart_start >> 12)); 153 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, 154 (u32)(adev->gmc.gart_start >> 44)); 155 156 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, 157 (u32)(adev->gmc.gart_end >> 12)); 158 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, 159 (u32)(adev->gmc.gart_end >> 44)); 160 } 161 162 static void mmhub_v3_3_init_system_aperture_regs(struct amdgpu_device *adev) 163 { 164 uint64_t value; 165 uint32_t tmp; 166 167 /* Program the AGP BAR */ 168 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BASE, 0); 169 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); 170 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); 171 172 /* 173 * the new L1 policy will block SRIOV guest from writing 174 * these regs, and they will be programed at host. 175 * so skip programing these regs. 176 */ 177 /* Program the system aperture low logical page number. */ 178 WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR, 179 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); 180 WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 181 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); 182 183 /* Set default page address. */ 184 value = amdgpu_gmc_vram_mc2pa(adev, adev->mem_scratch.gpu_addr); 185 WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 186 (u32)(value >> 12)); 187 WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 188 (u32)(value >> 44)); 189 190 /* Program "protection fault". */ 191 WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, 192 (u32)(adev->dummy_page_addr >> 12)); 193 WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, 194 (u32)((u64)adev->dummy_page_addr >> 44)); 195 196 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2); 197 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2, 198 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); 199 WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2, tmp); 200 } 201 202 static void mmhub_v3_3_init_tlb_regs(struct amdgpu_device *adev) 203 { 204 uint32_t tmp; 205 206 /* Setup TLB control */ 207 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); 208 209 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); 210 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); 211 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, 212 ENABLE_ADVANCED_DRIVER_MODEL, 1); 213 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, 214 SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); 215 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0); 216 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, 217 MTYPE, MTYPE_UC); /* UC, uncached */ 218 219 WREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL, tmp); 220 } 221 222 static void mmhub_v3_3_init_cache_regs(struct amdgpu_device *adev) 223 { 224 uint32_t tmp; 225 226 /* Setup L2 cache */ 227 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL); 228 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1); 229 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0); 230 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, 231 ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1); 232 /* XXX for emulation, Refer to closed source code.*/ 233 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE, 234 0); 235 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0); 236 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); 237 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0); 238 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL, tmp); 239 240 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2); 241 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); 242 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); 243 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2, tmp); 244 245 tmp = regMMVM_L2_CNTL3_DEFAULT; 246 if (adev->gmc.translate_further) { 247 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12); 248 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, 249 L2_CACHE_BIGK_FRAGMENT_SIZE, 9); 250 } else { 251 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9); 252 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, 253 L2_CACHE_BIGK_FRAGMENT_SIZE, 6); 254 } 255 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL3, tmp); 256 257 tmp = regMMVM_L2_CNTL4_DEFAULT; 258 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0); 259 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0); 260 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL4, tmp); 261 262 tmp = regMMVM_L2_CNTL5_DEFAULT; 263 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0); 264 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL5, tmp); 265 } 266 267 static void mmhub_v3_3_enable_system_domain(struct amdgpu_device *adev) 268 { 269 uint32_t tmp; 270 271 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL); 272 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 273 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); 274 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, 275 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0); 276 277 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL, tmp); 278 } 279 280 static void mmhub_v3_3_disable_identity_aperture(struct amdgpu_device *adev) 281 { 282 WREG32_SOC15(MMHUB, 0, 283 regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32, 284 0xFFFFFFFF); 285 WREG32_SOC15(MMHUB, 0, 286 regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32, 287 0x0000000F); 288 289 WREG32_SOC15(MMHUB, 0, 290 regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 0); 291 WREG32_SOC15(MMHUB, 0, 292 regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 0); 293 294 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 295 0); 296 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 297 0); 298 } 299 300 static void mmhub_v3_3_setup_vmid_config(struct amdgpu_device *adev) 301 { 302 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)]; 303 int i; 304 uint32_t tmp; 305 306 for (i = 0; i <= 14; i++) { 307 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL, i * hub->ctx_distance); 308 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); 309 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 310 adev->vm_manager.num_level); 311 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 312 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 313 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 314 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 315 1); 316 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 317 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 318 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 319 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 320 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 321 READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 322 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 323 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 324 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 325 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 326 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 327 PAGE_TABLE_BLOCK_SIZE, 328 adev->vm_manager.block_size - 9); 329 /* Send no-retry XNACK on fault to suppress VM fault storm. */ 330 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, 331 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 332 !amdgpu_noretry); 333 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL, 334 i * hub->ctx_distance, tmp); 335 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, 336 i * hub->ctx_addr_distance, 0); 337 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, 338 i * hub->ctx_addr_distance, 0); 339 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, 340 i * hub->ctx_addr_distance, 341 lower_32_bits(adev->vm_manager.max_pfn - 1)); 342 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, 343 i * hub->ctx_addr_distance, 344 upper_32_bits(adev->vm_manager.max_pfn - 1)); 345 } 346 347 hub->vm_cntx_cntl = tmp; 348 } 349 350 static void mmhub_v3_3_program_invalidation(struct amdgpu_device *adev) 351 { 352 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)]; 353 unsigned int i; 354 355 for (i = 0; i < 18; ++i) { 356 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32, 357 i * hub->eng_addr_distance, 0xffffffff); 358 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32, 359 i * hub->eng_addr_distance, 0x1f); 360 } 361 } 362 363 static int mmhub_v3_3_gart_enable(struct amdgpu_device *adev) 364 { 365 /* GART Enable. */ 366 mmhub_v3_3_init_gart_aperture_regs(adev); 367 mmhub_v3_3_init_system_aperture_regs(adev); 368 mmhub_v3_3_init_tlb_regs(adev); 369 mmhub_v3_3_init_cache_regs(adev); 370 371 mmhub_v3_3_enable_system_domain(adev); 372 mmhub_v3_3_disable_identity_aperture(adev); 373 mmhub_v3_3_setup_vmid_config(adev); 374 mmhub_v3_3_program_invalidation(adev); 375 376 return 0; 377 } 378 379 static void mmhub_v3_3_gart_disable(struct amdgpu_device *adev) 380 { 381 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)]; 382 u32 tmp; 383 u32 i; 384 385 /* Disable all tables */ 386 for (i = 0; i < 16; i++) 387 WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_CNTL, 388 i * hub->ctx_distance, 0); 389 390 /* Setup TLB control */ 391 tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); 392 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); 393 tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, 394 ENABLE_ADVANCED_DRIVER_MODEL, 0); 395 WREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL, tmp); 396 397 /* Setup L2 cache */ 398 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL); 399 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0); 400 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL, tmp); 401 WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL3, 0); 402 } 403 404 /** 405 * mmhub_v3_3_set_fault_enable_default - update GART/VM fault handling 406 * 407 * @adev: amdgpu_device pointer 408 * @value: true redirects VM faults to the default page 409 */ 410 static void mmhub_v3_3_set_fault_enable_default(struct amdgpu_device *adev, 411 bool value) 412 { 413 u32 tmp; 414 415 tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL); 416 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 417 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 418 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 419 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); 420 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 421 PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value); 422 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 423 PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value); 424 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 425 TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT, 426 value); 427 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 428 NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value); 429 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 430 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 431 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 432 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); 433 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 434 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); 435 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 436 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 437 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 438 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 439 if (!value) { 440 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 441 CRASH_ON_NO_RETRY_FAULT, 1); 442 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, 443 CRASH_ON_RETRY_FAULT, 1); 444 } 445 WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL, tmp); 446 } 447 448 static const struct amdgpu_vmhub_funcs mmhub_v3_3_vmhub_funcs = { 449 .print_l2_protection_fault_status = mmhub_v3_3_print_l2_protection_fault_status, 450 .get_invalidate_req = mmhub_v3_3_get_invalidate_req, 451 }; 452 453 static void mmhub_v3_3_init(struct amdgpu_device *adev) 454 { 455 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)]; 456 457 hub->ctx0_ptb_addr_lo32 = 458 SOC15_REG_OFFSET(MMHUB, 0, 459 regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32); 460 hub->ctx0_ptb_addr_hi32 = 461 SOC15_REG_OFFSET(MMHUB, 0, 462 regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32); 463 hub->vm_inv_eng0_sem = 464 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_SEM); 465 hub->vm_inv_eng0_req = 466 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_REQ); 467 hub->vm_inv_eng0_ack = 468 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ACK); 469 hub->vm_context0_cntl = 470 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_CNTL); 471 hub->vm_l2_pro_fault_status = 472 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_STATUS); 473 hub->vm_l2_pro_fault_cntl = 474 SOC15_REG_OFFSET(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL); 475 476 hub->ctx_distance = regMMVM_CONTEXT1_CNTL - regMMVM_CONTEXT0_CNTL; 477 hub->ctx_addr_distance = regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 - 478 regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32; 479 hub->eng_distance = regMMVM_INVALIDATE_ENG1_REQ - 480 regMMVM_INVALIDATE_ENG0_REQ; 481 hub->eng_addr_distance = regMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 - 482 regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32; 483 484 hub->vm_cntx_cntl_vm_fault = MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 485 MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 486 MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 487 MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 488 MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 489 MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 490 MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; 491 492 hub->vmhub_funcs = &mmhub_v3_3_vmhub_funcs; 493 } 494 495 static u64 mmhub_v3_3_get_fb_location(struct amdgpu_device *adev) 496 { 497 u64 base; 498 499 base = RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_LOCATION_BASE); 500 base &= MMMC_VM_FB_LOCATION_BASE__FB_BASE_MASK; 501 base <<= 24; 502 503 return base; 504 } 505 506 static u64 mmhub_v3_3_get_mc_fb_offset(struct amdgpu_device *adev) 507 { 508 u64 offset; 509 510 offset = RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_OFFSET); 511 offset &= MMMC_VM_FB_OFFSET__FB_OFFSET_MASK; 512 offset <<= 24; 513 514 return offset; 515 } 516 517 static void mmhub_v3_3_update_medium_grain_clock_gating(struct amdgpu_device *adev, 518 bool enable) 519 { 520 uint32_t def, data; 521 522 def = data = RREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG); 523 524 if (enable) 525 data |= MM_ATC_L2_MISC_CG__ENABLE_MASK; 526 else 527 data &= ~MM_ATC_L2_MISC_CG__ENABLE_MASK; 528 529 if (def != data) 530 WREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG, data); 531 } 532 533 static void mmhub_v3_3_update_medium_grain_light_sleep(struct amdgpu_device *adev, 534 bool enable) 535 { 536 uint32_t def, data; 537 538 def = data = RREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG); 539 540 if (enable) 541 data |= MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK; 542 else 543 data &= ~MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK; 544 545 if (def != data) 546 WREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG, data); 547 } 548 549 static int mmhub_v3_3_set_clockgating(struct amdgpu_device *adev, 550 enum amd_clockgating_state state) 551 { 552 if (amdgpu_sriov_vf(adev)) 553 return 0; 554 555 mmhub_v3_3_update_medium_grain_clock_gating(adev, 556 state == AMD_CG_STATE_GATE); 557 mmhub_v3_3_update_medium_grain_light_sleep(adev, 558 state == AMD_CG_STATE_GATE); 559 return 0; 560 } 561 562 static void mmhub_v3_3_get_clockgating(struct amdgpu_device *adev, u64 *flags) 563 { 564 int data; 565 566 if (amdgpu_sriov_vf(adev)) 567 *flags = 0; 568 569 data = RREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG); 570 571 /* AMD_CG_SUPPORT_MC_MGCG */ 572 if (data & MM_ATC_L2_MISC_CG__ENABLE_MASK) 573 *flags |= AMD_CG_SUPPORT_MC_MGCG; 574 575 /* AMD_CG_SUPPORT_MC_LS */ 576 if (data & MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK) 577 *flags |= AMD_CG_SUPPORT_MC_LS; 578 } 579 580 const struct amdgpu_mmhub_funcs mmhub_v3_3_funcs = { 581 .init = mmhub_v3_3_init, 582 .get_fb_location = mmhub_v3_3_get_fb_location, 583 .get_mc_fb_offset = mmhub_v3_3_get_mc_fb_offset, 584 .gart_enable = mmhub_v3_3_gart_enable, 585 .set_fault_enable_default = mmhub_v3_3_set_fault_enable_default, 586 .gart_disable = mmhub_v3_3_gart_disable, 587 .set_clockgating = mmhub_v3_3_set_clockgating, 588 .get_clockgating = mmhub_v3_3_get_clockgating, 589 .setup_vm_pt_regs = mmhub_v3_3_setup_vm_pt_regs, 590 }; 591